Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 9 | #include <delay.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 10 | #include "chip.h" |
Angel Pons | 2178b72 | 2020-05-31 00:55:35 +0200 | [diff] [blame] | 11 | #include "iobp.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include "pch.h" |
| 13 | |
| 14 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 15 | |
| 16 | static inline u32 sir_read(struct device *dev, int idx) |
| 17 | { |
| 18 | pci_write_config32(dev, SATA_SIRI, idx); |
| 19 | return pci_read_config32(dev, SATA_SIRD); |
| 20 | } |
| 21 | |
| 22 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 23 | { |
| 24 | pci_write_config32(dev, SATA_SIRI, idx); |
| 25 | pci_write_config32(dev, SATA_SIRD, value); |
| 26 | } |
| 27 | |
| 28 | static void sata_init(struct device *dev) |
| 29 | { |
| 30 | u32 reg32; |
| 31 | u16 reg16; |
| 32 | /* Get the chip configuration */ |
| 33 | config_t *config = dev->chip_info; |
| 34 | |
| 35 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 36 | |
| 37 | if (config == NULL) { |
| 38 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 39 | return; |
| 40 | } |
| 41 | |
| 42 | /* SATA configuration */ |
| 43 | |
Angel Pons | 1b85692 | 2020-10-30 15:30:48 +0100 | [diff] [blame^] | 44 | /* Enable memory space decoding for ABAR */ |
| 45 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 46 | |
| 47 | if (config->ide_legacy_combined) { |
| 48 | printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); |
| 49 | |
| 50 | /* No AHCI: clear AHCI base */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 51 | pci_write_config32(dev, 0x24, 0); |
| 52 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | /* And without AHCI BAR no memory decoding */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 54 | pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | |
| 56 | pci_write_config8(dev, 0x09, 0x80); |
| 57 | |
| 58 | /* Set timings */ |
| 59 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 60 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 61 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 62 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 63 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 64 | |
| 65 | /* Sync DMA */ |
| 66 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); |
| 67 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); |
| 68 | |
| 69 | /* Set IDE I/O Configuration */ |
| 70 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 71 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 72 | |
| 73 | /* Port enable */ |
| 74 | reg16 = pci_read_config16(dev, 0x92); |
| 75 | reg16 &= ~0x3f; |
| 76 | reg16 |= config->sata_port_map; |
| 77 | pci_write_config16(dev, 0x92, reg16); |
| 78 | |
| 79 | /* SATA Initialization register */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 80 | pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
Elyes HAOUAS | 70d79a4 | 2016-08-21 18:36:06 +0200 | [diff] [blame] | 81 | } else if (config->sata_ahci) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 82 | u32 *abar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | |
| 84 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
| 85 | |
| 86 | /* Set Interrupt Line */ |
| 87 | /* Interrupt Pin is set by D31IP.PIP */ |
| 88 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 89 | |
| 90 | /* Set timings */ |
| 91 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 92 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 93 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 94 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 95 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 96 | |
| 97 | /* Sync DMA */ |
| 98 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 99 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
| 100 | |
| 101 | /* Set IDE I/O Configuration */ |
| 102 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 103 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 104 | |
| 105 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 106 | reg16 = pci_read_config16(dev, 0x92); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 107 | reg16 &= ~0x3f; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | reg16 |= 0x8000 | config->sata_port_map; |
| 109 | pci_write_config16(dev, 0x92, reg16); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 110 | udelay(2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 112 | /* Setup register 98h */ |
| 113 | reg32 = pci_read_config16(dev, 0x98); |
| 114 | reg32 |= 1 << 19; /* BWG step 6 */ |
| 115 | reg32 |= 1 << 22; /* BWG step 5 */ |
| 116 | reg32 &= ~(0x3f << 7); |
| 117 | reg32 |= 0x04 << 7; /* BWG step 7 */ |
| 118 | reg32 |= 1 << 20; /* BWG step 8 */ |
| 119 | reg32 &= ~(0x03 << 5); |
| 120 | reg32 |= 1 << 5; /* BWG step 9 */ |
| 121 | reg32 |= 1 << 18; /* BWG step 10 */ |
| 122 | reg32 |= 1 << 29; /* BWG step 11 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 123 | if (pch_is_lp()) { |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 124 | reg32 &= ~((1 << 31) | (1 << 30)); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 125 | reg32 |= 1 << 23; |
| 126 | reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ |
| 127 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 128 | pci_write_config32(dev, 0x98, reg32); |
| 129 | |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 130 | /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ |
| 131 | pci_write_config16(dev, 0x9c, 1 << 5); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 132 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | /* SATA Initialization register */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 134 | reg32 = 0x183; |
| 135 | reg32 |= (config->sata_port_map ^ 0x3f) << 24; |
| 136 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 137 | pci_write_config32(dev, 0x94, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 138 | |
| 139 | /* Initialize AHCI memory-mapped space */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 140 | abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 141 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | /* CAP (HBA Capabilities) : enable power management */ |
| 143 | reg32 = read32(abar + 0x00); |
| 144 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 145 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 146 | if (pch_is_lp()) |
| 147 | reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | write32(abar + 0x00, reg32); |
| 149 | /* PI (Ports implemented) */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 150 | write32(abar + 0x03, config->sata_port_map); |
Angel Pons | 8cb8374 | 2020-10-17 18:28:29 +0200 | [diff] [blame] | 151 | (void)read32(abar + 0x03); /* Read back 1 */ |
| 152 | (void)read32(abar + 0x03); /* Read back 2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 153 | /* CAP2 (HBA Capabilities Extended)*/ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 154 | reg32 = read32(abar + 0x09); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 155 | /* Enable DEVSLP */ |
Marc Jones | e05cba2 | 2013-10-30 23:56:26 -0600 | [diff] [blame] | 156 | if (pch_is_lp()) { |
| 157 | if (config->sata_devslp_disable) |
| 158 | reg32 &= ~(1 << 3); |
| 159 | else |
| 160 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 161 | } else { |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 162 | reg32 &= ~0x00000002; |
Marc Jones | e05cba2 | 2013-10-30 23:56:26 -0600 | [diff] [blame] | 163 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 164 | write32(abar + 0x09, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 165 | } else { |
| 166 | printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); |
| 167 | |
| 168 | /* No AHCI: clear AHCI base */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 169 | pci_write_config32(dev, 0x24, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 170 | |
| 171 | /* And without AHCI BAR no memory decoding */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 172 | pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 174 | /* |
| 175 | * Native mode capable on both primary and secondary (0xa) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 176 | * or'ed with enabled (0x50) = 0xf |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 177 | * |
| 178 | * FIXME: Does not match the code. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 179 | */ |
| 180 | pci_write_config8(dev, 0x09, 0x8f); |
| 181 | |
| 182 | /* Set Interrupt Line */ |
| 183 | /* Interrupt Pin is set by D31IP.PIP */ |
| 184 | pci_write_config8(dev, INTR_LN, 0xff); |
| 185 | |
| 186 | /* Set timings */ |
| 187 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 188 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 189 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 190 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 191 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
| 192 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
| 193 | |
| 194 | /* Sync DMA */ |
| 195 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 196 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
| 197 | |
| 198 | /* Set IDE I/O Configuration */ |
| 199 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 200 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 201 | |
| 202 | /* Port enable */ |
| 203 | reg16 = pci_read_config16(dev, 0x92); |
| 204 | reg16 &= ~0x3f; |
| 205 | reg16 |= config->sata_port_map; |
| 206 | pci_write_config16(dev, 0x92, reg16); |
| 207 | |
| 208 | /* SATA Initialization register */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 209 | pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /* Set Gen3 Transmitter settings if needed */ |
| 213 | if (config->sata_port0_gen3_tx) |
| 214 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 215 | config->sata_port0_gen3_tx); |
| 216 | |
| 217 | if (config->sata_port1_gen3_tx) |
| 218 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 219 | config->sata_port1_gen3_tx); |
| 220 | |
Shawn Nematbakhsh | 2875227 | 2013-08-13 10:45:21 -0700 | [diff] [blame] | 221 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 222 | if (config->sata_port0_gen3_dtle) { |
| 223 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 224 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 225 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 226 | << SATA_DTLE_DATA_SHIFT); |
| 227 | |
| 228 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 229 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 230 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 231 | << SATA_DTLE_EDGE_SHIFT); |
| 232 | } |
| 233 | |
| 234 | if (config->sata_port1_gen3_dtle) { |
| 235 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 236 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 237 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 238 | << SATA_DTLE_DATA_SHIFT); |
| 239 | |
| 240 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 241 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 242 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 243 | << SATA_DTLE_EDGE_SHIFT); |
| 244 | } |
| 245 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 246 | /* Additional Programming Requirements */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 247 | /* Power Optimizer */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 248 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 249 | /* Step 1 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 250 | if (pch_is_lp()) |
| 251 | sir_write(dev, 0x64, 0x883c9003); |
| 252 | else |
| 253 | sir_write(dev, 0x64, 0x883c9001); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 254 | |
| 255 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 256 | reg32 = sir_read(dev, 0x68); |
| 257 | reg32 &= 0xffff0000; |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 258 | reg32 |= 0x880a; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 259 | sir_write(dev, 0x68, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 260 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 261 | /* Step 3: SIR 60h[3] = 1 */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 262 | reg32 = sir_read(dev, 0x60); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 263 | reg32 |= (1 << 3); |
| 264 | sir_write(dev, 0x60, reg32); |
| 265 | |
| 266 | /* Step 4: SIR 60h[0] = 1 */ |
| 267 | reg32 = sir_read(dev, 0x60); |
| 268 | reg32 |= (1 << 0); |
| 269 | sir_write(dev, 0x60, reg32); |
| 270 | |
| 271 | /* Step 5: SIR 60h[1] = 1 */ |
| 272 | reg32 = sir_read(dev, 0x60); |
| 273 | reg32 |= (1 << 1); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 274 | sir_write(dev, 0x60, reg32); |
| 275 | |
| 276 | /* Clock Gating */ |
| 277 | sir_write(dev, 0x70, 0x3f00bf1f); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 278 | if (pch_is_lp()) { |
| 279 | sir_write(dev, 0x54, 0xcf000f0f); |
| 280 | sir_write(dev, 0x58, 0x00190000); |
| 281 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 282 | |
| 283 | reg32 = pci_read_config32(dev, 0x300); |
| 284 | reg32 |= (1 << 17) | (1 << 16); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 285 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 286 | pci_write_config32(dev, 0x300, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 287 | } |
| 288 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 289 | static void sata_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 290 | { |
| 291 | /* Get the chip configuration */ |
| 292 | config_t *config = dev->chip_info; |
| 293 | u16 map = 0; |
| 294 | |
| 295 | if (!config) |
| 296 | return; |
| 297 | |
| 298 | /* |
| 299 | * Set SATA controller mode early so the resource allocator can |
| 300 | * properly assign IO/Memory resources for the controller. |
| 301 | */ |
| 302 | if (config->sata_ahci) |
| 303 | map = 0x0060; |
| 304 | |
| 305 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 306 | |
| 307 | pci_write_config16(dev, 0x90, map); |
| 308 | } |
| 309 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 310 | static struct device_operations sata_ops = { |
| 311 | .read_resources = pci_dev_read_resources, |
| 312 | .set_resources = pci_dev_set_resources, |
| 313 | .enable_resources = pci_dev_enable_resources, |
| 314 | .init = sata_init, |
| 315 | .enable = sata_enable, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 316 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | }; |
| 318 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 319 | static const unsigned short pci_device_ids[] = { |
| 320 | 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ |
| 321 | 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ |
| 322 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ |
| 323 | 0 |
| 324 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 325 | |
| 326 | static const struct pci_driver pch_sata __pci_driver = { |
| 327 | .ops = &sata_ops, |
| 328 | .vendor = PCI_VENDOR_ID_INTEL, |
| 329 | .devices = pci_device_ids, |
| 330 | }; |