Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 5 | * Copyright (C) 2012 Anton Kochkov |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 6 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdio.h> |
| 18 | #include <stdlib.h> |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 19 | #include <inttypes.h> |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 20 | #include "inteltool.h" |
| 21 | |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 22 | /* 320766 */ |
| 23 | static const io_register_t nehalem_dmi_registers[] = { |
| 24 | { 0x00, 4, "DMIVCH" }, // DMI Virtual Channel Capability Header |
| 25 | { 0x04, 4, "DMIVCCAP1" }, // DMI Port VC Capability Register 1 |
| 26 | { 0x08, 4, "DMIVCCAP2" }, // DMI Port VC Capability Register 2 |
| 27 | { 0x0C, 4, "DMIVCCTL" }, // DMI Port VC Control |
| 28 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 29 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 30 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 31 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 32 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 33 | { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control |
| 34 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 35 | { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status |
| 36 | /* ... - Reserved */ |
| 37 | { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities |
| 38 | { 0x88, 2, "DMILCTL" }, // DMI Link Control |
| 39 | { 0x8A, 2, "DMILSTS" }, // DMI Link Status |
| 40 | /* ... - Reserved */ |
| 41 | }; |
| 42 | |
| 43 | /* 322812 */ |
| 44 | static const io_register_t westmere_dmi_registers[] = { |
| 45 | { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability |
| 46 | { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 |
| 47 | { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 |
| 48 | { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control |
| 49 | /* { 0x0E, 2, "RSVD" }, // Reserved */ |
| 50 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 51 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 52 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 53 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 54 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 55 | { 0x20, 4, "DMIVC1RCTL1" }, // DMI VC1 Resource Control |
| 56 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 57 | { 0x26, 2, "DMIC1RSTS" }, // DMI VC1 Resource Status |
| 58 | /* ... - Reserved */ |
| 59 | { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities |
| 60 | { 0x88, 2, "DMILCTL" }, // DMI Link Control |
| 61 | { 0x8A, 2, "DMILSTS" }, // DMI Link Status |
| 62 | /* ... - Reserved */ |
| 63 | }; |
| 64 | |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 65 | static const io_register_t sandybridge_dmi_registers[] = { |
| 66 | { 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability |
| 67 | { 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1 |
| 68 | { 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2 |
| 69 | { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control |
| 70 | /* { 0x0E, 2, "RSVD" }, // Reserved */ |
| 71 | { 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability |
| 72 | { 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control |
| 73 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 74 | { 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status |
| 75 | { 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability |
| 76 | { 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control |
| 77 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 78 | { 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status |
| 79 | { 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability |
| 80 | { 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control |
| 81 | /* { 0x30, 2, "RSVD" }, // Reserved */ |
| 82 | { 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status |
| 83 | { 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability |
| 84 | { 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control |
| 85 | /* { 0x3C, 2, "RSVD" }, // Reserved */ |
| 86 | { 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status |
| 87 | /* { 0x40, 4, "RSVD" }, // Reserved */ |
| 88 | { 0x44, 4, "DMI ESC" }, // DMI Element Self Description |
| 89 | /* { 0x48, 8, "RSVD" }, // Reserved */ |
| 90 | { 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description |
| 91 | /* { 0x54, 4, "RSVD" }, // Reserved */ |
| 92 | { 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address |
| 93 | { 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address |
| 94 | { 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description |
| 95 | /* { 0x64, 4, "RSVD" }, // Reserved */ |
| 96 | { 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address |
| 97 | /* { 0x6C, 4, "RSVD" }, // Reserved |
| 98 | { 0x70, 8, "RSVD" }, // Reserved |
| 99 | { 0x78, 8, "RSVD" }, // Reserved |
| 100 | { 0x80, 4, "RSVD" }, // Reserved */ |
| 101 | { 0x84, 4, "LCAP" }, // Link Capabilities |
| 102 | { 0x88, 2, "LCTL" }, // Link Control |
| 103 | { 0x8A, 2, "LSTS" }, // Link Status |
| 104 | /* { 0x8C, 4, "RSVD" }, // Reserved |
| 105 | { 0x90, 4, "RSVD" }, // Reserved |
| 106 | { 0x94, 4, "RSVD" }, // Reserved */ |
| 107 | { 0x98, 2, "LCTL2" }, // Link Control 2 |
| 108 | { 0x9A, 2, "LSTS2" }, // Link Status 2 |
| 109 | /* ... - Reserved */ |
| 110 | { 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0 |
| 111 | { 0xBC4, 4, "RSVD" }, // Reserved |
| 112 | { 0xBC8, 4, "RSVD" }, // Reserved |
| 113 | { 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0 |
| 114 | /* ... - Reserved */ |
| 115 | }; |
| 116 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 117 | /* |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 118 | * All Haswell DMI Registers per |
| 119 | * |
| 120 | * Mobile 4th Generation Intel Core TM Processor Family, Mobile Intel Pentium Processor Family, |
| 121 | * and Mobile Intel Celeron Processor Family |
| 122 | * Datasheet Volume 2 |
| 123 | * 329002-002 |
| 124 | */ |
| 125 | static const io_register_t haswell_ult_dmi_registers[] = { |
Elyes HAOUAS | 9450150 | 2016-10-19 17:59:10 +0200 | [diff] [blame] | 126 | { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability |
| 127 | { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 |
| 128 | { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 |
| 129 | { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control |
| 130 | /* { 0x0E, 2, "RSVD" }, // Reserved */ |
| 131 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 132 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 133 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 134 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 135 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 136 | { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control |
| 137 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 138 | { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status |
| 139 | { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability |
| 140 | { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control |
| 141 | /* { 0x30, 2, "RSVD" }, // Reserved */ |
| 142 | { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status |
| 143 | { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability |
| 144 | { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control |
| 145 | /* { 0x3C, 2, "RSVD" }, // Reserved */ |
| 146 | { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status |
| 147 | { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ |
| 148 | { 0x44, 4, "DMIESD" }, // DMI Element Self Description |
| 149 | /* { 0x48, 4, "RSVD" }, // Reserved */ |
| 150 | /* { 0x4C, 4, "RSVD" }, // Reserved */ |
| 151 | { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description |
| 152 | /* { 0x54, 4, "RSVD" }, // Reserved */ |
| 153 | { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address |
| 154 | { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address |
| 155 | { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description |
| 156 | /* { 0x64, 4, "RSVD" }, // Reserved */ |
| 157 | { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address |
| 158 | /* { 0x6C, 4, "RSVD" }, // Reserved */ |
| 159 | /* { 0x70, 4, "RSVD" }, // Reserved */ |
| 160 | /* { 0x74, 4, "RSVD" }, // Reserved */ |
| 161 | /* { 0x78, 4, "RSVD" }, // Reserved */ |
| 162 | /* { 0x7C, 4, "RSVD" }, // Reserved */ |
| 163 | /* { 0x80, 4, "RSVD" }, // Reserved */ |
| 164 | /* { 0x84, 4, "RSVD" }, // Reserved */ |
| 165 | { 0x88, 2, "LCTL" }, // Link Control |
| 166 | /* ... - Reserved */ |
| 167 | { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status |
| 168 | { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask |
| 169 | { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status |
| 170 | { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 171 | /* ... - Reserved */ |
| 172 | }; |
| 173 | |
| 174 | /* |
Maximilian Schander | 98c11dd | 2017-11-05 05:52:13 +0100 | [diff] [blame] | 175 | * All Skylake-S/H DMI Registers per |
| 176 | * |
| 177 | * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 |
| 178 | * Page 117 |
| 179 | * 332688-003E |
| 180 | * |
| 181 | * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2 |
| 182 | * Page 117 |
| 183 | * 332987-002EN |
| 184 | */ |
| 185 | static const io_register_t skylake_dmi_registers[] = { |
| 186 | { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability |
| 187 | { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 |
| 188 | { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 |
| 189 | { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control |
| 190 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 191 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 192 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 193 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 194 | { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control |
| 195 | { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status |
| 196 | { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability |
| 197 | { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control |
| 198 | { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status |
| 199 | { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ |
| 200 | { 0x44, 4, "DMIESD" }, // DMI Element Self Description |
| 201 | { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description |
| 202 | { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address |
| 203 | { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address |
| 204 | { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description |
| 205 | { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address |
| 206 | { 0x84, 4, "LCAP" }, // Link Capabilities |
| 207 | { 0x88, 2, "LCTL" }, // Link Control |
| 208 | { 0x8A, 2, "LSTS" }, // DMI Link Status |
| 209 | { 0x98, 2, "LCTL2" }, // Link Control 2 |
| 210 | { 0x9A, 2, "LSTS2" }, // DMI Link Status 2 |
| 211 | { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status |
| 212 | { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask |
| 213 | { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask |
| 214 | { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status |
| 215 | { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask |
| 216 | }; |
| 217 | |
| 218 | |
| 219 | /* |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 220 | * Egress Port Root Complex MMIO configuration space |
| 221 | */ |
| 222 | int print_epbar(struct pci_dev *nb) |
| 223 | { |
| 224 | int i, size = (4 * 1024); |
| 225 | volatile uint8_t *epbar; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 226 | uint64_t epbar_phys; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 227 | |
| 228 | printf("\n============= EPBAR =============\n\n"); |
| 229 | |
| 230 | switch (nb->device_id) { |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 231 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 232 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 233 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 234 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 235 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 236 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 237 | epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; |
| 238 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 239 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 240 | case PCI_DEVICE_ID_INTEL_82Q965: |
| 241 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 242 | case PCI_DEVICE_ID_INTEL_82G33: |
| 243 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 244 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 245 | case PCI_DEVICE_ID_INTEL_32X0: |
Damien Zammit | 9c98664 | 2015-08-17 21:04:41 +1000 | [diff] [blame] | 246 | case PCI_DEVICE_ID_INTEL_82XX4X: |
| 247 | case PCI_DEVICE_ID_INTEL_82Q45: |
| 248 | case PCI_DEVICE_ID_INTEL_82G45: |
| 249 | case PCI_DEVICE_ID_INTEL_82G41: |
| 250 | case PCI_DEVICE_ID_INTEL_82B43: |
| 251 | case PCI_DEVICE_ID_INTEL_82B43_2: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 252 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 253 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 254 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 255 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
| 256 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
| 257 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
| 258 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 259 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 260 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 261 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 262 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 263 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 264 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 265 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Nico Huber | 54fe32f | 2017-10-03 16:03:07 +0200 | [diff] [blame] | 266 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: |
Maximilian Schander | 7985643 | 2017-11-05 06:14:55 +0100 | [diff] [blame] | 267 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: |
| 268 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: |
Christoph Pomaska | 48ac29e | 2018-01-01 01:48:21 +0100 | [diff] [blame] | 269 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: |
Maxim Polyakov | 1317689 | 2019-08-27 18:20:08 +0300 | [diff] [blame] | 270 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 271 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: |
| 272 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: |
| 273 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: |
Christian Walter | 9a8c5e7 | 2019-05-06 17:50:57 +0200 | [diff] [blame] | 274 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 275 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: |
| 276 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 277 | epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; |
| 278 | epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; |
| 279 | break; |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 280 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 281 | case PCI_DEVICE_ID_INTEL_82810_DC: |
| 282 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 283 | case PCI_DEVICE_ID_INTEL_82830M: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 284 | case PCI_DEVICE_ID_INTEL_82865: |
| 285 | printf("This northbridge does not have EPBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 286 | return 1; |
| 287 | default: |
| 288 | printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); |
| 289 | return 1; |
| 290 | } |
| 291 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 292 | epbar = map_physical(epbar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 293 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 294 | if (epbar == NULL) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 295 | perror("Error mapping EPBAR"); |
| 296 | exit(1); |
| 297 | } |
| 298 | |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 299 | printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 300 | for (i = 0; i < size; i += 4) { |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 301 | if (read32(epbar + i)) |
| 302 | printf("0x%04x: 0x%08x\n", i, read32(epbar+i)); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 303 | } |
| 304 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 305 | unmap_physical((void *)epbar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | /* |
| 310 | * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space |
| 311 | */ |
| 312 | int print_dmibar(struct pci_dev *nb) |
| 313 | { |
| 314 | int i, size = (4 * 1024); |
| 315 | volatile uint8_t *dmibar; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 316 | uint64_t dmibar_phys; |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 317 | const io_register_t *dmi_registers = NULL; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 318 | |
| 319 | printf("\n============= DMIBAR ============\n\n"); |
| 320 | |
| 321 | switch (nb->device_id) { |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 322 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 323 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 324 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 325 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 326 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 327 | dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; |
| 328 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 329 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 330 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 331 | case PCI_DEVICE_ID_INTEL_82Q965: |
Warren Turkal | 5329195 | 2010-09-03 09:32:17 +0000 | [diff] [blame] | 332 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 333 | case PCI_DEVICE_ID_INTEL_82G33: |
| 334 | case PCI_DEVICE_ID_INTEL_82Q33: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 335 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 336 | case PCI_DEVICE_ID_INTEL_32X0: |
Damien Zammit | 9c98664 | 2015-08-17 21:04:41 +1000 | [diff] [blame] | 337 | case PCI_DEVICE_ID_INTEL_82XX4X: |
| 338 | case PCI_DEVICE_ID_INTEL_82Q45: |
| 339 | case PCI_DEVICE_ID_INTEL_82G45: |
| 340 | case PCI_DEVICE_ID_INTEL_82G41: |
| 341 | case PCI_DEVICE_ID_INTEL_82B43: |
| 342 | case PCI_DEVICE_ID_INTEL_82B43_2: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 343 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 344 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Warren Turkal | 5329195 | 2010-09-03 09:32:17 +0000 | [diff] [blame] | 345 | dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; |
| 346 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 347 | break; |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 348 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 349 | case PCI_DEVICE_ID_INTEL_82810_DC: |
| 350 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 351 | case PCI_DEVICE_ID_INTEL_82865: |
| 352 | printf("This northbridge does not have DMIBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 353 | return 1; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 354 | case PCI_DEVICE_ID_INTEL_82X58: |
Warren Turkal | 3235eea | 2010-09-03 09:31:13 +0000 | [diff] [blame] | 355 | dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; |
| 356 | break; |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 357 | case PCI_DEVICE_ID_INTEL_CORE_0TH_GEN: |
| 358 | /* DMIBAR is called DMIRCBAR in Nehalem */ |
| 359 | dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; /* 31:12 */ |
| 360 | dmi_registers = nehalem_dmi_registers; |
| 361 | size = ARRAY_SIZE(nehalem_dmi_registers); |
| 362 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 363 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
| 364 | dmibar_phys = pci_read_long(nb, 0x68); |
| 365 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 366 | dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 367 | dmi_registers = westmere_dmi_registers; |
| 368 | size = ARRAY_SIZE(westmere_dmi_registers); |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 369 | break; |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 370 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 371 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 372 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 373 | dmi_registers = sandybridge_dmi_registers; |
| 374 | size = ARRAY_SIZE(sandybridge_dmi_registers); |
Paul Menzel | ceac787 | 2017-03-19 20:12:43 +0100 | [diff] [blame] | 375 | /* fall through */ |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 376 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: /* pretty printing not implemented yet */ |
| 377 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 378 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 379 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 380 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 381 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 382 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 383 | dmibar_phys = pci_read_long(nb, 0x68); |
| 384 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 385 | dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 386 | break; |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 387 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 388 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 389 | dmi_registers = haswell_ult_dmi_registers; |
| 390 | size = ARRAY_SIZE(haswell_ult_dmi_registers); |
| 391 | dmibar_phys = pci_read_long(nb, 0x68); |
| 392 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 393 | dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ |
| 394 | break; |
Nico Huber | 54fe32f | 2017-10-03 16:03:07 +0200 | [diff] [blame] | 395 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: |
Maximilian Schander | 98c11dd | 2017-11-05 05:52:13 +0100 | [diff] [blame] | 396 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: |
| 397 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: |
Christoph Pomaska | 48ac29e | 2018-01-01 01:48:21 +0100 | [diff] [blame] | 398 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: |
Maxim Polyakov | 1317689 | 2019-08-27 18:20:08 +0300 | [diff] [blame] | 399 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 400 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: |
| 401 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: |
| 402 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: |
Christian Walter | 9a8c5e7 | 2019-05-06 17:50:57 +0200 | [diff] [blame] | 403 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 404 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: |
| 405 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: |
Maximilian Schander | 98c11dd | 2017-11-05 05:52:13 +0100 | [diff] [blame] | 406 | dmi_registers = skylake_dmi_registers; |
| 407 | size = ARRAY_SIZE(skylake_dmi_registers); |
| 408 | dmibar_phys = pci_read_long(nb, 0x68); |
| 409 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 410 | dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ |
| 411 | break; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 412 | default: |
| 413 | printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); |
| 414 | return 1; |
| 415 | } |
| 416 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 417 | dmibar = map_physical(dmibar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 418 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 419 | if (dmibar == NULL) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 420 | perror("Error mapping DMIBAR"); |
| 421 | exit(1); |
| 422 | } |
| 423 | |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 424 | printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys); |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 425 | if (dmi_registers != NULL) { |
| 426 | for (i = 0; i < size; i++) { |
| 427 | switch (dmi_registers[i].size) { |
| 428 | case 4: |
| 429 | printf("dmibase+0x%04x: 0x%08x (%s)\n", |
| 430 | dmi_registers[i].addr, |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 431 | read32(dmibar+dmi_registers[i].addr), |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 432 | dmi_registers[i].name); |
| 433 | break; |
| 434 | case 2: |
| 435 | printf("dmibase+0x%04x: 0x%04x (%s)\n", |
| 436 | dmi_registers[i].addr, |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 437 | read16(dmibar+dmi_registers[i].addr), |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 438 | dmi_registers[i].name); |
| 439 | break; |
| 440 | case 1: |
| 441 | printf("dmibase+0x%04x: 0x%02x (%s)\n", |
| 442 | dmi_registers[i].addr, |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 443 | read8(dmibar+dmi_registers[i].addr), |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 444 | dmi_registers[i].name); |
| 445 | break; |
| 446 | } |
| 447 | } |
| 448 | } else { |
| 449 | for (i = 0; i < size; i += 4) { |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 450 | if (read32(dmibar + i)) |
| 451 | printf("0x%04x: 0x%08x\n", i, read32(dmibar+i)); |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 452 | } |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 453 | } |
| 454 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 455 | unmap_physical((void *)dmibar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 456 | return 0; |
| 457 | } |
| 458 | |
| 459 | /* |
| 460 | * PCIe MMIO configuration space |
| 461 | */ |
| 462 | int print_pciexbar(struct pci_dev *nb) |
| 463 | { |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 464 | uint64_t pciexbar_reg; |
| 465 | uint64_t pciexbar_phys; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 466 | volatile uint8_t *pciexbar; |
| 467 | int max_busses, devbase, i; |
| 468 | int bus, dev, fn; |
| 469 | |
| 470 | printf("========= PCIEXBAR ========\n\n"); |
| 471 | |
| 472 | switch (nb->device_id) { |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 473 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 474 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 475 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 476 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 477 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 478 | pciexbar_reg = pci_read_long(nb, 0x48); |
| 479 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 480 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 481 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 482 | case PCI_DEVICE_ID_INTEL_82Q965: |
| 483 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 484 | case PCI_DEVICE_ID_INTEL_82G33: |
| 485 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 486 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 487 | case PCI_DEVICE_ID_INTEL_32X0: |
Damien Zammit | 9c98664 | 2015-08-17 21:04:41 +1000 | [diff] [blame] | 488 | case PCI_DEVICE_ID_INTEL_82XX4X: |
| 489 | case PCI_DEVICE_ID_INTEL_82Q45: |
| 490 | case PCI_DEVICE_ID_INTEL_82G45: |
| 491 | case PCI_DEVICE_ID_INTEL_82G41: |
| 492 | case PCI_DEVICE_ID_INTEL_82B43: |
| 493 | case PCI_DEVICE_ID_INTEL_82B43_2: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 494 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 495 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 496 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 497 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
| 498 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
| 499 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
| 500 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 501 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 502 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 503 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 504 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 505 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 506 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 507 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Nico Huber | 54fe32f | 2017-10-03 16:03:07 +0200 | [diff] [blame] | 508 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: |
Maximilian Schander | 7985643 | 2017-11-05 06:14:55 +0100 | [diff] [blame] | 509 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: |
| 510 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: |
Christoph Pomaska | 48ac29e | 2018-01-01 01:48:21 +0100 | [diff] [blame] | 511 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: |
Maxim Polyakov | 1317689 | 2019-08-27 18:20:08 +0300 | [diff] [blame] | 512 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 513 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: |
| 514 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: |
| 515 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: |
Christian Walter | 9a8c5e7 | 2019-05-06 17:50:57 +0200 | [diff] [blame] | 516 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 517 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: |
| 518 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 519 | pciexbar_reg = pci_read_long(nb, 0x60); |
| 520 | pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; |
| 521 | break; |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 522 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 523 | case PCI_DEVICE_ID_INTEL_82810_DC: |
| 524 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 525 | case PCI_DEVICE_ID_INTEL_82865: |
| 526 | printf("Error: This northbridge does not have PCIEXBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 527 | return 1; |
| 528 | default: |
| 529 | printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); |
| 530 | return 1; |
| 531 | } |
| 532 | |
| 533 | if (!(pciexbar_reg & (1 << 0))) { |
| 534 | printf("PCIEXBAR register is disabled.\n"); |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | switch ((pciexbar_reg >> 1) & 3) { |
| 539 | case 0: // 256MB |
Paul Menzel | 17c05f2 | 2013-04-03 10:00:33 +0200 | [diff] [blame] | 540 | pciexbar_phys = pciexbar_reg & (0xffULL << 28); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 541 | max_busses = 256; |
| 542 | break; |
| 543 | case 1: // 128M |
Paul Menzel | 17c05f2 | 2013-04-03 10:00:33 +0200 | [diff] [blame] | 544 | pciexbar_phys = pciexbar_reg & (0x1ffULL << 27); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 545 | max_busses = 128; |
| 546 | break; |
| 547 | case 2: // 64M |
Paul Menzel | 17c05f2 | 2013-04-03 10:00:33 +0200 | [diff] [blame] | 548 | pciexbar_phys = pciexbar_reg & (0x3ffULL << 26); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 549 | max_busses = 64; |
| 550 | break; |
| 551 | default: // RSVD |
| 552 | printf("Undefined address base. Bailing out.\n"); |
| 553 | return 1; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 554 | } |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 555 | |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 556 | printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 557 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 558 | pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 559 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 560 | if (pciexbar == NULL) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 561 | perror("Error mapping PCIEXBAR"); |
| 562 | exit(1); |
| 563 | } |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 564 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 565 | for (bus = 0; bus < max_busses; bus++) { |
| 566 | for (dev = 0; dev < 32; dev++) { |
| 567 | for (fn = 0; fn < 8; fn++) { |
| 568 | devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024); |
| 569 | |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 570 | if (read16(pciexbar + devbase) == 0xffff) |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 571 | continue; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 572 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 573 | /* This is a heuristics. Anyone got a better check? */ |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 574 | if( (read32(pciexbar + devbase + 256) == 0xffffffff) && |
| 575 | (read32(pciexbar + devbase + 512) == 0xffffffff) ) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 576 | #if DEBUG |
| 577 | printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn); |
| 578 | #endif |
| 579 | continue; |
| 580 | } |
| 581 | |
| 582 | printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn); |
| 583 | for (i = 0; i < 4096; i++) { |
| 584 | if((i % 0x10) == 0) |
| 585 | printf("\n%04x:", i); |
| 586 | printf(" %02x", *(pciexbar+devbase+i)); |
| 587 | } |
| 588 | printf("\n"); |
| 589 | } |
| 590 | } |
| 591 | } |
| 592 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 593 | unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024)); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 594 | |
| 595 | return 0; |
| 596 | } |