Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 3 | #include <assert.h> |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Angel Pons | 47a80a0 | 2020-12-07 13:15:23 +0100 | [diff] [blame] | 6 | #include <cpu/intel/model_206ax/model_206ax.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/chip.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <delay.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 12 | #include <types.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 13 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 14 | #include "raminit_native.h" |
| 15 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 16 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 17 | #include "sandybridge.h" |
| 18 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 19 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 20 | |
| 21 | static void sfence(void) |
| 22 | { |
| 23 | asm volatile ("sfence"); |
| 24 | } |
| 25 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 26 | /* Toggle IO reset bit */ |
| 27 | static void toggle_io_reset(void) |
| 28 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 29 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 30 | MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 31 | udelay(1); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 32 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 33 | udelay(1); |
| 34 | } |
| 35 | |
| 36 | static u32 get_XOVER_CLK(u8 rankmap) |
| 37 | { |
| 38 | return rankmap << 24; |
| 39 | } |
| 40 | |
| 41 | static u32 get_XOVER_CMD(u8 rankmap) |
| 42 | { |
| 43 | u32 reg; |
| 44 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 45 | /* Enable xover cmd */ |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 46 | reg = 1 << 14; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 47 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 48 | /* Enable xover ctl */ |
| 49 | if (rankmap & 0x03) |
| 50 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 51 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 52 | if (rankmap & 0x0c) |
| 53 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 54 | |
| 55 | return reg; |
| 56 | } |
| 57 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 58 | void dram_find_common_params(ramctr_timing *ctrl) |
| 59 | { |
| 60 | size_t valid_dimms; |
| 61 | int channel, slot; |
| 62 | dimm_info *dimms = &ctrl->info; |
| 63 | |
| 64 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 65 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 66 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 67 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 68 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 69 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 70 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 71 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 72 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 73 | valid_dimms++; |
| 74 | |
| 75 | /* Find all possible CAS combinations */ |
| 76 | ctrl->cas_supported &= dimm->cas_supported; |
| 77 | |
| 78 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 79 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 80 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 81 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 82 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 83 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 84 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 85 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 86 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 87 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 88 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 89 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 90 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 91 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 95 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 96 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 97 | if (!valid_dimms) |
| 98 | die("No valid DIMMs found"); |
| 99 | } |
| 100 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 101 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 102 | { |
| 103 | u32 reg; |
| 104 | int channel; |
| 105 | |
| 106 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 107 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 108 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 109 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 110 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 111 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 112 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 113 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 114 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 115 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 116 | } |
| 117 | } |
| 118 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 119 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 120 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 121 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 122 | |
| 123 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 124 | /* |
| 125 | * ODT stretch: |
| 126 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 127 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 128 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 129 | if (stretch == 2) |
| 130 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 131 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 132 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 133 | MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 134 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 135 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 136 | addr = TC_OTHP_ch(channel); |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 137 | union tc_othp_reg tc_othp = { |
| 138 | .raw = MCHBAR32(addr), |
| 139 | }; |
| 140 | tc_othp.odt_delay_d0 = stretch; |
| 141 | tc_othp.odt_delay_d1 = stretch; |
| 142 | MCHBAR32(addr) = tc_othp.raw; |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 143 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 144 | } |
| 145 | } |
| 146 | |
| 147 | void dram_timing_regs(ramctr_timing *ctrl) |
| 148 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 149 | int channel; |
| 150 | |
Angel Pons | 8137806 | 2020-11-12 13:46:21 +0100 | [diff] [blame] | 151 | /* BIN parameters */ |
| 152 | const union tc_dbp_reg tc_dbp = { |
| 153 | .tRCD = ctrl->tRCD, |
| 154 | .tRP = ctrl->tRP, |
| 155 | .tAA = ctrl->CAS, |
| 156 | .tCWL = ctrl->CWL, |
| 157 | .tRAS = ctrl->tRAS, |
| 158 | }; |
| 159 | |
| 160 | /* Regular access parameters */ |
| 161 | const union tc_rap_reg tc_rap = { |
| 162 | .tRRD = ctrl->tRRD, |
| 163 | .tRTP = ctrl->tRTP, |
| 164 | .tCKE = ctrl->tCKE, |
| 165 | .tWTR = ctrl->tWTR, |
| 166 | .tFAW = ctrl->tFAW, |
| 167 | .tWR = ctrl->tWR, |
| 168 | .tCMD = 3, |
| 169 | }; |
| 170 | |
| 171 | /* Other parameters */ |
| 172 | const union tc_othp_reg tc_othp = { |
Angel Pons | da43737 | 2021-01-24 18:34:51 +0100 | [diff] [blame] | 173 | .tXPDLL = MIN(ctrl->tXPDLL, 31), |
| 174 | .tXP = MIN(ctrl->tXP, 7), |
Angel Pons | 8137806 | 2020-11-12 13:46:21 +0100 | [diff] [blame] | 175 | .tAONPD = ctrl->tAONPD, |
| 176 | .tCPDED = 2, |
Angel Pons | 2ad03a4 | 2020-11-19 11:07:27 +0100 | [diff] [blame] | 177 | .tPRPDEN = 1, |
Angel Pons | 8137806 | 2020-11-12 13:46:21 +0100 | [diff] [blame] | 178 | }; |
| 179 | |
| 180 | /* |
Angel Pons | da43737 | 2021-01-24 18:34:51 +0100 | [diff] [blame] | 181 | * If tXP and tXPDLL are very high, they no longer fit in the bitfields |
| 182 | * of the TC_OTHP register. If so, we set bits in TC_DTP to compensate. |
Angel Pons | 8137806 | 2020-11-12 13:46:21 +0100 | [diff] [blame] | 183 | * This can only happen on Ivy Bridge, and when overclocking the RAM. |
| 184 | */ |
| 185 | const union tc_dtp_reg tc_dtp = { |
| 186 | .overclock_tXP = ctrl->tXP >= 8, |
| 187 | .overclock_tXPDLL = ctrl->tXPDLL >= 32, |
| 188 | }; |
| 189 | |
| 190 | /* |
| 191 | * TC-Refresh timing parameters: |
| 192 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 193 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
| 194 | */ |
| 195 | const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 196 | |
| 197 | const union tc_rftp_reg tc_rftp = { |
| 198 | .tREFI = ctrl->tREFI, |
| 199 | .tRFC = ctrl->tRFC, |
| 200 | .tREFIx9 = val32 / 1024, |
| 201 | }; |
| 202 | |
| 203 | /* Self-refresh timing parameters */ |
| 204 | const union tc_srftp_reg tc_srftp = { |
| 205 | .tXSDLL = tDLLK, |
| 206 | .tXS_offset = ctrl->tXSOffset, |
| 207 | .tZQOPER = tDLLK - ctrl->tXSOffset, |
| 208 | .tMOD = ctrl->tMOD - 8, |
| 209 | }; |
| 210 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 211 | FOR_ALL_CHANNELS { |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 212 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); |
| 213 | MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 214 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 215 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); |
| 216 | MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 217 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 218 | printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); |
| 219 | MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 220 | |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 221 | if (IS_IVY_CPU(ctrl->cpu)) { |
Angel Pons | 8137806 | 2020-11-12 13:46:21 +0100 | [diff] [blame] | 222 | /* Debug parameters - only applies to Ivy Bridge */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 223 | MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 224 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 225 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 226 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 227 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 228 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); |
| 229 | MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 230 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 231 | union tc_rfp_reg tc_rfp = { |
| 232 | .raw = MCHBAR32(TC_RFP_ch(channel)), |
| 233 | }; |
| 234 | tc_rfp.oref_ri = 0xff; |
| 235 | MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 236 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 237 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); |
| 238 | MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 239 | } |
| 240 | } |
| 241 | |
| 242 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 243 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 244 | int channel; |
| 245 | dimm_info *info = &ctrl->info; |
| 246 | |
| 247 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 248 | dimm_attr *dimmA, *dimmB; |
| 249 | u32 reg = 0; |
| 250 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 251 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 252 | dimmA = &info->dimm[channel][0]; |
| 253 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 254 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 255 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 256 | dimmA = &info->dimm[channel][1]; |
| 257 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 258 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 259 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 260 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 261 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 262 | reg |= (dimmA->size_mb / 256) << 0; |
| 263 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 264 | reg |= (dimmA->width / 8 - 1) << 19; |
| 265 | } |
| 266 | |
| 267 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 268 | reg |= (dimmB->size_mb / 256) << 8; |
| 269 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 270 | reg |= (dimmB->width / 8 - 1) << 20; |
| 271 | } |
| 272 | |
Patrick Rudolph | 4e0cd82 | 2020-05-01 18:35:36 +0200 | [diff] [blame] | 273 | /* |
| 274 | * Rank interleave: Bit 16 of the physical address space sets |
| 275 | * the rank to use in a dual single rank DIMM configuration. |
| 276 | * That results in every 64KiB being interleaved between two ranks. |
| 277 | */ |
| 278 | reg |= 1 << 21; |
| 279 | /* Enhanced interleave */ |
| 280 | reg |= 1 << 22; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 281 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 282 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 283 | ctrl->mad_dimm[channel] = reg; |
| 284 | } else { |
| 285 | ctrl->mad_dimm[channel] = 0; |
| 286 | } |
| 287 | } |
| 288 | } |
| 289 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 290 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 291 | { |
| 292 | int channel; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 293 | u32 ecc; |
| 294 | |
| 295 | if (ctrl->ecc_enabled) |
| 296 | ecc = training ? (1 << 24) : (3 << 24); |
| 297 | else |
| 298 | ecc = 0; |
| 299 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 300 | FOR_ALL_CHANNELS { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 301 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 302 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 303 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 304 | if (ctrl->ecc_enabled) |
| 305 | udelay(10); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 306 | } |
| 307 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 308 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 309 | { |
| 310 | u32 reg, ch0size, ch1size; |
| 311 | u8 val; |
| 312 | reg = 0; |
| 313 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 314 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 315 | if (training) { |
| 316 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 317 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 318 | } else { |
| 319 | ch0size = ctrl->channel_size_mb[0]; |
| 320 | ch1size = ctrl->channel_size_mb[1]; |
| 321 | } |
| 322 | |
| 323 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 324 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 325 | val = ch1size / 256; |
| 326 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 327 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 328 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 329 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 330 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 331 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 332 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 333 | val = ch0size / 256; |
| 334 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 335 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 336 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 337 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 341 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 342 | |
| 343 | static unsigned int get_mmio_size(void) |
| 344 | { |
| 345 | const struct device *dev; |
| 346 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 347 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 348 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 349 | if (dev) |
| 350 | cfg = dev->chip_info; |
| 351 | |
| 352 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 353 | if (!cfg || cfg->pci_mmio_size == 0) |
| 354 | return DEFAULT_PCI_MMIO_SIZE; |
| 355 | else |
| 356 | return cfg->pci_mmio_size; |
| 357 | } |
| 358 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 359 | /* |
| 360 | * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. |
| 361 | * The ME/PCU/.. has the ability to change this. |
| 362 | * Return 0: ECC is optional |
| 363 | * Return 1: ECC is forced |
| 364 | */ |
| 365 | bool get_host_ecc_forced(void) |
| 366 | { |
| 367 | /* read Capabilities A Register */ |
| 368 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 369 | return !!(reg32 & (1 << 24)); |
| 370 | } |
| 371 | |
| 372 | /* |
| 373 | * Returns the ECC capability. |
| 374 | * The ME/PCU/.. has the ability to change this. |
| 375 | * Return 0: ECC is disabled |
| 376 | * Return 1: ECC is possible |
| 377 | */ |
| 378 | bool get_host_ecc_cap(void) |
| 379 | { |
| 380 | /* read Capabilities A Register */ |
| 381 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 382 | return !(reg32 & (1 << 25)); |
| 383 | } |
| 384 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 385 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 386 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 387 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 388 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 389 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 390 | uint16_t ggc; |
| 391 | |
| 392 | mmiosize = get_mmio_size(); |
| 393 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 394 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 395 | if (!(ggc & 2)) { |
| 396 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 397 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 398 | } else { |
| 399 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 400 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 401 | } |
| 402 | |
| 403 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 404 | |
| 405 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 406 | |
| 407 | mestolenbase = tom - me_uma_size; |
| 408 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 409 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 410 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 411 | gfxstolenbase = toludbase - gfxstolen; |
| 412 | gttbase = gfxstolenbase - gttsize; |
| 413 | |
| 414 | tsegbase = gttbase - tsegsize; |
| 415 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 416 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 417 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 418 | tsegbase &= ~(tsegsize - 1); |
| 419 | |
| 420 | gttbase -= tsegbasedelta; |
| 421 | gfxstolenbase -= tsegbasedelta; |
| 422 | toludbase -= tsegbasedelta; |
| 423 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 424 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 425 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 426 | /* Reclaim is possible */ |
| 427 | reclaim = 1; |
| 428 | remapbase = MAX(4096, tom - me_uma_size); |
| 429 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 430 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 431 | } else { |
Angel Pons | c728e25 | 2021-01-03 16:47:09 +0100 | [diff] [blame] | 432 | /* Reclaim not possible */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 433 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 434 | touudbase = tom - me_uma_size; |
| 435 | } |
| 436 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 437 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 438 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 439 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 440 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 441 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 442 | val = tom & 0xfff; |
| 443 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 444 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 445 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 446 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 447 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 448 | val = tom & 0xfffff000; |
| 449 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 450 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 451 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 452 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 453 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 454 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 455 | val = toludbase & 0xfff; |
| 456 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 457 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 458 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 459 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 460 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 461 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 462 | val = touudbase & 0xfff; |
| 463 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 464 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 465 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 466 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 467 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 468 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 469 | val = touudbase & 0xfffff000; |
| 470 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 471 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 472 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 473 | |
| 474 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 475 | /* REMAP BASE */ |
| 476 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 477 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 478 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 479 | /* REMAP LIMIT */ |
| 480 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 481 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 482 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 483 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 484 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 485 | val = tsegbase & 0xfff; |
| 486 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 487 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 488 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 489 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 490 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 491 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 492 | val = gfxstolenbase & 0xfff; |
| 493 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 494 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 495 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 496 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 497 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 498 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 499 | val = gttbase & 0xfff; |
| 500 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 501 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 502 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 503 | |
| 504 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 505 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 506 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 507 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 508 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 509 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 510 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 511 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 512 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 513 | val = mestolenbase & 0xfff; |
| 514 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 515 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 516 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 517 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 518 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 519 | val = mestolenbase & 0xfffff000; |
| 520 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 521 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 522 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 523 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 524 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 525 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 526 | val = (0x80000 - me_uma_size) & 0xfff; |
| 527 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 528 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 529 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 530 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 531 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 532 | } |
| 533 | } |
| 534 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 535 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 536 | { |
| 537 | int channel, slotrank; |
| 538 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 539 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 540 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 541 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 542 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 543 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 544 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 545 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 546 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 547 | iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 548 | |
Angel Pons | edd7cb4 | 2020-12-07 12:17:17 +0100 | [diff] [blame] | 549 | /* This is actually using the IOSAV state machine as a timer */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 550 | iosav_run_queue(channel, 1, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 551 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 552 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 553 | } |
| 554 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 555 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 556 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 557 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 558 | int channel; |
| 559 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 560 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 561 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 562 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 563 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 564 | } while ((reg & 0x14) == 0); |
| 565 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 567 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 568 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 569 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 570 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 571 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 572 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 573 | /* Assert DIMM reset signal */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 574 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 575 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 576 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 577 | udelay(200); |
| 578 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 579 | /* Deassert DIMM reset signal */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 580 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 581 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 582 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 583 | udelay(500); |
| 584 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 585 | /* Enable DCLK */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 586 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 587 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 588 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 589 | udelay(1); |
| 590 | |
| 591 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 592 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 593 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 594 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 595 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 596 | /* Wait 10ns for ranks to settle */ |
| 597 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 598 | |
| 599 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 600 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 601 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 602 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 603 | write_reset(ctrl); |
| 604 | } |
| 605 | } |
| 606 | |
Angel Pons | 3d3bf48 | 2020-11-14 16:18:15 +0100 | [diff] [blame] | 607 | /* |
| 608 | * DDR3 Rank1 Address mirror swap the following pins: |
| 609 | * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 |
| 610 | */ |
| 611 | static void ddr3_mirror_mrreg(int *bank, u32 *addr) |
| 612 | { |
| 613 | *bank = ((*bank >> 1) & 1) | ((*bank << 1) & 2); |
| 614 | *addr = (*addr & ~0x1f8) | ((*addr >> 1) & 0xa8) | ((*addr & 0xa8) << 1); |
| 615 | } |
| 616 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 617 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 618 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 619 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 620 | |
Angel Pons | 3d3bf48 | 2020-11-14 16:18:15 +0100 | [diff] [blame] | 621 | if (ctrl->rank_mirror[channel][slotrank]) |
| 622 | ddr3_mirror_mrreg(®, &val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 623 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 624 | const struct iosav_ssq sequence[] = { |
| 625 | /* DRAM command MRS */ |
| 626 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 627 | .sp_cmd_ctrl = { |
| 628 | .command = IOSAV_MRS, |
| 629 | }, |
| 630 | .subseq_ctrl = { |
| 631 | .cmd_executions = 1, |
| 632 | .cmd_delay_gap = 4, |
| 633 | .post_ssq_wait = 4, |
| 634 | .data_direction = SSQ_NA, |
| 635 | }, |
| 636 | .sp_cmd_addr = { |
| 637 | .address = val, |
| 638 | .rowbits = 6, |
| 639 | .bank = reg, |
| 640 | .rank = slotrank, |
| 641 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 642 | }, |
| 643 | /* DRAM command MRS */ |
| 644 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 645 | .sp_cmd_ctrl = { |
| 646 | .command = IOSAV_MRS, |
| 647 | .ranksel_ap = 1, |
| 648 | }, |
| 649 | .subseq_ctrl = { |
| 650 | .cmd_executions = 1, |
| 651 | .cmd_delay_gap = 4, |
| 652 | .post_ssq_wait = 4, |
| 653 | .data_direction = SSQ_NA, |
| 654 | }, |
| 655 | .sp_cmd_addr = { |
| 656 | .address = val, |
| 657 | .rowbits = 6, |
| 658 | .bank = reg, |
| 659 | .rank = slotrank, |
| 660 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 661 | }, |
| 662 | /* DRAM command MRS */ |
| 663 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 664 | .sp_cmd_ctrl = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 665 | .command = IOSAV_MRS, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 666 | }, |
| 667 | .subseq_ctrl = { |
| 668 | .cmd_executions = 1, |
| 669 | .cmd_delay_gap = 4, |
| 670 | .post_ssq_wait = ctrl->tMOD, |
| 671 | .data_direction = SSQ_NA, |
| 672 | }, |
| 673 | .sp_cmd_addr = { |
| 674 | .address = val, |
| 675 | .rowbits = 6, |
| 676 | .bank = reg, |
| 677 | .rank = slotrank, |
| 678 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 679 | }, |
| 680 | }; |
| 681 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 682 | |
Angel Pons | 9f4ed3b | 2020-12-07 12:34:36 +0100 | [diff] [blame] | 683 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 684 | } |
| 685 | |
Angel Pons | 09fc4b9 | 2020-11-19 12:02:07 +0100 | [diff] [blame] | 686 | /* Obtain optimal power down mode for current configuration */ |
| 687 | static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) |
| 688 | { |
| 689 | if (ctrl->tXP > 8) |
| 690 | return PDM_NONE; |
| 691 | |
| 692 | if (ctrl->tXPDLL > 32) |
| 693 | return PDM_PPD; |
| 694 | |
| 695 | if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) |
| 696 | return PDM_DLL_OFF; |
| 697 | |
| 698 | return PDM_APD_PPD; |
| 699 | } |
| 700 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 701 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 702 | { |
| 703 | u16 mr0reg, mch_cas, mch_wr; |
| 704 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Angel Pons | 09fc4b9 | 2020-11-19 12:02:07 +0100 | [diff] [blame] | 705 | |
| 706 | const enum pdwm_mode power_down = get_power_down_mode(ctrl); |
| 707 | |
| 708 | const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 709 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 710 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 711 | if (ctrl->CAS < 12) { |
| 712 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 713 | } else { |
| 714 | mch_cas = (u16) (ctrl->CAS - 12); |
| 715 | mch_cas = ((mch_cas << 1) | 0x1); |
| 716 | } |
| 717 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 718 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 719 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 720 | |
Angel Pons | 2bf28ed | 2020-11-12 13:49:59 +0100 | [diff] [blame] | 721 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 722 | mr0reg = 1 << 8; |
| 723 | |
| 724 | mr0reg |= (mch_cas & 0x1) << 2; |
| 725 | mr0reg |= (mch_cas & 0xe) << 3; |
| 726 | mr0reg |= mch_wr << 9; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 727 | |
Angel Pons | 09fc4b9 | 2020-11-19 12:02:07 +0100 | [diff] [blame] | 728 | /* Precharge PD - Use slow exit when DLL-off is used - mostly power-saving feature */ |
| 729 | mr0reg |= !slow_exit << 12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 730 | return mr0reg; |
| 731 | } |
| 732 | |
| 733 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 734 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 735 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 736 | } |
| 737 | |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 738 | static odtmap get_ODT(ramctr_timing *ctrl, int channel) |
Angel Pons | 1a9b5aa | 2020-11-12 13:51:46 +0100 | [diff] [blame] | 739 | { |
| 740 | /* Get ODT based on rankmap */ |
| 741 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
| 742 | |
| 743 | if (dimms_per_ch == 1) { |
| 744 | return (const odtmap){60, 60}; |
| 745 | } else { |
| 746 | return (const odtmap){120, 30}; |
| 747 | } |
| 748 | } |
| 749 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 750 | static u32 encode_odt(u32 odt) |
| 751 | { |
| 752 | switch (odt) { |
| 753 | case 30: |
Angel Pons | c728e25 | 2021-01-03 16:47:09 +0100 | [diff] [blame] | 754 | return (1 << 9) | (1 << 2); /* RZQ/8, RZQ/4 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 755 | case 60: |
Angel Pons | c728e25 | 2021-01-03 16:47:09 +0100 | [diff] [blame] | 756 | return (1 << 2); /* RZQ/4 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 757 | case 120: |
Angel Pons | c728e25 | 2021-01-03 16:47:09 +0100 | [diff] [blame] | 758 | return (1 << 6); /* RZQ/2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 759 | default: |
| 760 | case 0: |
| 761 | return 0; |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 766 | { |
| 767 | odtmap odt; |
| 768 | u32 mr1reg; |
| 769 | |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 770 | odt = get_ODT(ctrl, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 771 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 772 | |
| 773 | mr1reg |= encode_odt(odt.rttnom); |
| 774 | |
| 775 | return mr1reg; |
| 776 | } |
| 777 | |
| 778 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 779 | { |
| 780 | u16 mr1reg; |
| 781 | |
| 782 | mr1reg = make_mr1(ctrl, rank, channel); |
| 783 | |
| 784 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 785 | } |
| 786 | |
| 787 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 788 | { |
Angel Pons | 868bca2 | 2020-11-13 13:38:04 +0100 | [diff] [blame] | 789 | const u16 pasr = 0; |
| 790 | const u16 cwl = ctrl->CWL - 5; |
| 791 | const odtmap odt = get_ODT(ctrl, channel); |
| 792 | |
Angel Pons | dca3cb5 | 2020-11-13 13:42:07 +0100 | [diff] [blame] | 793 | int srt = 0; |
Angel Pons | dca3cb5 | 2020-11-13 13:42:07 +0100 | [diff] [blame] | 794 | if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) |
| 795 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 796 | |
Angel Pons | 868bca2 | 2020-11-13 13:38:04 +0100 | [diff] [blame] | 797 | u16 mr2reg = 0; |
| 798 | mr2reg |= pasr; |
| 799 | mr2reg |= cwl << 3; |
| 800 | mr2reg |= ctrl->auto_self_refresh << 6; |
| 801 | mr2reg |= srt << 7; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 802 | mr2reg |= (odt.rttwr / 60) << 9; |
| 803 | |
| 804 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
Angel Pons | 7f1363d | 2020-11-13 13:31:58 +0100 | [diff] [blame] | 805 | |
| 806 | /* Program MR2 shadow */ |
| 807 | u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); |
| 808 | |
| 809 | reg32 &= 3 << 14 | 3 << 6; |
| 810 | |
| 811 | reg32 |= mr2reg & ~(3 << 6); |
| 812 | |
Angel Pons | 927b1c0 | 2020-12-10 22:11:27 +0100 | [diff] [blame] | 813 | if (srt) |
| 814 | reg32 |= 1 << (rank / 2 + 6); |
| 815 | |
| 816 | if (ctrl->rank_mirror[channel][rank]) |
| 817 | reg32 |= 1 << (rank / 2 + 14); |
| 818 | |
Angel Pons | 7f1363d | 2020-11-13 13:31:58 +0100 | [diff] [blame] | 819 | MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 823 | { |
| 824 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 825 | } |
| 826 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 827 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 828 | { |
| 829 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 830 | int channel; |
| 831 | |
| 832 | FOR_ALL_POPULATED_CHANNELS { |
| 833 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 834 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 835 | dram_mr2(ctrl, slotrank, channel); |
| 836 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 837 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 838 | dram_mr3(ctrl, slotrank, channel); |
| 839 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 840 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 841 | dram_mr1(ctrl, slotrank, channel); |
| 842 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 843 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 844 | dram_mr0(ctrl, slotrank, channel); |
| 845 | } |
| 846 | } |
| 847 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 848 | const struct iosav_ssq zqcl_sequence[] = { |
| 849 | /* DRAM command NOP (without ODT nor chip selects) */ |
| 850 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 851 | .sp_cmd_ctrl = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 852 | .command = IOSAV_NOP & ~(0xff << 8), |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 853 | }, |
| 854 | .subseq_ctrl = { |
| 855 | .cmd_executions = 1, |
| 856 | .cmd_delay_gap = 4, |
| 857 | .post_ssq_wait = 15, |
| 858 | .data_direction = SSQ_NA, |
| 859 | }, |
| 860 | .sp_cmd_addr = { |
| 861 | .address = 2, |
| 862 | .rowbits = 6, |
| 863 | .bank = 0, |
| 864 | .rank = 0, |
| 865 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 866 | }, |
| 867 | /* DRAM command ZQCL */ |
| 868 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 869 | .sp_cmd_ctrl = { |
| 870 | .command = IOSAV_ZQCS, |
| 871 | .ranksel_ap = 1, |
| 872 | }, |
| 873 | .subseq_ctrl = { |
| 874 | .cmd_executions = 1, |
| 875 | .cmd_delay_gap = 4, |
| 876 | .post_ssq_wait = 400, |
| 877 | .data_direction = SSQ_NA, |
| 878 | }, |
| 879 | .sp_cmd_addr = { |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 880 | .address = 1 << 10, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 881 | .rowbits = 6, |
| 882 | .bank = 0, |
| 883 | .rank = 0, |
| 884 | }, |
| 885 | .addr_update = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 886 | .inc_rank = 1, |
| 887 | .addr_wrap = 20, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 888 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 889 | }, |
| 890 | }; |
| 891 | iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 892 | |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 893 | iosav_run_queue(BROADCAST_CH, 4, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 894 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 895 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 896 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 897 | } |
| 898 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 899 | /* Refresh enable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 900 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 901 | |
| 902 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 903 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 904 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 905 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 906 | |
| 907 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 908 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 909 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 910 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 911 | iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 912 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 913 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 914 | } |
| 915 | } |
| 916 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 917 | static const u32 lane_base[] = { |
| 918 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 919 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 920 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 921 | }; |
| 922 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 923 | /* Maximum delay for command, control, clock */ |
| 924 | #define CCC_MAX_PI (2 * QCLK_PI - 1) |
| 925 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 926 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 927 | { |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 928 | u32 reg_roundtrip_latency, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 929 | int lane; |
| 930 | int slotrank, slot; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 931 | |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 932 | u32 ctl_delay[NUM_SLOTS] = { 0 }; |
| 933 | int cmd_delay = 0; |
| 934 | |
| 935 | /* Enable CLK XOVER */ |
| 936 | u32 clk_pi_coding = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 937 | u32 clk_logic_dly = 0; |
| 938 | |
| 939 | /* |
Angel Pons | 7519ca4 | 2021-01-12 01:21:24 +0100 | [diff] [blame] | 940 | * Compute command timing as abs() of the most negative PI code |
| 941 | * across all ranks. Use zero if none of the values is negative. |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 942 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 943 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7519ca4 | 2021-01-12 01:21:24 +0100 | [diff] [blame] | 944 | cmd_delay = MAX(cmd_delay, -ctrl->timings[channel][slotrank].pi_coding); |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 945 | } |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 946 | if (cmd_delay > CCC_MAX_PI) { |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 947 | printk(BIOS_ERR, "C%d command delay overflow: %d\n", channel, cmd_delay); |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 948 | cmd_delay = CCC_MAX_PI; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 949 | } |
| 950 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 951 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 952 | const int pi_coding_0 = ctrl->timings[channel][2 * slot + 0].pi_coding; |
| 953 | const int pi_coding_1 = ctrl->timings[channel][2 * slot + 1].pi_coding; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 954 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 955 | const u8 slot_map = (ctrl->rankmap[channel] >> (2 * slot)) & 3; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 956 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 957 | if (slot_map & 1) |
| 958 | ctl_delay[slot] += pi_coding_0 + cmd_delay; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 959 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 960 | if (slot_map & 2) |
| 961 | ctl_delay[slot] += pi_coding_1 + cmd_delay; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 962 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 963 | /* If both ranks in a slot are populated, use the average */ |
| 964 | if (slot_map == 3) |
| 965 | ctl_delay[slot] /= 2; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 966 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 967 | if (ctl_delay[slot] > CCC_MAX_PI) { |
| 968 | printk(BIOS_ERR, "C%dS%d control delay overflow: %d\n", |
| 969 | channel, slot, ctl_delay[slot]); |
| 970 | ctl_delay[slot] = CCC_MAX_PI; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 971 | } |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 972 | } |
| 973 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 0a7d99c | 2021-01-12 01:13:08 +0100 | [diff] [blame] | 974 | int clk_delay = ctrl->timings[channel][slotrank].pi_coding + cmd_delay; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 975 | |
Angel Pons | 0a7d99c | 2021-01-12 01:13:08 +0100 | [diff] [blame] | 976 | /* |
| 977 | * Clock is a differential signal, whereas command and control are not. |
| 978 | * This affects its timing, and it is also why it needs a magic offset. |
| 979 | */ |
| 980 | clk_delay += ctrl->pi_code_offset; |
| 981 | |
| 982 | /* Can never happen with valid values */ |
| 983 | if (clk_delay < 0) { |
| 984 | printk(BIOS_ERR, "C%dR%d clock delay underflow: %d\n", |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 985 | channel, slotrank, clk_delay); |
Angel Pons | 0a7d99c | 2021-01-12 01:13:08 +0100 | [diff] [blame] | 986 | clk_delay = 0; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 987 | } |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 988 | |
Angel Pons | 0a7d99c | 2021-01-12 01:13:08 +0100 | [diff] [blame] | 989 | /* Clock can safely wrap around because it is a periodic signal */ |
| 990 | clk_delay %= CCC_MAX_PI + 1; |
| 991 | |
Angel Pons | 89200d2 | 2021-01-12 01:04:04 +0100 | [diff] [blame] | 992 | clk_pi_coding |= (clk_delay % QCLK_PI) << (6 * slotrank); |
| 993 | clk_logic_dly |= (clk_delay / QCLK_PI) << slotrank; |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 994 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 995 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 996 | /* Enable CMD XOVER */ |
Angel Pons | 737f111 | 2020-11-13 14:07:30 +0100 | [diff] [blame] | 997 | union gdcr_cmd_pi_coding_reg cmd_pi_coding = { |
| 998 | .raw = get_XOVER_CMD(ctrl->rankmap[channel]), |
| 999 | }; |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1000 | cmd_pi_coding.cmd_pi_code = cmd_delay % QCLK_PI; |
| 1001 | cmd_pi_coding.cmd_logic_delay = cmd_delay / QCLK_PI; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1002 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1003 | cmd_pi_coding.ctl_pi_code_d0 = ctl_delay[0] % QCLK_PI; |
| 1004 | cmd_pi_coding.ctl_pi_code_d1 = ctl_delay[1] % QCLK_PI; |
| 1005 | cmd_pi_coding.ctl_logic_delay_d0 = ctl_delay[0] / QCLK_PI; |
| 1006 | cmd_pi_coding.ctl_logic_delay_d1 = ctl_delay[1] / QCLK_PI; |
Angel Pons | 737f111 | 2020-11-13 14:07:30 +0100 | [diff] [blame] | 1007 | |
| 1008 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1009 | |
Angel Pons | 7584e55 | 2020-11-19 21:34:32 +0100 | [diff] [blame] | 1010 | MCHBAR32(GDCRCKPICODE_ch(channel)) = clk_pi_coding; |
| 1011 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = clk_logic_dly; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1012 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1013 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1014 | reg_io_latency &= ~0xffff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1015 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1016 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1017 | |
| 1018 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 075d123 | 2020-11-19 21:50:33 +0100 | [diff] [blame] | 1019 | reg_io_latency |= ctrl->timings[channel][slotrank].io_latency << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1020 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1021 | reg_roundtrip_latency |= |
Angel Pons | 075d123 | 2020-11-19 21:50:33 +0100 | [diff] [blame] | 1022 | ctrl->timings[channel][slotrank].roundtrip_latency << (8 * slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1023 | |
| 1024 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1025 | const u16 rcven = ctrl->timings[channel][slotrank].lanes[lane].rcven; |
| 1026 | const u8 dqs_p = ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p; |
| 1027 | const u8 dqs_n = ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n; |
Angel Pons | 9fcc110 | 2020-11-19 22:23:13 +0100 | [diff] [blame] | 1028 | const union gdcr_rx_reg gdcr_rx = { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1029 | .rcven_pi_code = rcven % QCLK_PI, |
Angel Pons | 9fcc110 | 2020-11-19 22:23:13 +0100 | [diff] [blame] | 1030 | .rx_dqs_p_pi_code = dqs_p, |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1031 | .rcven_logic_delay = rcven / QCLK_PI, |
Angel Pons | 9fcc110 | 2020-11-19 22:23:13 +0100 | [diff] [blame] | 1032 | .rx_dqs_n_pi_code = dqs_n, |
| 1033 | }; |
| 1034 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = gdcr_rx.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1035 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1036 | const u16 tx_dqs = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; |
| 1037 | const int tx_dq = ctrl->timings[channel][slotrank].lanes[lane].tx_dq; |
Angel Pons | 9fcc110 | 2020-11-19 22:23:13 +0100 | [diff] [blame] | 1038 | const union gdcr_tx_reg gdcr_tx = { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1039 | .tx_dq_pi_code = tx_dq % QCLK_PI, |
| 1040 | .tx_dqs_pi_code = tx_dqs % QCLK_PI, |
| 1041 | .tx_dqs_logic_delay = tx_dqs / QCLK_PI, |
| 1042 | .tx_dq_logic_delay = tx_dq / QCLK_PI, |
Angel Pons | 9fcc110 | 2020-11-19 22:23:13 +0100 | [diff] [blame] | 1043 | }; |
| 1044 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = gdcr_tx.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1045 | } |
| 1046 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1047 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1048 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1049 | } |
| 1050 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1051 | static void test_rcven(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1052 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1053 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1054 | |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1055 | /* Send a burst of 16 back-to-back read commands (4 DCLK apart) */ |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1056 | iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1057 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1058 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1059 | } |
| 1060 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1061 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1062 | { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1063 | u32 rcven = ctrl->timings[channel][slotrank].lanes[lane].rcven; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1064 | |
| 1065 | return (MCHBAR32(lane_base[lane] + |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1066 | GDCRTRAININGRESULT(channel, (rcven / 32) & 1)) >> (rcven % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1067 | } |
| 1068 | |
| 1069 | struct run { |
| 1070 | int middle; |
| 1071 | int end; |
| 1072 | int start; |
| 1073 | int all; |
| 1074 | int length; |
| 1075 | }; |
| 1076 | |
| 1077 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1078 | { |
| 1079 | int i, ls; |
| 1080 | int bl = 0, bs = 0; |
| 1081 | struct run ret; |
| 1082 | |
| 1083 | ls = 0; |
| 1084 | for (i = 0; i < 2 * sz; i++) |
| 1085 | if (seq[i % sz]) { |
| 1086 | if (i - ls > bl) { |
| 1087 | bl = i - ls; |
| 1088 | bs = ls; |
| 1089 | } |
| 1090 | ls = i + 1; |
| 1091 | } |
| 1092 | if (bl == 0) { |
| 1093 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1094 | ret.start = 0; |
| 1095 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1096 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1097 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1098 | return ret; |
| 1099 | } |
| 1100 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1101 | ret.start = bs % sz; |
| 1102 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1103 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1104 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1105 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1106 | |
| 1107 | return ret; |
| 1108 | } |
| 1109 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1110 | #define RCVEN_COARSE_PI_LENGTH (2 * QCLK_PI) |
| 1111 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1112 | static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1113 | { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1114 | int rcven; |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1115 | int statistics[NUM_LANES][RCVEN_COARSE_PI_LENGTH]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1116 | int lane; |
| 1117 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1118 | for (rcven = 0; rcven < RCVEN_COARSE_PI_LENGTH; rcven++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1119 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1120 | ctrl->timings[channel][slotrank].lanes[lane].rcven = rcven; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1121 | } |
| 1122 | program_timings(ctrl, channel); |
| 1123 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1124 | test_rcven(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1125 | |
| 1126 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1127 | statistics[lane][rcven] = |
| 1128 | !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1129 | } |
| 1130 | } |
| 1131 | FOR_ALL_LANES { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1132 | struct run rn = get_longest_zero_run(statistics[lane], RCVEN_COARSE_PI_LENGTH); |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1133 | ctrl->timings[channel][slotrank].lanes[lane].rcven = rn.middle; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1134 | upperA[lane] = rn.end; |
| 1135 | if (upperA[lane] < rn.middle) |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1136 | upperA[lane] += 2 * QCLK_PI; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1137 | |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1138 | printram("rcven: %d, %d, %d: % 4d-% 4d-% 4d\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1139 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1140 | } |
| 1141 | } |
| 1142 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1143 | static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1144 | { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1145 | int rcven_delta; |
Angel Pons | 86e3d74 | 2021-01-03 14:55:12 +0100 | [diff] [blame] | 1146 | int statistics[NUM_LANES][51] = {0}; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1147 | int lane, i; |
| 1148 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1149 | for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1150 | |
| 1151 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1152 | ctrl->timings[channel][slotrank].lanes[lane].rcven |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1153 | = upperA[lane] + rcven_delta + QCLK_PI; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1154 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1155 | program_timings(ctrl, channel); |
| 1156 | |
| 1157 | for (i = 0; i < 100; i++) { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1158 | test_rcven(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1159 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1160 | statistics[lane][rcven_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1161 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1162 | } |
| 1163 | } |
| 1164 | } |
| 1165 | FOR_ALL_LANES { |
| 1166 | int last_zero, first_all; |
| 1167 | |
| 1168 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1169 | if (statistics[lane][last_zero + 25]) |
| 1170 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1171 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1172 | last_zero--; |
| 1173 | for (first_all = -25; first_all <= 25; first_all++) |
| 1174 | if (statistics[lane][first_all + 25] == 100) |
| 1175 | break; |
| 1176 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1177 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1178 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1179 | ctrl->timings[channel][slotrank].lanes[lane].rcven = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1180 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1181 | |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1182 | printram("Aval: %d, %d, %d: % 4d\n", channel, slotrank, |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1183 | lane, ctrl->timings[channel][slotrank].lanes[lane].rcven); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1184 | } |
| 1185 | } |
| 1186 | |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1187 | /* |
| 1188 | * Once the DQS high phase has been found (for each DRAM) the next stage |
| 1189 | * is to find out the round trip latency, by locating the preamble cycle. |
| 1190 | * This is achieved by trying smaller and smaller roundtrip values until |
| 1191 | * the strobe sampling is done on the preamble cycle. |
| 1192 | */ |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1193 | static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1194 | { |
| 1195 | int works[NUM_LANES]; |
| 1196 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1197 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1198 | while (1) { |
| 1199 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1200 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1201 | program_timings(ctrl, channel); |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1202 | test_rcven(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1203 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1204 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1205 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1206 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1207 | if (works[lane]) |
| 1208 | some_works = 1; |
| 1209 | else |
| 1210 | all_works = 0; |
| 1211 | } |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1212 | |
| 1213 | /* If every lane is working, exit */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1214 | if (all_works) |
| 1215 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1216 | |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1217 | /* |
| 1218 | * If all bits are one (everyone is failing), decrement |
| 1219 | * the roundtrip value by two, and do another iteration. |
| 1220 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1221 | if (!some_works) { |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1222 | /* Guard against roundtrip latency underflow */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1223 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 1224 | printk(BIOS_EMERG, "Roundtrip latency underflow: %d, %d\n", |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1225 | channel, slotrank); |
| 1226 | return MAKE_ERR; |
| 1227 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1228 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1229 | printram("4024 -= 2;\n"); |
| 1230 | continue; |
| 1231 | } |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1232 | |
| 1233 | /* |
| 1234 | * Else (if some lanes are failing), increase the rank's |
| 1235 | * I/O latency by 2, and increase rcven logic delay by 2 |
| 1236 | * on the working lanes, then perform another iteration. |
| 1237 | */ |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1238 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1239 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1240 | |
Angel Pons | 3aed6ac | 2020-12-07 02:00:41 +0100 | [diff] [blame] | 1241 | /* Guard against I/O latency overflow */ |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 1242 | if (ctrl->timings[channel][slotrank].io_latency >= 16) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 1243 | printk(BIOS_EMERG, "I/O latency overflow: %d, %d\n", |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1244 | channel, slotrank); |
| 1245 | return MAKE_ERR; |
| 1246 | } |
| 1247 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1248 | ctrl->timings[channel][slotrank].lanes[lane].rcven += 2 * QCLK_PI; |
| 1249 | upperA[lane] += 2 * QCLK_PI; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1250 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1251 | } |
| 1252 | } |
| 1253 | return 0; |
| 1254 | } |
| 1255 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1256 | static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1257 | { |
| 1258 | int lane; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1259 | u16 logic_delay_min = 7; |
| 1260 | u16 logic_delay_max = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1261 | |
| 1262 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1263 | const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].rcven >> 6; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1264 | |
| 1265 | logic_delay_min = MIN(logic_delay_min, logic_delay); |
| 1266 | logic_delay_max = MAX(logic_delay_max, logic_delay); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1267 | } |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1268 | |
| 1269 | if (logic_delay_max < logic_delay_min) { |
| 1270 | printk(BIOS_EMERG, "Logic delay max < min (%u < %u): %d, %d\n", |
| 1271 | logic_delay_max, logic_delay_min, channel, slotrank); |
| 1272 | } |
| 1273 | |
| 1274 | assert(logic_delay_max >= logic_delay_min); |
| 1275 | |
| 1276 | return logic_delay_max - logic_delay_min; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1277 | } |
| 1278 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1279 | static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int slotrank, int prev) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1280 | { |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1281 | int latency_offset = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1282 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1283 | /* Get changed maxima */ |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1284 | const int post = get_logic_delay_delta(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1285 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1286 | if (prev < post) |
| 1287 | latency_offset = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1288 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1289 | else if (prev > post) |
| 1290 | latency_offset = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1291 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1292 | else |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1293 | latency_offset = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1294 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1295 | ctrl->timings[channel][slotrank].io_latency += latency_offset; |
| 1296 | ctrl->timings[channel][slotrank].roundtrip_latency += latency_offset; |
| 1297 | printram("4024 += %d;\n", latency_offset); |
| 1298 | printram("4028 += %d;\n", latency_offset); |
| 1299 | |
| 1300 | return post; |
| 1301 | } |
| 1302 | |
| 1303 | static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slotrank) |
| 1304 | { |
| 1305 | u16 logic_delay_min = 7; |
| 1306 | int lane; |
| 1307 | |
| 1308 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1309 | const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].rcven >> 6; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1310 | |
| 1311 | logic_delay_min = MIN(logic_delay_min, logic_delay); |
| 1312 | } |
| 1313 | |
| 1314 | if (logic_delay_min >= 2) { |
| 1315 | printk(BIOS_WARNING, "Logic delay %u greater than 1: %d %d\n", |
| 1316 | logic_delay_min, channel, slotrank); |
| 1317 | } |
| 1318 | |
| 1319 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1320 | ctrl->timings[channel][slotrank].lanes[lane].rcven -= logic_delay_min << 6; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1321 | } |
| 1322 | ctrl->timings[channel][slotrank].io_latency -= logic_delay_min; |
| 1323 | printram("4028 -= %d;\n", logic_delay_min); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1324 | } |
| 1325 | |
Angel Pons | 7f5a97c | 2020-11-13 16:58:46 +0100 | [diff] [blame] | 1326 | int receive_enable_calibration(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1327 | { |
| 1328 | int channel, slotrank, lane; |
| 1329 | int err; |
| 1330 | |
| 1331 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1332 | int all_high, some_high; |
| 1333 | int upperA[NUM_LANES]; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1334 | int prev; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1335 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1336 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1337 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1338 | iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1339 | |
Angel Pons | 9f4ed3b | 2020-12-07 12:34:36 +0100 | [diff] [blame] | 1340 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1341 | |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 1342 | const union gdcr_training_mod_reg training_mod = { |
| 1343 | .receive_enable_mode = 1, |
| 1344 | .training_rank_sel = slotrank, |
| 1345 | .odt_always_on = 1, |
| 1346 | }; |
| 1347 | MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1348 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1349 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1350 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1351 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1352 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1353 | find_rcven_pi_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1354 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1355 | all_high = 1; |
| 1356 | some_high = 0; |
| 1357 | FOR_ALL_LANES { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1358 | if (ctrl->timings[channel][slotrank].lanes[lane].rcven >= QCLK_PI) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1359 | some_high = 1; |
| 1360 | else |
| 1361 | all_high = 0; |
| 1362 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1363 | |
| 1364 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1365 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1366 | printram("4028--;\n"); |
| 1367 | FOR_ALL_LANES { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1368 | ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI; |
| 1369 | upperA[lane] -= QCLK_PI; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1370 | |
| 1371 | } |
| 1372 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1373 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1374 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1375 | printram("4024++;\n"); |
| 1376 | printram("4028++;\n"); |
| 1377 | } |
| 1378 | |
| 1379 | program_timings(ctrl, channel); |
| 1380 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1381 | prev = get_logic_delay_delta(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1382 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1383 | err = find_roundtrip_latency(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1384 | if (err) |
| 1385 | return err; |
| 1386 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1387 | prev = align_rt_io_latency(ctrl, channel, slotrank, prev); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1388 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1389 | fine_tune_rcven_pi(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1390 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1391 | prev = align_rt_io_latency(ctrl, channel, slotrank, prev); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1392 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1393 | compute_final_logic_delay(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1394 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1395 | align_rt_io_latency(ctrl, channel, slotrank, prev); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1396 | |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1397 | printram("4/8: %d, %d, % 4d, % 4d\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1398 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1399 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1400 | |
| 1401 | printram("final results:\n"); |
| 1402 | FOR_ALL_LANES |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1403 | printram("Aval: %d, %d, %d: % 4d\n", channel, slotrank, lane, |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1404 | ctrl->timings[channel][slotrank].lanes[lane].rcven); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1405 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1406 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1407 | |
| 1408 | toggle_io_reset(); |
| 1409 | } |
| 1410 | |
| 1411 | FOR_ALL_POPULATED_CHANNELS { |
| 1412 | program_timings(ctrl, channel); |
| 1413 | } |
Angel Pons | c674223 | 2020-11-15 13:26:21 +0100 | [diff] [blame] | 1414 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1415 | return 0; |
| 1416 | } |
| 1417 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1418 | static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1419 | { |
| 1420 | int lane; |
| 1421 | |
| 1422 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1423 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1424 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1425 | } |
| 1426 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1427 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1428 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1429 | iosav_write_misc_write_sequence(ctrl, channel, slotrank, |
| 1430 | MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1431 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1432 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1433 | |
Angel Pons | 801a5cb | 2020-11-15 15:48:29 +0100 | [diff] [blame] | 1434 | iosav_write_prea_act_read_sequence(ctrl, channel, slotrank); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1435 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1436 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1437 | } |
| 1438 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1439 | static void tx_dq_threshold_process(int *data, const int count) |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1440 | { |
| 1441 | int min = data[0]; |
| 1442 | int max = min; |
| 1443 | int i; |
| 1444 | for (i = 1; i < count; i++) { |
| 1445 | if (min > data[i]) |
| 1446 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1447 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1448 | if (max < data[i]) |
| 1449 | max = data[i]; |
| 1450 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1451 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1452 | for (i = 0; i < count; i++) |
| 1453 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1454 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1455 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1456 | } |
| 1457 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1458 | static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1459 | { |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1460 | int tx_dq; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1461 | int stats[NUM_LANES][MAX_TX_DQ + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1462 | int lane; |
| 1463 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1464 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1465 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1466 | iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1467 | |
Angel Pons | 9f4ed3b | 2020-12-07 12:34:36 +0100 | [diff] [blame] | 1468 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1469 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1470 | for (tx_dq = 0; tx_dq <= MAX_TX_DQ; tx_dq++) { |
| 1471 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].tx_dq = tx_dq; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1472 | program_timings(ctrl, channel); |
| 1473 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1474 | test_tx_dq(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1475 | |
| 1476 | FOR_ALL_LANES { |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1477 | stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1478 | } |
| 1479 | } |
| 1480 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1481 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1482 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1483 | if (rn.all || rn.length < 8) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 1484 | printk(BIOS_EMERG, "tx_dq write leveling failed: %d, %d, %d\n", |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1485 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1486 | /* |
| 1487 | * With command training not being done yet, the lane can be erroneous. |
| 1488 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1489 | */ |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1490 | tx_dq_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1491 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1492 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1493 | if (rn.all || rn.length < 8) { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1494 | printk(BIOS_EMERG, "tx_dq recovery failed\n"); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1495 | return MAKE_ERR; |
| 1496 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1497 | } |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1498 | ctrl->timings[channel][slotrank].lanes[lane].tx_dq = rn.middle; |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1499 | printram("tx_dq: %d, %d, %d: % 4d-% 4d-% 4d\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1500 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1501 | } |
| 1502 | return 0; |
| 1503 | } |
| 1504 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1505 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1506 | { |
| 1507 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1508 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1509 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1510 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1511 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1512 | return ret; |
| 1513 | } |
| 1514 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1515 | /* Each cacheline is 64 bits long */ |
| 1516 | static void program_wdb_pattern_length(int channel, const unsigned int num_cachelines) |
| 1517 | { |
| 1518 | MCHBAR8(IOSAV_DATA_CTL_ch(channel)) = num_cachelines / 8 - 1; |
| 1519 | } |
| 1520 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1521 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1522 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1523 | unsigned int j; |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 1524 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1525 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1526 | for (j = 0; j < 16; j++) |
| 1527 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1528 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1529 | sfence(); |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1530 | |
| 1531 | program_wdb_pattern_length(channel, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1532 | } |
| 1533 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1534 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1535 | { |
| 1536 | int ret = 0; |
| 1537 | int channel; |
| 1538 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1539 | return ret; |
| 1540 | } |
| 1541 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1542 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1543 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1544 | unsigned int j; |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 1545 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64; |
| 1546 | unsigned int channel_step = 64 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1547 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1548 | for (j = 0; j < 16; j++) |
| 1549 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1550 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1551 | for (j = 0; j < 16; j++) |
| 1552 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1553 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1554 | sfence(); |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1555 | |
| 1556 | program_wdb_pattern_length(channel, 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1557 | } |
| 1558 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1559 | #define TX_DQS_PI_LENGTH (2 * QCLK_PI) |
| 1560 | |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1561 | static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1562 | { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1563 | int tx_dqs; |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1564 | int statistics[NUM_LANES][TX_DQS_PI_LENGTH]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1565 | int lane; |
| 1566 | |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 1567 | const union gdcr_training_mod_reg training_mod = { |
| 1568 | .write_leveling_mode = 1, |
| 1569 | .training_rank_sel = slotrank, |
| 1570 | .enable_dqs_wl = 5, |
| 1571 | .odt_always_on = 1, |
| 1572 | .force_drive_enable = 1, |
| 1573 | }; |
| 1574 | MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1575 | |
Angel Pons | c6d2fea | 2020-11-14 16:52:33 +0100 | [diff] [blame] | 1576 | u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; |
| 1577 | int bank = 1; |
| 1578 | |
| 1579 | if (ctrl->rank_mirror[channel][slotrank]) |
| 1580 | ddr3_mirror_mrreg(&bank, &mr1reg); |
| 1581 | |
| 1582 | wait_for_iosav(channel); |
| 1583 | |
| 1584 | iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); |
| 1585 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1586 | for (tx_dqs = 0; tx_dqs < TX_DQS_PI_LENGTH; tx_dqs++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1587 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1588 | ctrl->timings[channel][slotrank].lanes[lane].tx_dqs = tx_dqs; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1589 | } |
| 1590 | program_timings(ctrl, channel); |
| 1591 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1592 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1593 | |
| 1594 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1595 | statistics[lane][tx_dqs] = !((MCHBAR32(lane_base[lane] + |
| 1596 | GDCRTRAININGRESULT(channel, (tx_dqs / 32) & 1)) >> |
| 1597 | (tx_dqs % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1598 | } |
| 1599 | } |
| 1600 | FOR_ALL_LANES { |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1601 | struct run rn = get_longest_zero_run(statistics[lane], TX_DQS_PI_LENGTH); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1602 | /* |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1603 | * tx_dq is a direct function of tx_dqs's 6 LSBs. Some tests increment the value |
| 1604 | * of tx_dqs by a small value, which might cause the 6-bit value to overflow if |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1605 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 1606 | * to overflow, to make sure it won't overflow while running tests and bricks |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1607 | * the system due to a non matching tx_dq. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1608 | * |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1609 | * TODO: find out why some tests (edge write discovery) increment tx_dqs. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1610 | */ |
| 1611 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1612 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1613 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1614 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1615 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1616 | ctrl->timings[channel][slotrank].lanes[lane].tx_dqs = rn.start; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1617 | if (rn.all) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 1618 | printk(BIOS_EMERG, "JEDEC write leveling failed: %d, %d, %d\n", |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1619 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1620 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1621 | return MAKE_ERR; |
| 1622 | } |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1623 | printram("tx_dqs: %d, %d, %d: % 4d-% 4d-% 4d\n", |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1624 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1625 | } |
| 1626 | return 0; |
| 1627 | } |
| 1628 | |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1629 | static int get_dqs_flyby_adjust(u64 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1630 | { |
| 1631 | int i; |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1632 | /* DQS is good enough */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1633 | if (val == 0xffffffffffffffffLL) |
| 1634 | return 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1635 | if (val >= 0xf000000000000000LL) { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1636 | /* DQS is late, needs negative adjustment */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1637 | for (i = 0; i < 8; i++) |
| 1638 | if (val << (8 * (7 - i) + 4)) |
| 1639 | return -i; |
| 1640 | } else { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1641 | /* DQS is early, needs positive adjustment */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1642 | for (i = 0; i < 8; i++) |
| 1643 | if (val >> (8 * (7 - i) + 4)) |
| 1644 | return i; |
| 1645 | } |
| 1646 | return 8; |
| 1647 | } |
| 1648 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1649 | static void train_write_flyby(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1650 | { |
| 1651 | int channel, slotrank, lane, old; |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 1652 | |
| 1653 | const union gdcr_training_mod_reg training_mod = { |
| 1654 | .dq_dqs_training_res = 1, |
| 1655 | }; |
| 1656 | MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; |
| 1657 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1658 | FOR_ALL_POPULATED_CHANNELS { |
| 1659 | fill_pattern1(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1660 | } |
| 1661 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1662 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1663 | /* Reset read and write WDB pointers */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1664 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1665 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1666 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1667 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1668 | iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1669 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1670 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1671 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1672 | const struct iosav_ssq rd_sequence[] = { |
| 1673 | /* DRAM command PREA */ |
| 1674 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1675 | .sp_cmd_ctrl = { |
| 1676 | .command = IOSAV_PRE, |
| 1677 | .ranksel_ap = 1, |
| 1678 | }, |
| 1679 | .subseq_ctrl = { |
| 1680 | .cmd_executions = 1, |
| 1681 | .cmd_delay_gap = 3, |
| 1682 | .post_ssq_wait = ctrl->tRP, |
| 1683 | .data_direction = SSQ_NA, |
| 1684 | }, |
| 1685 | .sp_cmd_addr = { |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 1686 | .address = 1 << 10, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1687 | .rowbits = 6, |
| 1688 | .bank = 0, |
| 1689 | .rank = slotrank, |
| 1690 | }, |
| 1691 | .addr_update = { |
| 1692 | .addr_wrap = 18, |
| 1693 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1694 | }, |
| 1695 | /* DRAM command ACT */ |
| 1696 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1697 | .sp_cmd_ctrl = { |
| 1698 | .command = IOSAV_ACT, |
| 1699 | .ranksel_ap = 1, |
| 1700 | }, |
| 1701 | .subseq_ctrl = { |
| 1702 | .cmd_executions = 1, |
| 1703 | .cmd_delay_gap = 3, |
| 1704 | .post_ssq_wait = ctrl->tRCD, |
| 1705 | .data_direction = SSQ_NA, |
| 1706 | }, |
| 1707 | .sp_cmd_addr = { |
| 1708 | .address = 0, |
| 1709 | .rowbits = 6, |
| 1710 | .bank = 0, |
| 1711 | .rank = slotrank, |
| 1712 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1713 | }, |
Angel Pons | f550231 | 2021-02-10 11:08:28 +0100 | [diff] [blame] | 1714 | /* DRAM command RDA */ |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1715 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1716 | .sp_cmd_ctrl = { |
| 1717 | .command = IOSAV_RD, |
| 1718 | .ranksel_ap = 3, |
| 1719 | }, |
| 1720 | .subseq_ctrl = { |
| 1721 | .cmd_executions = 1, |
| 1722 | .cmd_delay_gap = 3, |
| 1723 | .post_ssq_wait = ctrl->tRP + |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1724 | ctrl->timings[channel][slotrank].roundtrip_latency + |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1725 | ctrl->timings[channel][slotrank].io_latency, |
| 1726 | .data_direction = SSQ_RD, |
| 1727 | }, |
| 1728 | .sp_cmd_addr = { |
| 1729 | .address = 8, |
| 1730 | .rowbits = 6, |
| 1731 | .bank = 0, |
| 1732 | .rank = slotrank, |
| 1733 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1734 | }, |
| 1735 | }; |
| 1736 | iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1737 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1738 | iosav_run_once_and_wait(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1739 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1740 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1741 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 1742 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1743 | GDCRTRAININGRESULT2(channel))) << 32; |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1744 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1745 | old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; |
| 1746 | ctrl->timings[channel][slotrank].lanes[lane].tx_dqs += |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1747 | get_dqs_flyby_adjust(res) * QCLK_PI; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1748 | |
| 1749 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 1750 | printram("Bval+: %d, %d, %d, % 4d -> % 4d\n", channel, slotrank, lane, |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1751 | old, ctrl->timings[channel][slotrank].lanes[lane].tx_dqs); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1752 | } |
| 1753 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1754 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1755 | } |
| 1756 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1757 | static void disable_refresh_machine(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1758 | { |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1759 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1760 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1761 | FOR_ALL_POPULATED_CHANNELS { |
| 1762 | /* choose an existing rank */ |
| 1763 | const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1764 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1765 | iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1766 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1767 | iosav_run_once_and_wait(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1768 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1769 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
| 1770 | } |
| 1771 | |
| 1772 | /* Refresh disable */ |
| 1773 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); |
| 1774 | |
| 1775 | FOR_ALL_POPULATED_CHANNELS { |
| 1776 | /* Execute the same command queue */ |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1777 | iosav_run_once_and_wait(channel); |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1778 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1779 | } |
| 1780 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1781 | /* |
| 1782 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1783 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1784 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 1785 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 1786 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 1787 | * CLK/ADDR/CMD signals have the same routing delay. |
| 1788 | * |
| 1789 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 1790 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 1791 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1792 | */ |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1793 | static int jedec_write_leveling(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1794 | { |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1795 | int channel, slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1796 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1797 | disable_refresh_machine(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1798 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1799 | /* Enable write leveling on all ranks |
| 1800 | Disable all DQ outputs |
| 1801 | Only NOP is allowed in this mode */ |
| 1802 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 1803 | write_mrreg(ctrl, channel, slotrank, 1, |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1804 | make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1805 | |
Angel Pons | a1f1714 | 2020-11-15 12:50:03 +0100 | [diff] [blame] | 1806 | /* Needs to be programmed before I/O reset below */ |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 1807 | const union gdcr_training_mod_reg training_mod = { |
| 1808 | .write_leveling_mode = 1, |
| 1809 | .enable_dqs_wl = 5, |
| 1810 | .odt_always_on = 1, |
| 1811 | .force_drive_enable = 1, |
| 1812 | }; |
| 1813 | MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1814 | |
| 1815 | toggle_io_reset(); |
| 1816 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1817 | /* Set any valid value for tx_dqs, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1818 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1819 | const int err = write_level_rank(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1820 | if (err) |
| 1821 | return err; |
| 1822 | } |
| 1823 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1824 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1825 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1826 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1827 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1828 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1829 | |
| 1830 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1831 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1832 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1833 | /* Refresh enable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1834 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1835 | |
| 1836 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 1837 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1838 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 1839 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1840 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1841 | iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1842 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1843 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1844 | } |
| 1845 | |
| 1846 | toggle_io_reset(); |
| 1847 | |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1848 | return 0; |
| 1849 | } |
| 1850 | |
| 1851 | int write_training(ramctr_timing *ctrl) |
| 1852 | { |
Angel Pons | c674223 | 2020-11-15 13:26:21 +0100 | [diff] [blame] | 1853 | int channel, slotrank; |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1854 | int err; |
| 1855 | |
Angel Pons | 4d19282 | 2020-12-12 13:54:37 +0100 | [diff] [blame] | 1856 | /* |
| 1857 | * Set the DEC_WRD bit, required for the write flyby algorithm. |
| 1858 | * Needs to be done before starting the write training procedure. |
| 1859 | */ |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1860 | FOR_ALL_POPULATED_CHANNELS |
| 1861 | MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |
| 1862 | |
Angel Pons | 4c76d25 | 2020-11-15 13:06:53 +0100 | [diff] [blame] | 1863 | printram("CPE\n"); |
| 1864 | |
Angel Pons | 820bce7 | 2020-11-14 17:02:55 +0100 | [diff] [blame] | 1865 | err = jedec_write_leveling(ctrl); |
| 1866 | if (err) |
| 1867 | return err; |
| 1868 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1869 | printram("CPF\n"); |
| 1870 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1871 | FOR_ALL_POPULATED_CHANNELS { |
| 1872 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1873 | } |
| 1874 | |
| 1875 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1876 | err = tx_dq_write_leveling(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1877 | if (err) |
| 1878 | return err; |
| 1879 | } |
| 1880 | |
| 1881 | FOR_ALL_POPULATED_CHANNELS |
| 1882 | program_timings(ctrl, channel); |
| 1883 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1884 | /* measure and adjust tx_dqs timings */ |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1885 | train_write_flyby(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1886 | |
| 1887 | FOR_ALL_POPULATED_CHANNELS |
| 1888 | program_timings(ctrl, channel); |
| 1889 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1890 | return 0; |
| 1891 | } |
| 1892 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1893 | static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1894 | { |
| 1895 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1896 | int tx_dq_delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1897 | int lanes_ok = 0; |
| 1898 | int ctr = 0; |
| 1899 | int lane; |
| 1900 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1901 | for (tx_dq_delta = -5; tx_dq_delta <= 5; tx_dq_delta++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1902 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 1903 | ctrl->timings[channel][slotrank].lanes[lane].tx_dq = |
| 1904 | saved_rt.lanes[lane].tx_dq + tx_dq_delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1905 | } |
| 1906 | program_timings(ctrl, channel); |
| 1907 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1908 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1909 | } |
| 1910 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1911 | /* Reset read WDB pointer */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1912 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1913 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1914 | wait_for_iosav(channel); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1915 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1916 | iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1917 | |
| 1918 | /* Program LFSR for the RD/WR subsequences */ |
| 1919 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
| 1920 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1921 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 1922 | iosav_run_once_and_wait(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1923 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1924 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1925 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1926 | |
| 1927 | if (r32 == 0) |
| 1928 | lanes_ok |= 1 << lane; |
| 1929 | } |
| 1930 | ctr++; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 1931 | if (lanes_ok == ((1 << ctrl->lanes) - 1)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1932 | break; |
| 1933 | } |
| 1934 | |
| 1935 | ctrl->timings[channel][slotrank] = saved_rt; |
| 1936 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 1937 | return lanes_ok != ((1 << ctrl->lanes) - 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1938 | } |
| 1939 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1940 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1941 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1942 | unsigned int i, j; |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 1943 | unsigned int offset = get_precedening_channels(ctrl, channel) * 64; |
| 1944 | unsigned int step = 64 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1945 | |
| 1946 | if (patno) { |
| 1947 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 1948 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 1949 | for (i = 0; i < 32; i++) { |
| 1950 | for (j = 0; j < 16; j++) { |
| 1951 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1952 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1953 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 1954 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1955 | |
| 1956 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1957 | } |
| 1958 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1959 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1960 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 1961 | for (j = 0; j < 16; j++) { |
| 1962 | const u32 val = pattern[i][j]; |
| 1963 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 1964 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1965 | } |
| 1966 | sfence(); |
| 1967 | } |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1968 | |
| 1969 | program_wdb_pattern_length(channel, 256); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1970 | } |
| 1971 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1972 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1973 | { |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1974 | disable_refresh_machine(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1975 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1976 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1977 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1978 | |
| 1979 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1980 | dram_mrscommands(ctrl); |
| 1981 | |
| 1982 | toggle_io_reset(); |
| 1983 | } |
| 1984 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 1985 | #define CT_MIN_PI (-CCC_MAX_PI) |
| 1986 | #define CT_MAX_PI (+CCC_MAX_PI + 1) |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1987 | #define CT_PI_LENGTH (CT_MAX_PI - CT_MIN_PI + 1) |
| 1988 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1989 | #define MIN_C320C_LEN 13 |
| 1990 | |
| 1991 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 1992 | { |
| 1993 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 1994 | int slotrank; |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1995 | int command_pi; |
| 1996 | int stat[NUM_SLOTRANKS][CT_PI_LENGTH]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1997 | int delta = 0; |
| 1998 | |
| 1999 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2000 | |
| 2001 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2002 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2003 | } |
| 2004 | |
| 2005 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2006 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2007 | const union tc_rap_reg tc_rap = { |
| 2008 | .tRRD = ctrl->tRRD, |
| 2009 | .tRTP = ctrl->tRTP, |
| 2010 | .tCKE = ctrl->tCKE, |
| 2011 | .tWTR = ctrl->tWTR, |
| 2012 | .tFAW = ctrl->tFAW, |
| 2013 | .tWR = ctrl->tWR, |
| 2014 | .tCMD = ctrl->cmd_stretch[channel], |
| 2015 | }; |
| 2016 | MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2017 | |
| 2018 | if (ctrl->cmd_stretch[channel] == 2) |
| 2019 | delta = 2; |
| 2020 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2021 | delta = 4; |
| 2022 | |
| 2023 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2024 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2025 | } |
| 2026 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2027 | for (command_pi = CT_MIN_PI; command_pi < CT_MAX_PI; command_pi++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2028 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2029 | ctrl->timings[channel][slotrank].pi_coding = command_pi; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2030 | } |
| 2031 | program_timings(ctrl, channel); |
| 2032 | reprogram_320c(ctrl); |
| 2033 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2034 | stat[slotrank][command_pi - CT_MIN_PI] = |
| 2035 | test_command_training(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2036 | } |
| 2037 | } |
| 2038 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2039 | struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2040 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2041 | ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 2042 | printram("cmd_stretch: %d, %d: % 4d-% 4d-% 4d\n", |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2043 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2044 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2045 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2046 | FOR_ALL_POPULATED_RANKS { |
| 2047 | ctrl->timings[channel][slotrank] = |
| 2048 | saved_timings[channel][slotrank]; |
| 2049 | } |
| 2050 | return MAKE_ERR; |
| 2051 | } |
| 2052 | } |
| 2053 | |
| 2054 | return 0; |
| 2055 | } |
| 2056 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2057 | /* |
| 2058 | * Adjust CMD phase shift and try multiple command rates. |
| 2059 | * A command rate of 2T doubles the time needed for address and command decode. |
| 2060 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2061 | int command_training(ramctr_timing *ctrl) |
| 2062 | { |
| 2063 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2064 | |
| 2065 | FOR_ALL_POPULATED_CHANNELS { |
| 2066 | fill_pattern5(ctrl, channel, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2067 | } |
| 2068 | |
| 2069 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2070 | int cmdrate, err; |
| 2071 | |
| 2072 | /* |
| 2073 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2074 | * Issue: |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 2075 | * While command training seems to succeed, raminit will fail in write training. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2076 | * |
| 2077 | * Workaround: |
| 2078 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 2079 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2080 | * |
| 2081 | * Single DIMM per channel: |
| 2082 | * Try command rate 1T and 2T |
| 2083 | */ |
| 2084 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2085 | if (ctrl->tCMD) |
| 2086 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2087 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2088 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2089 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2090 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2091 | |
| 2092 | if (!err) |
| 2093 | break; |
| 2094 | } |
| 2095 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2096 | if (err) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 2097 | printk(BIOS_EMERG, "Command training failed: %d\n", channel); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2098 | return err; |
| 2099 | } |
| 2100 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2101 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2102 | } |
| 2103 | |
| 2104 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 2105 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2106 | |
| 2107 | reprogram_320c(ctrl); |
| 2108 | return 0; |
| 2109 | } |
| 2110 | |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2111 | static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2112 | { |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2113 | int dqs_pi; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2114 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2115 | int lane; |
| 2116 | |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2117 | for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2118 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2119 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = dqs_pi; |
| 2120 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = dqs_pi; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2121 | } |
| 2122 | program_timings(ctrl, channel); |
| 2123 | |
| 2124 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2125 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2126 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2127 | } |
| 2128 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2129 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2130 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2131 | iosav_write_read_mpr_sequence( |
| 2132 | channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2133 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 2134 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2135 | |
| 2136 | FOR_ALL_LANES { |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2137 | stats[lane][dqs_pi] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2138 | } |
| 2139 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2140 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2141 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2142 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2143 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2144 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2145 | if (rn.all) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 2146 | printk(BIOS_EMERG, "Read MPR training failed: %d, %d, %d\n", channel, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2147 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2148 | return MAKE_ERR; |
| 2149 | } |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 2150 | printram("eval %d, %d, %d: % 4d\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2151 | } |
| 2152 | return 0; |
| 2153 | } |
| 2154 | |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2155 | static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) |
| 2156 | { |
| 2157 | int slotrank, lane; |
| 2158 | |
| 2159 | fill_pattern0(ctrl, channel, 0, 0); |
| 2160 | FOR_ALL_LANES { |
Angel Pons | c674223 | 2020-11-15 13:26:21 +0100 | [diff] [blame] | 2161 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2162 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
| 2163 | } |
| 2164 | |
| 2165 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2166 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = 16; |
| 2167 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = 16; |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2168 | } |
| 2169 | |
| 2170 | program_timings(ctrl, channel); |
| 2171 | |
| 2172 | FOR_ALL_POPULATED_RANKS { |
| 2173 | wait_for_iosav(channel); |
| 2174 | |
| 2175 | iosav_write_read_mpr_sequence( |
| 2176 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
| 2177 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 2178 | iosav_run_once_and_wait(channel); |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2179 | } |
| 2180 | |
| 2181 | /* XXX: check any measured value ? */ |
| 2182 | |
| 2183 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2184 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = 48; |
| 2185 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = 48; |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2186 | } |
| 2187 | |
| 2188 | program_timings(ctrl, channel); |
| 2189 | |
| 2190 | FOR_ALL_POPULATED_RANKS { |
| 2191 | wait_for_iosav(channel); |
| 2192 | |
| 2193 | iosav_write_read_mpr_sequence( |
| 2194 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
| 2195 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 2196 | iosav_run_once_and_wait(channel); |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2197 | } |
| 2198 | |
| 2199 | /* XXX: check any measured value ? */ |
| 2200 | |
| 2201 | FOR_ALL_LANES { |
| 2202 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
| 2203 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
| 2204 | } |
| 2205 | } |
| 2206 | |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2207 | int read_mpr_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2208 | { |
| 2209 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2210 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2211 | int channel, slotrank, lane; |
| 2212 | int err; |
| 2213 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2214 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2215 | |
| 2216 | toggle_io_reset(); |
| 2217 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2218 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2219 | find_predefined_pattern(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2220 | |
| 2221 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2222 | } |
| 2223 | |
Angel Pons | 0c3936e | 2020-03-22 12:49:27 +0100 | [diff] [blame] | 2224 | /* |
| 2225 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2226 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2227 | */ |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 2228 | MCHBAR32(IOSAV_DC_MASK) = 3 << 8; |
| 2229 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2230 | |
| 2231 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2232 | err = find_read_mpr_margin(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2233 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2234 | if (err) |
| 2235 | return err; |
| 2236 | } |
| 2237 | |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 2238 | MCHBAR32(IOSAV_DC_MASK) = 2 << 8; |
| 2239 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2240 | |
| 2241 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2242 | err = find_read_mpr_margin(ctrl, channel, slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2243 | rising_edges[channel][slotrank]); |
| 2244 | if (err) |
| 2245 | return err; |
| 2246 | } |
| 2247 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2248 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2249 | |
| 2250 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2251 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2252 | falling_edges[channel][slotrank][lane]; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2253 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2254 | rising_edges[channel][slotrank][lane]; |
| 2255 | } |
| 2256 | |
| 2257 | FOR_ALL_POPULATED_CHANNELS { |
| 2258 | program_timings(ctrl, channel); |
| 2259 | } |
| 2260 | |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 2261 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2262 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2263 | } |
| 2264 | return 0; |
| 2265 | } |
| 2266 | |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2267 | static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2268 | { |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2269 | const int rd_vref_offsets[] = { 0, 0xc, 0x2c }; |
| 2270 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2271 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2272 | int lower[NUM_LANES]; |
| 2273 | int upper[NUM_LANES]; |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2274 | int lane, i, read_pi, pat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2275 | |
| 2276 | FOR_ALL_LANES { |
| 2277 | lower[lane] = 0; |
| 2278 | upper[lane] = MAX_EDGE_TIMING; |
| 2279 | } |
| 2280 | |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2281 | for (i = 0; i < ARRAY_SIZE(rd_vref_offsets); i++) { |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 2282 | const union gdcr_training_mod_reg training_mod = { |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2283 | .vref_gen_ctl = rd_vref_offsets[i], |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 2284 | }; |
| 2285 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; |
| 2286 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2287 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2288 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2289 | fill_pattern5(ctrl, channel, pat); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2290 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2291 | |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2292 | for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2293 | FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2294 | ctrl->timings[channel][slotrank].lanes[lane] |
| 2295 | .rx_dqs_p = read_pi; |
| 2296 | ctrl->timings[channel][slotrank].lanes[lane] |
| 2297 | .rx_dqs_n = read_pi; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2298 | } |
| 2299 | program_timings(ctrl, channel); |
| 2300 | |
| 2301 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2302 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2303 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2304 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2305 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2306 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2307 | iosav_write_data_write_sequence(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2308 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 2309 | iosav_run_once_and_wait(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2310 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2311 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2312 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2313 | } |
| 2314 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2315 | /* FIXME: This register only exists on Ivy Bridge */ |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2316 | raw_stats[read_pi] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2317 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2318 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2319 | FOR_ALL_LANES { |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2320 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2321 | struct run rn; |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2322 | |
| 2323 | for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) |
| 2324 | stats[read_pi] = !!(raw_stats[read_pi] & (1 << lane)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2325 | |
| 2326 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 2327 | |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 2328 | printram("edges: %d, %d, %d: % 4d-% 4d-% 4d, " |
| 2329 | "% 4d-% 4d\n", channel, slotrank, i, rn.start, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2330 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2331 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2332 | |
| 2333 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2334 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2335 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2336 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2337 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 2338 | printk(BIOS_EMERG, "Aggressive read training failed: " |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2339 | "%d, %d, %d\n", channel, slotrank, lane); |
| 2340 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2341 | return MAKE_ERR; |
| 2342 | } |
| 2343 | } |
| 2344 | } |
| 2345 | } |
| 2346 | |
Angel Pons | a93f46e | 2020-11-17 16:54:01 +0100 | [diff] [blame] | 2347 | /* Restore nominal Vref after training */ |
| 2348 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2349 | printram("CPA\n"); |
| 2350 | return 0; |
| 2351 | } |
| 2352 | |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2353 | int aggressive_read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2354 | { |
| 2355 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2356 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2357 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2358 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2359 | /* |
| 2360 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2361 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2362 | */ |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 2363 | MCHBAR32(IOSAV_DC_MASK) = 3 << 8; |
| 2364 | printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2365 | |
| 2366 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2367 | err = find_agrsv_read_margin(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2368 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2369 | if (err) |
| 2370 | return err; |
| 2371 | } |
| 2372 | |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 2373 | MCHBAR32(IOSAV_DC_MASK) = 2 << 8; |
| 2374 | printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2375 | |
| 2376 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 2377 | err = find_agrsv_read_margin(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2378 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2379 | if (err) |
| 2380 | return err; |
| 2381 | } |
| 2382 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2383 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2384 | |
| 2385 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2386 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2387 | falling_edges[channel][slotrank][lane]; |
| 2388 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2389 | ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2390 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2391 | } |
| 2392 | |
| 2393 | FOR_ALL_POPULATED_CHANNELS |
| 2394 | program_timings(ctrl, channel); |
| 2395 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2396 | return 0; |
| 2397 | } |
| 2398 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2399 | static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2400 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2401 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2402 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2403 | iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2404 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 2405 | iosav_run_once_and_wait(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2406 | } |
| 2407 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2408 | static void set_write_vref(const int channel, const u8 wr_vref) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2409 | { |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2410 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24), wr_vref << 24); |
| 2411 | udelay(2); |
| 2412 | } |
| 2413 | |
| 2414 | int aggressive_write_training(ramctr_timing *ctrl) |
| 2415 | { |
| 2416 | const u8 wr_vref_offsets[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2417 | int i, pat; |
| 2418 | |
| 2419 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2420 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2421 | int channel, slotrank, lane; |
| 2422 | |
Angel Pons | 9fbb1b0 | 2020-11-19 12:53:36 +0100 | [diff] [blame] | 2423 | /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ |
| 2424 | if (!IS_IVY_CPU(ctrl->cpu)) |
| 2425 | return 0; |
| 2426 | |
| 2427 | if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF)) |
| 2428 | return 0; |
| 2429 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2430 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2431 | lower[channel][slotrank][lane] = 0; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2432 | upper[channel][slotrank][lane] = MAX_TX_DQ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2433 | } |
| 2434 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2435 | /* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ |
| 2436 | const bool enable_iosav_opt = IS_IVY_CPU_D(ctrl->cpu) || IS_IVY_CPU_E(ctrl->cpu); |
| 2437 | |
| 2438 | if (enable_iosav_opt) |
| 2439 | MCHBAR32(MCMNTS_SPARE) = 1; |
| 2440 | |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 2441 | printram("Aggresive write training:\n"); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2442 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2443 | for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2444 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2445 | set_write_vref(channel, wr_vref_offsets[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2446 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2447 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2448 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2449 | int tx_dq; |
| 2450 | u32 raw_stats[MAX_TX_DQ + 1]; |
| 2451 | int stats[MAX_TX_DQ + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2452 | |
| 2453 | /* Make sure rn.start < rn.end */ |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2454 | stats[MAX_TX_DQ] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2455 | |
| 2456 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2457 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2458 | for (tx_dq = 0; tx_dq < MAX_TX_DQ; tx_dq++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2459 | FOR_ALL_LANES { |
| 2460 | ctrl->timings[channel][slotrank] |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2461 | .lanes[lane].tx_dq = tx_dq; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2462 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2463 | program_timings(ctrl, channel); |
| 2464 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2465 | test_aggressive_write(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2466 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2467 | raw_stats[tx_dq] = MCHBAR32( |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2468 | IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2469 | } |
| 2470 | FOR_ALL_LANES { |
| 2471 | struct run rn; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2472 | for (tx_dq = 0; tx_dq < MAX_TX_DQ; tx_dq++) { |
| 2473 | stats[tx_dq] = !!(raw_stats[tx_dq] |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2474 | & (1 << lane)); |
| 2475 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2476 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2477 | rn = get_longest_zero_run(stats, MAX_TX_DQ + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2478 | if (rn.all) { |
Angel Pons | 3079163 | 2020-12-12 12:28:29 +0100 | [diff] [blame] | 2479 | printk(BIOS_EMERG, "Aggressive " |
| 2480 | "write training failed: " |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2481 | "%d, %d, %d\n", channel, |
| 2482 | slotrank, lane); |
| 2483 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2484 | return MAKE_ERR; |
| 2485 | } |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2486 | printram("tx_dq: %d, %d, %d: " |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 2487 | "% 4d-% 4d-% 4d, " |
| 2488 | "% 4d-% 4d\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2489 | i, rn.start, rn.middle, rn.end, |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2490 | rn.start + ctrl->tx_dq_offset[i], |
| 2491 | rn.end - ctrl->tx_dq_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2492 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2493 | lower[channel][slotrank][lane] = |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2494 | MAX(rn.start + ctrl->tx_dq_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2495 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2496 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2497 | upper[channel][slotrank][lane] = |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2498 | MIN(rn.end - ctrl->tx_dq_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2499 | upper[channel][slotrank][lane]); |
| 2500 | |
| 2501 | } |
| 2502 | } |
| 2503 | } |
| 2504 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2505 | } |
| 2506 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 2507 | FOR_ALL_CHANNELS { |
| 2508 | /* Restore nominal write Vref after training */ |
| 2509 | set_write_vref(channel, 0); |
| 2510 | } |
| 2511 | |
| 2512 | /* Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization */ |
| 2513 | if (enable_iosav_opt) |
| 2514 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2515 | |
| 2516 | printram("CPB\n"); |
| 2517 | |
| 2518 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7e439c9 | 2020-12-07 11:56:01 +0100 | [diff] [blame] | 2519 | printram("tx_dq %d, %d, %d: % 4d\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2520 | (lower[channel][slotrank][lane] + |
| 2521 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2522 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2523 | ctrl->timings[channel][slotrank].lanes[lane].tx_dq = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2524 | (lower[channel][slotrank][lane] + |
| 2525 | upper[channel][slotrank][lane]) / 2; |
| 2526 | } |
| 2527 | FOR_ALL_POPULATED_CHANNELS { |
| 2528 | program_timings(ctrl, channel); |
| 2529 | } |
| 2530 | return 0; |
| 2531 | } |
| 2532 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2533 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2534 | { |
| 2535 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2536 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2537 | |
| 2538 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2539 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2540 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2541 | FOR_ALL_LANES mat = |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 2542 | MAX(ctrl->timings[channel][slotrank].lanes[lane].rcven, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2543 | printram("normalize %d, %d, %d: mat %d\n", |
| 2544 | channel, slotrank, lane, mat); |
| 2545 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2546 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2547 | printram("normalize %d, %d, %d: delta %d\n", |
| 2548 | channel, slotrank, lane, delta); |
| 2549 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2550 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2551 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2552 | } |
| 2553 | |
| 2554 | FOR_ALL_POPULATED_CHANNELS { |
| 2555 | program_timings(ctrl, channel); |
| 2556 | } |
| 2557 | } |
| 2558 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2559 | int channel_test(ramctr_timing *ctrl) |
| 2560 | { |
| 2561 | int channel, slotrank, lane; |
| 2562 | |
| 2563 | slotrank = 0; |
| 2564 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2565 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2566 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2567 | return MAKE_ERR; |
| 2568 | } |
| 2569 | FOR_ALL_POPULATED_CHANNELS { |
| 2570 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2571 | } |
| 2572 | |
| 2573 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 2574 | FOR_ALL_CHANNELS |
| 2575 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 2576 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2577 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 2578 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2579 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2580 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2581 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2582 | iosav_write_memory_test_sequence(ctrl, channel, slotrank); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2583 | |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 2584 | iosav_run_once_and_wait(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2585 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2586 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2587 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2588 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 2589 | channel, slotrank, lane); |
| 2590 | return MAKE_ERR; |
| 2591 | } |
| 2592 | } |
| 2593 | return 0; |
| 2594 | } |
| 2595 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2596 | void channel_scrub(ramctr_timing *ctrl) |
| 2597 | { |
| 2598 | int channel, slotrank, row, rowsize; |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2599 | u8 bank; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2600 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2601 | FOR_ALL_POPULATED_CHANNELS { |
| 2602 | wait_for_iosav(channel); |
| 2603 | fill_pattern0(ctrl, channel, 0, 0); |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2604 | } |
| 2605 | |
| 2606 | /* |
| 2607 | * During runtime the "scrubber" will periodically scan through the memory in the |
| 2608 | * physical address space, to identify and fix CRC errors. |
| 2609 | * The following loops writes to every DRAM address, setting the ECC bits to the |
| 2610 | * correct value. A read from this location will no longer return a CRC error, |
| 2611 | * except when a bit has toggled due to external events. |
Angel Pons | 3b9d3e9 | 2020-11-11 19:10:39 +0100 | [diff] [blame] | 2612 | * The same could be achieved by writing to the physical memory map, but it's |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2613 | * much more difficult due to SMM remapping, ME stolen memory, GFX stolen memory, |
| 2614 | * and firmware running in x86_32. |
| 2615 | */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2616 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2617 | rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2618 | for (bank = 0; bank < 8; bank++) { |
| 2619 | for (row = 0; row < rowsize; row += 16) { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2620 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2621 | u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); |
| 2622 | const struct iosav_ssq sequence[] = { |
| 2623 | /* |
| 2624 | * DRAM command ACT |
| 2625 | * Opens the row for writing. |
| 2626 | */ |
| 2627 | [0] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2628 | .sp_cmd_ctrl = { |
| 2629 | .command = IOSAV_ACT, |
| 2630 | .ranksel_ap = 1, |
| 2631 | }, |
| 2632 | .subseq_ctrl = { |
| 2633 | .cmd_executions = 1, |
| 2634 | .cmd_delay_gap = gap, |
| 2635 | .post_ssq_wait = ctrl->tRCD, |
| 2636 | .data_direction = SSQ_NA, |
| 2637 | }, |
| 2638 | .sp_cmd_addr = { |
| 2639 | .address = row, |
| 2640 | .rowbits = 6, |
| 2641 | .bank = bank, |
| 2642 | .rank = slotrank, |
| 2643 | }, |
| 2644 | .addr_update = { |
| 2645 | .inc_addr_1 = 1, |
| 2646 | .addr_wrap = 18, |
| 2647 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2648 | }, |
| 2649 | /* |
| 2650 | * DRAM command WR |
| 2651 | * Writes (128 + 1) * 8 (burst length) * 8 (bus width) |
| 2652 | * bytes. |
| 2653 | */ |
| 2654 | [1] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2655 | .sp_cmd_ctrl = { |
| 2656 | .command = IOSAV_WR, |
| 2657 | .ranksel_ap = 1, |
| 2658 | }, |
| 2659 | .subseq_ctrl = { |
| 2660 | .cmd_executions = 129, |
| 2661 | .cmd_delay_gap = 4, |
| 2662 | .post_ssq_wait = ctrl->tWTR + |
| 2663 | ctrl->CWL + 8, |
| 2664 | .data_direction = SSQ_WR, |
| 2665 | }, |
| 2666 | .sp_cmd_addr = { |
| 2667 | .address = row, |
| 2668 | .rowbits = 0, |
| 2669 | .bank = bank, |
| 2670 | .rank = slotrank, |
| 2671 | }, |
| 2672 | .addr_update = { |
| 2673 | .inc_addr_8 = 1, |
| 2674 | .addr_wrap = 9, |
| 2675 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2676 | }, |
| 2677 | /* |
| 2678 | * DRAM command PRE |
| 2679 | * Closes the row. |
| 2680 | */ |
| 2681 | [2] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2682 | .sp_cmd_ctrl = { |
| 2683 | .command = IOSAV_PRE, |
| 2684 | .ranksel_ap = 1, |
| 2685 | }, |
| 2686 | .subseq_ctrl = { |
| 2687 | .cmd_executions = 1, |
| 2688 | .cmd_delay_gap = 4, |
| 2689 | .post_ssq_wait = ctrl->tRP, |
| 2690 | .data_direction = SSQ_NA, |
| 2691 | }, |
| 2692 | .sp_cmd_addr = { |
| 2693 | .address = 0, |
| 2694 | .rowbits = 6, |
| 2695 | .bank = bank, |
| 2696 | .rank = slotrank, |
| 2697 | }, |
| 2698 | .addr_update = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 2699 | .addr_wrap = 18, |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2700 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2701 | }, |
| 2702 | }; |
| 2703 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2704 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2705 | iosav_run_queue(channel, 16, 0); |
| 2706 | |
| 2707 | wait_for_iosav(channel); |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2708 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2709 | } |
| 2710 | } |
| 2711 | } |
| 2712 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2713 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2714 | { |
| 2715 | int channel; |
| 2716 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2717 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2718 | static u32 seeds[NUM_CHANNELS][3] = { |
| 2719 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 2720 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 2721 | }; |
| 2722 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2723 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2724 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 2725 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 2726 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2727 | } |
| 2728 | } |
| 2729 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 2730 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2731 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2732 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2733 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2734 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2735 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2736 | } |
| 2737 | } |
| 2738 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2739 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2740 | { |
| 2741 | int channel; |
| 2742 | |
| 2743 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2744 | /* Always drive command bus */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2745 | MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2746 | } |
| 2747 | |
| 2748 | udelay(1); |
| 2749 | |
| 2750 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2751 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2752 | } |
| 2753 | } |
| 2754 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2755 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2756 | { |
Angel Pons | 1146332 | 2020-11-19 11:04:28 +0100 | [diff] [blame] | 2757 | /* Use a larger delay when running fast to improve stability */ |
| 2758 | const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; |
| 2759 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2760 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 2761 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2762 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2763 | int min_pi = 10000; |
| 2764 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2765 | |
| 2766 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2767 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 2768 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2769 | } |
| 2770 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2771 | const u32 tWRDRDD = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2772 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2773 | const u32 val = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 3 : 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2774 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 2775 | dram_odt_stretch(ctrl, channel); |
| 2776 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2777 | const union tc_rwp_reg tc_rwp = { |
| 2778 | .tRRDR = 0, |
| 2779 | .tRRDD = val, |
| 2780 | .tWWDR = val, |
| 2781 | .tWWDD = val, |
Angel Pons | 1146332 | 2020-11-19 11:04:28 +0100 | [diff] [blame] | 2782 | .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc, |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2783 | .tWRDRDD = tWRDRDD, |
| 2784 | .tRWSR = 2, |
| 2785 | .dec_wrd = 1, |
| 2786 | }; |
| 2787 | MCHBAR32(TC_RWP_ch(channel)) = tc_rwp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2788 | } |
| 2789 | } |
| 2790 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2791 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2792 | { |
| 2793 | int channel; |
| 2794 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2795 | MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel]; |
| 2796 | MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2797 | } |
| 2798 | } |
| 2799 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2800 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 2801 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2802 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2803 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2804 | } |
| 2805 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2806 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2807 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2808 | { |
| 2809 | int channel; |
| 2810 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 2811 | int t3_ns; |
| 2812 | u32 r32; |
| 2813 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2814 | /* FIXME: This register only exists on Ivy Bridge */ |
| 2815 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2816 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2817 | FOR_ALL_CHANNELS { |
| 2818 | union tc_othp_reg tc_othp = { |
| 2819 | .raw = MCHBAR32(TC_OTHP_ch(channel)), |
| 2820 | }; |
| 2821 | tc_othp.tCPDED = 1; |
| 2822 | MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; |
| 2823 | } |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 2824 | |
Angel Pons | 09fc4b9 | 2020-11-19 12:02:07 +0100 | [diff] [blame] | 2825 | /* 64 DCLKs until idle, decision per rank */ |
| 2826 | MCHBAR32(PM_PDWN_CONFIG) = get_power_down_mode(ctrl) << 8 | 64; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 2827 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 2828 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2829 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 2830 | |
Angel Pons | c728e25 | 2021-01-03 16:47:09 +0100 | [diff] [blame] | 2831 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; |
| 2832 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2833 | |
| 2834 | FOR_ALL_CHANNELS { |
| 2835 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2836 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2837 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2838 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2839 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2840 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2841 | case 1: |
| 2842 | case 4: |
| 2843 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2844 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2845 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2846 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2847 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2848 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2849 | break; |
| 2850 | } |
| 2851 | } |
| 2852 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 2853 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2854 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 2855 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 2856 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2857 | FOR_ALL_CHANNELS { |
| 2858 | union tc_rfp_reg tc_rfp = { |
| 2859 | .raw = MCHBAR32(TC_RFP_ch(channel)), |
| 2860 | }; |
| 2861 | tc_rfp.refresh_2x_control = 1; |
| 2862 | MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; |
| 2863 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2864 | |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2865 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); |
| 2866 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2867 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2868 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2869 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2870 | FOR_ALL_POPULATED_CHANNELS |
| 2871 | break; |
| 2872 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2873 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 2874 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2875 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2876 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2877 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2878 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2879 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2880 | t1_ns += 500; |
| 2881 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2882 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2883 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2884 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2885 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2886 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2887 | t3_ns = 500; |
| 2888 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2889 | |
| 2890 | /* The graphics driver will use these watermark values */ |
| 2891 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2892 | MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2893 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 2894 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2895 | } |
| 2896 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2897 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2898 | { |
Angel Pons | c674223 | 2020-11-15 13:26:21 +0100 | [diff] [blame] | 2899 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2900 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2901 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 2902 | const union tc_rap_reg tc_rap = { |
| 2903 | .tRRD = ctrl->tRRD, |
| 2904 | .tRTP = ctrl->tRTP, |
| 2905 | .tCKE = ctrl->tCKE, |
| 2906 | .tWTR = ctrl->tWTR, |
| 2907 | .tFAW = ctrl->tFAW, |
| 2908 | .tWR = ctrl->tWR, |
| 2909 | .tCMD = ctrl->cmd_stretch[channel], |
| 2910 | }; |
| 2911 | MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2912 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2913 | |
| 2914 | udelay(1); |
| 2915 | |
| 2916 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2917 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2918 | } |
| 2919 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2920 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2921 | MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2922 | |
| 2923 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2924 | udelay(1); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2925 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2926 | } |
| 2927 | |
| 2928 | printram("CPE\n"); |
| 2929 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2930 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 2931 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2932 | |
| 2933 | printram("CP5b\n"); |
| 2934 | |
| 2935 | FOR_ALL_POPULATED_CHANNELS { |
| 2936 | program_timings(ctrl, channel); |
| 2937 | } |
| 2938 | |
| 2939 | u32 reg, addr; |
| 2940 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2941 | /* Poll for RCOMP */ |
| 2942 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 2943 | ; |
| 2944 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2945 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2946 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2947 | } while ((reg & 0x14) == 0); |
| 2948 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2949 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2950 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2951 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2952 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2953 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2954 | udelay(500); |
| 2955 | |
| 2956 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2957 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2958 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2959 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2960 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2961 | MCHBAR32(addr) = reg; |
| 2962 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2963 | /* Wait 10ns for ranks to settle */ |
| 2964 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2965 | |
| 2966 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 2967 | MCHBAR32(addr) = reg; |
| 2968 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2969 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2970 | write_reset(ctrl); |
| 2971 | } |
| 2972 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2973 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2974 | dram_mrscommands(ctrl); |
| 2975 | |
| 2976 | printram("CP5c\n"); |
| 2977 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2978 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2979 | |
| 2980 | FOR_ALL_CHANNELS { |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 2981 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2982 | udelay(2); |
| 2983 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2984 | } |