Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 3 | #include <assert.h> |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 6 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 7 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 10 | #include <northbridge/intel/sandybridge/chip.h> |
| 11 | #include <device/pci_def.h> |
| 12 | #include <delay.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 13 | #include <types.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 14 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 15 | #include "raminit_native.h" |
| 16 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 17 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 18 | #include "sandybridge.h" |
| 19 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 20 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 21 | |
| 22 | static void sfence(void) |
| 23 | { |
| 24 | asm volatile ("sfence"); |
| 25 | } |
| 26 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 27 | /* Toggle IO reset bit */ |
| 28 | static void toggle_io_reset(void) |
| 29 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 30 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 31 | MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 32 | udelay(1); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 33 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 34 | udelay(1); |
| 35 | } |
| 36 | |
| 37 | static u32 get_XOVER_CLK(u8 rankmap) |
| 38 | { |
| 39 | return rankmap << 24; |
| 40 | } |
| 41 | |
| 42 | static u32 get_XOVER_CMD(u8 rankmap) |
| 43 | { |
| 44 | u32 reg; |
| 45 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 46 | /* Enable xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 47 | reg = 0x4000; |
| 48 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 49 | /* Enable xover ctl */ |
| 50 | if (rankmap & 0x03) |
| 51 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 52 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 53 | if (rankmap & 0x0c) |
| 54 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 55 | |
| 56 | return reg; |
| 57 | } |
| 58 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 59 | void dram_find_common_params(ramctr_timing *ctrl) |
| 60 | { |
| 61 | size_t valid_dimms; |
| 62 | int channel, slot; |
| 63 | dimm_info *dimms = &ctrl->info; |
| 64 | |
| 65 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 66 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 67 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 68 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 69 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 70 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 71 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 72 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 73 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 74 | valid_dimms++; |
| 75 | |
| 76 | /* Find all possible CAS combinations */ |
| 77 | ctrl->cas_supported &= dimm->cas_supported; |
| 78 | |
| 79 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 80 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 81 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 82 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 83 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 84 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 85 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 86 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 87 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 88 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 89 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 90 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 91 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 92 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 96 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 97 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 98 | if (!valid_dimms) |
| 99 | die("No valid DIMMs found"); |
| 100 | } |
| 101 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 102 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 103 | { |
| 104 | u32 reg; |
| 105 | int channel; |
| 106 | |
| 107 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 108 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 109 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 110 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 111 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 112 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 113 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 114 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 115 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 116 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 120 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 121 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 122 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 123 | |
| 124 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 125 | /* |
| 126 | * ODT stretch: |
| 127 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 128 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 129 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 130 | if (stretch == 2) |
| 131 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 132 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 133 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 134 | MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 135 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 136 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 137 | addr = TC_OTHP_ch(channel); |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 138 | union tc_othp_reg tc_othp = { |
| 139 | .raw = MCHBAR32(addr), |
| 140 | }; |
| 141 | tc_othp.odt_delay_d0 = stretch; |
| 142 | tc_othp.odt_delay_d1 = stretch; |
| 143 | MCHBAR32(addr) = tc_othp.raw; |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 144 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 145 | } |
| 146 | } |
| 147 | |
| 148 | void dram_timing_regs(ramctr_timing *ctrl) |
| 149 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 150 | int channel; |
| 151 | |
| 152 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 153 | /* BIN parameters */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 154 | const union tc_dbp_reg tc_dbp = { |
| 155 | .tRCD = ctrl->tRCD, |
| 156 | .tRP = ctrl->tRP, |
| 157 | .tAA = ctrl->CAS, |
| 158 | .tCWL = ctrl->CWL, |
| 159 | .tRAS = ctrl->tRAS, |
| 160 | }; |
| 161 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); |
| 162 | MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 163 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 164 | /* Regular access parameters */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 165 | const union tc_rap_reg tc_rap = { |
| 166 | .tRRD = ctrl->tRRD, |
| 167 | .tRTP = ctrl->tRTP, |
| 168 | .tCKE = ctrl->tCKE, |
| 169 | .tWTR = ctrl->tWTR, |
| 170 | .tFAW = ctrl->tFAW, |
| 171 | .tWR = ctrl->tWR, |
| 172 | .tCMD = 3, |
| 173 | }; |
| 174 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); |
| 175 | MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 176 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 177 | /* Other parameters */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 178 | const union tc_othp_reg tc_othp = { |
| 179 | .tXPDLL = ctrl->tXPDLL, |
| 180 | .tXP = ctrl->tXP, |
| 181 | .tAONPD = ctrl->tAONPD, |
| 182 | .tCPDED = 2, |
| 183 | .tPRPDEN = 2, |
| 184 | }; |
| 185 | printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); |
| 186 | MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 187 | |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 188 | /* Debug parameters - only applies to Ivy Bridge */ |
| 189 | if (IS_IVY_CPU(ctrl->cpu)) { |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 190 | /* |
| 191 | * If tXP and tXPDLL are very high, we need to increase them by one. |
| 192 | * This can only happen on Ivy Bridge, and when overclocking the RAM. |
| 193 | */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 194 | const union tc_dtp_reg tc_dtp = { |
| 195 | .overclock_tXP = ctrl->tXP >= 8, |
| 196 | .overclock_tXPDLL = ctrl->tXPDLL >= 32, |
| 197 | }; |
| 198 | MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 199 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 200 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 201 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 202 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 203 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 204 | * TC-Refresh timing parameters: |
| 205 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 206 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 207 | */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 208 | const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 209 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 210 | const union tc_rftp_reg tc_rftp = { |
| 211 | .tREFI = ctrl->tREFI, |
| 212 | .tRFC = ctrl->tRFC, |
| 213 | .tREFIx9 = val32 / 1024, |
| 214 | }; |
| 215 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); |
| 216 | MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 217 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 218 | union tc_rfp_reg tc_rfp = { |
| 219 | .raw = MCHBAR32(TC_RFP_ch(channel)), |
| 220 | }; |
| 221 | tc_rfp.oref_ri = 0xff; |
| 222 | MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 223 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 224 | /* Self-refresh timing parameters */ |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 225 | const union tc_srftp_reg tc_srftp = { |
| 226 | .tXSDLL = tDLLK, |
| 227 | .tXS_offset = ctrl->tXSOffset, |
| 228 | .tZQOPER = tDLLK - ctrl->tXSOffset, |
| 229 | .tMOD = ctrl->tMOD - 8, |
| 230 | }; |
| 231 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); |
| 232 | MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 233 | } |
| 234 | } |
| 235 | |
| 236 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 237 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 238 | int channel; |
| 239 | dimm_info *info = &ctrl->info; |
| 240 | |
| 241 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 242 | dimm_attr *dimmA, *dimmB; |
| 243 | u32 reg = 0; |
| 244 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 245 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 246 | dimmA = &info->dimm[channel][0]; |
| 247 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 248 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 249 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 250 | dimmA = &info->dimm[channel][1]; |
| 251 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 252 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 253 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 254 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 255 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 256 | reg |= (dimmA->size_mb / 256) << 0; |
| 257 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 258 | reg |= (dimmA->width / 8 - 1) << 19; |
| 259 | } |
| 260 | |
| 261 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 262 | reg |= (dimmB->size_mb / 256) << 8; |
| 263 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 264 | reg |= (dimmB->width / 8 - 1) << 20; |
| 265 | } |
| 266 | |
Patrick Rudolph | 4e0cd82 | 2020-05-01 18:35:36 +0200 | [diff] [blame] | 267 | /* |
| 268 | * Rank interleave: Bit 16 of the physical address space sets |
| 269 | * the rank to use in a dual single rank DIMM configuration. |
| 270 | * That results in every 64KiB being interleaved between two ranks. |
| 271 | */ |
| 272 | reg |= 1 << 21; |
| 273 | /* Enhanced interleave */ |
| 274 | reg |= 1 << 22; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 275 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 276 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 277 | ctrl->mad_dimm[channel] = reg; |
| 278 | } else { |
| 279 | ctrl->mad_dimm[channel] = 0; |
| 280 | } |
| 281 | } |
| 282 | } |
| 283 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 284 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 285 | { |
| 286 | int channel; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 287 | u32 ecc; |
| 288 | |
| 289 | if (ctrl->ecc_enabled) |
| 290 | ecc = training ? (1 << 24) : (3 << 24); |
| 291 | else |
| 292 | ecc = 0; |
| 293 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 294 | FOR_ALL_CHANNELS { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 295 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 296 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 297 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 298 | if (ctrl->ecc_enabled) |
| 299 | udelay(10); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 300 | } |
| 301 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 302 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 303 | { |
| 304 | u32 reg, ch0size, ch1size; |
| 305 | u8 val; |
| 306 | reg = 0; |
| 307 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 308 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 309 | if (training) { |
| 310 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 311 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 312 | } else { |
| 313 | ch0size = ctrl->channel_size_mb[0]; |
| 314 | ch1size = ctrl->channel_size_mb[1]; |
| 315 | } |
| 316 | |
| 317 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 318 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 319 | val = ch1size / 256; |
| 320 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 321 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 322 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 323 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 324 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 325 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 326 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 327 | val = ch0size / 256; |
| 328 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 329 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 330 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 331 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 332 | } |
| 333 | } |
| 334 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 335 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 336 | |
| 337 | static unsigned int get_mmio_size(void) |
| 338 | { |
| 339 | const struct device *dev; |
| 340 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 341 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 342 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 343 | if (dev) |
| 344 | cfg = dev->chip_info; |
| 345 | |
| 346 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 347 | if (!cfg || cfg->pci_mmio_size == 0) |
| 348 | return DEFAULT_PCI_MMIO_SIZE; |
| 349 | else |
| 350 | return cfg->pci_mmio_size; |
| 351 | } |
| 352 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 353 | /* |
| 354 | * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. |
| 355 | * The ME/PCU/.. has the ability to change this. |
| 356 | * Return 0: ECC is optional |
| 357 | * Return 1: ECC is forced |
| 358 | */ |
| 359 | bool get_host_ecc_forced(void) |
| 360 | { |
| 361 | /* read Capabilities A Register */ |
| 362 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 363 | return !!(reg32 & (1 << 24)); |
| 364 | } |
| 365 | |
| 366 | /* |
| 367 | * Returns the ECC capability. |
| 368 | * The ME/PCU/.. has the ability to change this. |
| 369 | * Return 0: ECC is disabled |
| 370 | * Return 1: ECC is possible |
| 371 | */ |
| 372 | bool get_host_ecc_cap(void) |
| 373 | { |
| 374 | /* read Capabilities A Register */ |
| 375 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 376 | return !(reg32 & (1 << 25)); |
| 377 | } |
| 378 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 379 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 380 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 381 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 382 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 383 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 384 | uint16_t ggc; |
| 385 | |
| 386 | mmiosize = get_mmio_size(); |
| 387 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 388 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 389 | if (!(ggc & 2)) { |
| 390 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 391 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 392 | } else { |
| 393 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 394 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 398 | |
| 399 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 400 | |
| 401 | mestolenbase = tom - me_uma_size; |
| 402 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 403 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 404 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 405 | gfxstolenbase = toludbase - gfxstolen; |
| 406 | gttbase = gfxstolenbase - gttsize; |
| 407 | |
| 408 | tsegbase = gttbase - tsegsize; |
| 409 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 410 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 411 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 412 | tsegbase &= ~(tsegsize - 1); |
| 413 | |
| 414 | gttbase -= tsegbasedelta; |
| 415 | gfxstolenbase -= tsegbasedelta; |
| 416 | toludbase -= tsegbasedelta; |
| 417 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 418 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 419 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 420 | /* Reclaim is possible */ |
| 421 | reclaim = 1; |
| 422 | remapbase = MAX(4096, tom - me_uma_size); |
| 423 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 424 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 425 | } else { |
| 426 | // Reclaim not possible |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 427 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 428 | touudbase = tom - me_uma_size; |
| 429 | } |
| 430 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 431 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 432 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 433 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 434 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 435 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 436 | val = tom & 0xfff; |
| 437 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 438 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 439 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 440 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 441 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 442 | val = tom & 0xfffff000; |
| 443 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 444 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 445 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 446 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 447 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 448 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 449 | val = toludbase & 0xfff; |
| 450 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 451 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 452 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 453 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 454 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 455 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 456 | val = touudbase & 0xfff; |
| 457 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 458 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 459 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 460 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 461 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 462 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 463 | val = touudbase & 0xfffff000; |
| 464 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 465 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 466 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 467 | |
| 468 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 469 | /* REMAP BASE */ |
| 470 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 471 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 472 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 473 | /* REMAP LIMIT */ |
| 474 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 475 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 476 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 477 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 478 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 479 | val = tsegbase & 0xfff; |
| 480 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 481 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 482 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 483 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 484 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 485 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 486 | val = gfxstolenbase & 0xfff; |
| 487 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 488 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 489 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 490 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 491 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 492 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 493 | val = gttbase & 0xfff; |
| 494 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 495 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 496 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 497 | |
| 498 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 499 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 500 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 501 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 502 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 503 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 504 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 505 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 506 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 507 | val = mestolenbase & 0xfff; |
| 508 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 509 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 510 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 511 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 512 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 513 | val = mestolenbase & 0xfffff000; |
| 514 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 515 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 516 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 517 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 518 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 519 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 520 | val = (0x80000 - me_uma_size) & 0xfff; |
| 521 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 522 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 523 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 524 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 525 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 526 | } |
| 527 | } |
| 528 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 529 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 530 | { |
| 531 | int channel, slotrank; |
| 532 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 533 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 534 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 535 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 536 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 537 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 538 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 539 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 540 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 541 | iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 542 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 543 | /* |
| 544 | * Execute command queue - why is bit 22 set here?! |
| 545 | * |
| 546 | * This is actually using the IOSAV state machine as a timer, so refresh is allowed. |
| 547 | */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 548 | iosav_run_queue(channel, 1, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 549 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 550 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 551 | } |
| 552 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 553 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 554 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 555 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 556 | int channel; |
| 557 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 558 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 559 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 560 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 561 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 562 | } while ((reg & 0x14) == 0); |
| 563 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 564 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 565 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 566 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 567 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 568 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 569 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 570 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 571 | /* Assert DIMM reset signal */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 572 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 573 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 574 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 575 | udelay(200); |
| 576 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 577 | /* Deassert DIMM reset signal */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 578 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 579 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 580 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 581 | udelay(500); |
| 582 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 583 | /* Enable DCLK */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 584 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 585 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 586 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 587 | udelay(1); |
| 588 | |
| 589 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 590 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 591 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 592 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 593 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 594 | /* Wait 10ns for ranks to settle */ |
| 595 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 596 | |
| 597 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 598 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 599 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 600 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 601 | write_reset(ctrl); |
| 602 | } |
| 603 | } |
| 604 | |
Angel Pons | 3d3bf48 | 2020-11-14 16:18:15 +0100 | [diff] [blame] | 605 | /* |
| 606 | * DDR3 Rank1 Address mirror swap the following pins: |
| 607 | * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 |
| 608 | */ |
| 609 | static void ddr3_mirror_mrreg(int *bank, u32 *addr) |
| 610 | { |
| 611 | *bank = ((*bank >> 1) & 1) | ((*bank << 1) & 2); |
| 612 | *addr = (*addr & ~0x1f8) | ((*addr >> 1) & 0xa8) | ((*addr & 0xa8) << 1); |
| 613 | } |
| 614 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 615 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 616 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 617 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 618 | |
Angel Pons | 3d3bf48 | 2020-11-14 16:18:15 +0100 | [diff] [blame] | 619 | if (ctrl->rank_mirror[channel][slotrank]) |
| 620 | ddr3_mirror_mrreg(®, &val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 621 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 622 | const struct iosav_ssq sequence[] = { |
| 623 | /* DRAM command MRS */ |
| 624 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 625 | .sp_cmd_ctrl = { |
| 626 | .command = IOSAV_MRS, |
| 627 | }, |
| 628 | .subseq_ctrl = { |
| 629 | .cmd_executions = 1, |
| 630 | .cmd_delay_gap = 4, |
| 631 | .post_ssq_wait = 4, |
| 632 | .data_direction = SSQ_NA, |
| 633 | }, |
| 634 | .sp_cmd_addr = { |
| 635 | .address = val, |
| 636 | .rowbits = 6, |
| 637 | .bank = reg, |
| 638 | .rank = slotrank, |
| 639 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 640 | }, |
| 641 | /* DRAM command MRS */ |
| 642 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 643 | .sp_cmd_ctrl = { |
| 644 | .command = IOSAV_MRS, |
| 645 | .ranksel_ap = 1, |
| 646 | }, |
| 647 | .subseq_ctrl = { |
| 648 | .cmd_executions = 1, |
| 649 | .cmd_delay_gap = 4, |
| 650 | .post_ssq_wait = 4, |
| 651 | .data_direction = SSQ_NA, |
| 652 | }, |
| 653 | .sp_cmd_addr = { |
| 654 | .address = val, |
| 655 | .rowbits = 6, |
| 656 | .bank = reg, |
| 657 | .rank = slotrank, |
| 658 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 659 | }, |
| 660 | /* DRAM command MRS */ |
| 661 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 662 | .sp_cmd_ctrl = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 663 | .command = IOSAV_MRS, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 664 | }, |
| 665 | .subseq_ctrl = { |
| 666 | .cmd_executions = 1, |
| 667 | .cmd_delay_gap = 4, |
| 668 | .post_ssq_wait = ctrl->tMOD, |
| 669 | .data_direction = SSQ_NA, |
| 670 | }, |
| 671 | .sp_cmd_addr = { |
| 672 | .address = val, |
| 673 | .rowbits = 6, |
| 674 | .bank = reg, |
| 675 | .rank = slotrank, |
| 676 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 677 | }, |
| 678 | }; |
| 679 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 680 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 681 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 682 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 683 | } |
| 684 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 685 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 686 | { |
| 687 | u16 mr0reg, mch_cas, mch_wr; |
| 688 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 689 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 690 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 691 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 692 | if (ctrl->CAS < 12) { |
| 693 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 694 | } else { |
| 695 | mch_cas = (u16) (ctrl->CAS - 12); |
| 696 | mch_cas = ((mch_cas << 1) | 0x1); |
| 697 | } |
| 698 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 699 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 700 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 701 | |
Angel Pons | 2bf28ed | 2020-11-12 13:49:59 +0100 | [diff] [blame] | 702 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 703 | mr0reg = 1 << 8; |
| 704 | |
| 705 | mr0reg |= (mch_cas & 0x1) << 2; |
| 706 | mr0reg |= (mch_cas & 0xe) << 3; |
| 707 | mr0reg |= mch_wr << 9; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 708 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 709 | /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ |
Angel Pons | 2bf28ed | 2020-11-12 13:49:59 +0100 | [diff] [blame] | 710 | mr0reg |= !is_mobile << 12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 711 | return mr0reg; |
| 712 | } |
| 713 | |
| 714 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 715 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 716 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 717 | } |
| 718 | |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 719 | static odtmap get_ODT(ramctr_timing *ctrl, int channel) |
Angel Pons | 1a9b5aa | 2020-11-12 13:51:46 +0100 | [diff] [blame] | 720 | { |
| 721 | /* Get ODT based on rankmap */ |
| 722 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
| 723 | |
| 724 | if (dimms_per_ch == 1) { |
| 725 | return (const odtmap){60, 60}; |
| 726 | } else { |
| 727 | return (const odtmap){120, 30}; |
| 728 | } |
| 729 | } |
| 730 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 731 | static u32 encode_odt(u32 odt) |
| 732 | { |
| 733 | switch (odt) { |
| 734 | case 30: |
| 735 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 736 | case 60: |
| 737 | return (1 << 2); // RZQ/4 |
| 738 | case 120: |
| 739 | return (1 << 6); // RZQ/2 |
| 740 | default: |
| 741 | case 0: |
| 742 | return 0; |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 747 | { |
| 748 | odtmap odt; |
| 749 | u32 mr1reg; |
| 750 | |
Angel Pons | f999748 | 2020-11-12 16:02:52 +0100 | [diff] [blame] | 751 | odt = get_ODT(ctrl, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 752 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 753 | |
| 754 | mr1reg |= encode_odt(odt.rttnom); |
| 755 | |
| 756 | return mr1reg; |
| 757 | } |
| 758 | |
| 759 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 760 | { |
| 761 | u16 mr1reg; |
| 762 | |
| 763 | mr1reg = make_mr1(ctrl, rank, channel); |
| 764 | |
| 765 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 766 | } |
| 767 | |
| 768 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 769 | { |
Angel Pons | 868bca2 | 2020-11-13 13:38:04 +0100 | [diff] [blame] | 770 | const u16 pasr = 0; |
| 771 | const u16 cwl = ctrl->CWL - 5; |
| 772 | const odtmap odt = get_ODT(ctrl, channel); |
| 773 | |
Angel Pons | dca3cb5 | 2020-11-13 13:42:07 +0100 | [diff] [blame] | 774 | int srt = 0; |
Angel Pons | dca3cb5 | 2020-11-13 13:42:07 +0100 | [diff] [blame] | 775 | if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) |
| 776 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 777 | |
Angel Pons | 868bca2 | 2020-11-13 13:38:04 +0100 | [diff] [blame] | 778 | u16 mr2reg = 0; |
| 779 | mr2reg |= pasr; |
| 780 | mr2reg |= cwl << 3; |
| 781 | mr2reg |= ctrl->auto_self_refresh << 6; |
| 782 | mr2reg |= srt << 7; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 783 | mr2reg |= (odt.rttwr / 60) << 9; |
| 784 | |
| 785 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
Angel Pons | 7f1363d | 2020-11-13 13:31:58 +0100 | [diff] [blame] | 786 | |
| 787 | /* Program MR2 shadow */ |
| 788 | u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); |
| 789 | |
| 790 | reg32 &= 3 << 14 | 3 << 6; |
| 791 | |
| 792 | reg32 |= mr2reg & ~(3 << 6); |
| 793 | |
| 794 | if (rank & 1) { |
| 795 | if (srt) |
| 796 | reg32 |= 1 << (rank / 2 + 6); |
| 797 | } else { |
| 798 | if (ctrl->rank_mirror[channel][rank]) |
| 799 | reg32 |= 1 << (rank / 2 + 14); |
| 800 | } |
| 801 | MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 802 | } |
| 803 | |
| 804 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 805 | { |
| 806 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 807 | } |
| 808 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 809 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 810 | { |
| 811 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 812 | int channel; |
| 813 | |
| 814 | FOR_ALL_POPULATED_CHANNELS { |
| 815 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 816 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 817 | dram_mr2(ctrl, slotrank, channel); |
| 818 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 819 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 820 | dram_mr3(ctrl, slotrank, channel); |
| 821 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 822 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 823 | dram_mr1(ctrl, slotrank, channel); |
| 824 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 825 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 826 | dram_mr0(ctrl, slotrank, channel); |
| 827 | } |
| 828 | } |
| 829 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 830 | const struct iosav_ssq zqcl_sequence[] = { |
| 831 | /* DRAM command NOP (without ODT nor chip selects) */ |
| 832 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 833 | .sp_cmd_ctrl = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 834 | .command = IOSAV_NOP & ~(0xff << 8), |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 835 | }, |
| 836 | .subseq_ctrl = { |
| 837 | .cmd_executions = 1, |
| 838 | .cmd_delay_gap = 4, |
| 839 | .post_ssq_wait = 15, |
| 840 | .data_direction = SSQ_NA, |
| 841 | }, |
| 842 | .sp_cmd_addr = { |
| 843 | .address = 2, |
| 844 | .rowbits = 6, |
| 845 | .bank = 0, |
| 846 | .rank = 0, |
| 847 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 848 | }, |
| 849 | /* DRAM command ZQCL */ |
| 850 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 851 | .sp_cmd_ctrl = { |
| 852 | .command = IOSAV_ZQCS, |
| 853 | .ranksel_ap = 1, |
| 854 | }, |
| 855 | .subseq_ctrl = { |
| 856 | .cmd_executions = 1, |
| 857 | .cmd_delay_gap = 4, |
| 858 | .post_ssq_wait = 400, |
| 859 | .data_direction = SSQ_NA, |
| 860 | }, |
| 861 | .sp_cmd_addr = { |
| 862 | .address = 1024, |
| 863 | .rowbits = 6, |
| 864 | .bank = 0, |
| 865 | .rank = 0, |
| 866 | }, |
| 867 | .addr_update = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 868 | .inc_rank = 1, |
| 869 | .addr_wrap = 20, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 870 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 871 | }, |
| 872 | }; |
| 873 | iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 874 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 875 | /* Execute command queue on all channels. Do it four times. */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 876 | iosav_run_queue(BROADCAST_CH, 4, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 877 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 878 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 879 | /* Wait for ref drained */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 880 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 881 | } |
| 882 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 883 | /* Refresh enable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 884 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 885 | |
| 886 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 887 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 888 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 889 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 890 | |
| 891 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 892 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 893 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 894 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 895 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 896 | iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 897 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 898 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 899 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 900 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 901 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 902 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 903 | } |
| 904 | } |
| 905 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 906 | static const u32 lane_base[] = { |
| 907 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 908 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 909 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 910 | }; |
| 911 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 912 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 913 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 914 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 915 | int lane; |
| 916 | int slotrank, slot; |
| 917 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 918 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 919 | |
| 920 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 921 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 922 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 923 | } |
| 924 | |
| 925 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 926 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 927 | case 0: |
| 928 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 929 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 930 | break; |
| 931 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 932 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 933 | ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 934 | break; |
| 935 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 936 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 937 | ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 938 | break; |
| 939 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 940 | pi_coding_ctrl[slot] = |
| 941 | (ctrl->timings[channel][2 * slot].pi_coding + |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 942 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 943 | break; |
| 944 | } |
| 945 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 946 | /* Enable CMD XOVER */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 947 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 948 | reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; |
| 949 | reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 950 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 951 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 952 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 953 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 954 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 955 | /* Enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 956 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 957 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 958 | |
| 959 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 960 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 961 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 962 | if (shift < 0) |
| 963 | shift = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 964 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 965 | offset_pi_code = ctrl->pi_code_offset + shift; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 966 | |
| 967 | /* Set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 968 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 969 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 970 | } |
| 971 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 972 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 973 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 974 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 975 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 976 | reg_io_latency &= ~0xffff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 977 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 978 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 979 | |
| 980 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 981 | int post_timA_min_high = 7, pre_timA_min_high = 7; |
| 982 | int post_timA_max_high = 0, pre_timA_max_high = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 983 | int shift_402x = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 984 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 985 | |
| 986 | if (shift < 0) |
| 987 | shift = 0; |
| 988 | |
| 989 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 990 | post_timA_min_high = MIN(post_timA_min_high, |
| 991 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 992 | timA + shift) >> 6); |
| 993 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 994 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 995 | timA >> 6); |
| 996 | post_timA_max_high = MAX(post_timA_max_high, |
| 997 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 998 | timA + shift) >> 6); |
| 999 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 1000 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1001 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1002 | } |
| 1003 | |
| 1004 | if (pre_timA_max_high - pre_timA_min_high < |
| 1005 | post_timA_max_high - post_timA_min_high) |
| 1006 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1007 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1008 | else if (pre_timA_max_high - pre_timA_min_high > |
| 1009 | post_timA_max_high - post_timA_min_high) |
| 1010 | shift_402x = -1; |
| 1011 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 1012 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1013 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1014 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1015 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1016 | reg_roundtrip_latency |= |
| 1017 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1018 | shift_402x) << (8 * slotrank); |
| 1019 | |
| 1020 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1021 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1022 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1023 | timA + shift) & 0x3f) |
| 1024 | | |
| 1025 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1026 | rising + shift) << 8) |
| 1027 | | |
| 1028 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1029 | timA + shift - |
| 1030 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1031 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1032 | falling + shift) << 20)); |
| 1033 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1034 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1035 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1036 | timC + shift) & 0x3f) |
| 1037 | | |
| 1038 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1039 | timB + shift) & 0x3f) << 8) |
| 1040 | | |
| 1041 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1042 | timB + shift) & 0x1c0) << 9) |
| 1043 | | |
| 1044 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1045 | timC + shift) & 0x40) << 13)); |
| 1046 | } |
| 1047 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1048 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1049 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1050 | } |
| 1051 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1052 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1053 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1054 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1055 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1056 | iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1057 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1058 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1059 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1060 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1061 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1062 | } |
| 1063 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1064 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1065 | { |
| 1066 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1067 | |
| 1068 | return (MCHBAR32(lane_base[lane] + |
| 1069 | GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1070 | } |
| 1071 | |
| 1072 | struct run { |
| 1073 | int middle; |
| 1074 | int end; |
| 1075 | int start; |
| 1076 | int all; |
| 1077 | int length; |
| 1078 | }; |
| 1079 | |
| 1080 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1081 | { |
| 1082 | int i, ls; |
| 1083 | int bl = 0, bs = 0; |
| 1084 | struct run ret; |
| 1085 | |
| 1086 | ls = 0; |
| 1087 | for (i = 0; i < 2 * sz; i++) |
| 1088 | if (seq[i % sz]) { |
| 1089 | if (i - ls > bl) { |
| 1090 | bl = i - ls; |
| 1091 | bs = ls; |
| 1092 | } |
| 1093 | ls = i + 1; |
| 1094 | } |
| 1095 | if (bl == 0) { |
| 1096 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1097 | ret.start = 0; |
| 1098 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1099 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1100 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1101 | return ret; |
| 1102 | } |
| 1103 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1104 | ret.start = bs % sz; |
| 1105 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1106 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1107 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1108 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1109 | |
| 1110 | return ret; |
| 1111 | } |
| 1112 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1113 | static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1114 | { |
| 1115 | int timA; |
| 1116 | int statistics[NUM_LANES][128]; |
| 1117 | int lane; |
| 1118 | |
| 1119 | for (timA = 0; timA < 128; timA++) { |
| 1120 | FOR_ALL_LANES { |
| 1121 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1122 | } |
| 1123 | program_timings(ctrl, channel); |
| 1124 | |
| 1125 | test_timA(ctrl, channel, slotrank); |
| 1126 | |
| 1127 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1128 | statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1129 | } |
| 1130 | } |
| 1131 | FOR_ALL_LANES { |
| 1132 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1133 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1134 | upperA[lane] = rn.end; |
| 1135 | if (upperA[lane] < rn.middle) |
| 1136 | upperA[lane] += 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1137 | |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1138 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1139 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1140 | } |
| 1141 | } |
| 1142 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1143 | static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1144 | { |
| 1145 | int timA_delta; |
| 1146 | int statistics[NUM_LANES][51]; |
| 1147 | int lane, i; |
| 1148 | |
| 1149 | memset(statistics, 0, sizeof(statistics)); |
| 1150 | |
| 1151 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1152 | |
| 1153 | FOR_ALL_LANES { |
| 1154 | ctrl->timings[channel][slotrank].lanes[lane].timA |
| 1155 | = upperA[lane] + timA_delta + 0x40; |
| 1156 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1157 | program_timings(ctrl, channel); |
| 1158 | |
| 1159 | for (i = 0; i < 100; i++) { |
| 1160 | test_timA(ctrl, channel, slotrank); |
| 1161 | FOR_ALL_LANES { |
| 1162 | statistics[lane][timA_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1163 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1164 | } |
| 1165 | } |
| 1166 | } |
| 1167 | FOR_ALL_LANES { |
| 1168 | int last_zero, first_all; |
| 1169 | |
| 1170 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1171 | if (statistics[lane][last_zero + 25]) |
| 1172 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1173 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1174 | last_zero--; |
| 1175 | for (first_all = -25; first_all <= 25; first_all++) |
| 1176 | if (statistics[lane][first_all + 25] == 100) |
| 1177 | break; |
| 1178 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1179 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1180 | |
| 1181 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1182 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1183 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1184 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1185 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1186 | } |
| 1187 | } |
| 1188 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1189 | static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1190 | { |
| 1191 | int works[NUM_LANES]; |
| 1192 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1193 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1194 | while (1) { |
| 1195 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1196 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1197 | program_timings(ctrl, channel); |
| 1198 | test_timA(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1199 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1200 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1201 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1202 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1203 | if (works[lane]) |
| 1204 | some_works = 1; |
| 1205 | else |
| 1206 | all_works = 0; |
| 1207 | } |
| 1208 | if (all_works) |
| 1209 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1210 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1211 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1212 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1213 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1214 | channel, slotrank); |
| 1215 | return MAKE_ERR; |
| 1216 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1217 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1218 | printram("4024 -= 2;\n"); |
| 1219 | continue; |
| 1220 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1221 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1222 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1223 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1224 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1225 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1226 | channel, slotrank); |
| 1227 | return MAKE_ERR; |
| 1228 | } |
| 1229 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1230 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1231 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1232 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1233 | } |
| 1234 | } |
| 1235 | return 0; |
| 1236 | } |
| 1237 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1238 | static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1239 | { |
| 1240 | int lane; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1241 | u16 logic_delay_min = 7; |
| 1242 | u16 logic_delay_max = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1243 | |
| 1244 | FOR_ALL_LANES { |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1245 | const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; |
| 1246 | |
| 1247 | logic_delay_min = MIN(logic_delay_min, logic_delay); |
| 1248 | logic_delay_max = MAX(logic_delay_max, logic_delay); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1249 | } |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1250 | |
| 1251 | if (logic_delay_max < logic_delay_min) { |
| 1252 | printk(BIOS_EMERG, "Logic delay max < min (%u < %u): %d, %d\n", |
| 1253 | logic_delay_max, logic_delay_min, channel, slotrank); |
| 1254 | } |
| 1255 | |
| 1256 | assert(logic_delay_max >= logic_delay_min); |
| 1257 | |
| 1258 | return logic_delay_max - logic_delay_min; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1259 | } |
| 1260 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1261 | static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int slotrank, int prev) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1262 | { |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1263 | int latency_offset = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1264 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1265 | /* Get changed maxima */ |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1266 | const int post = get_logic_delay_delta(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1267 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1268 | if (prev < post) |
| 1269 | latency_offset = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1270 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1271 | else if (prev > post) |
| 1272 | latency_offset = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1273 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1274 | else |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1275 | latency_offset = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1276 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1277 | ctrl->timings[channel][slotrank].io_latency += latency_offset; |
| 1278 | ctrl->timings[channel][slotrank].roundtrip_latency += latency_offset; |
| 1279 | printram("4024 += %d;\n", latency_offset); |
| 1280 | printram("4028 += %d;\n", latency_offset); |
| 1281 | |
| 1282 | return post; |
| 1283 | } |
| 1284 | |
| 1285 | static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slotrank) |
| 1286 | { |
| 1287 | u16 logic_delay_min = 7; |
| 1288 | int lane; |
| 1289 | |
| 1290 | FOR_ALL_LANES { |
| 1291 | const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; |
| 1292 | |
| 1293 | logic_delay_min = MIN(logic_delay_min, logic_delay); |
| 1294 | } |
| 1295 | |
| 1296 | if (logic_delay_min >= 2) { |
| 1297 | printk(BIOS_WARNING, "Logic delay %u greater than 1: %d %d\n", |
| 1298 | logic_delay_min, channel, slotrank); |
| 1299 | } |
| 1300 | |
| 1301 | FOR_ALL_LANES { |
| 1302 | ctrl->timings[channel][slotrank].lanes[lane].timA -= logic_delay_min << 6; |
| 1303 | } |
| 1304 | ctrl->timings[channel][slotrank].io_latency -= logic_delay_min; |
| 1305 | printram("4028 -= %d;\n", logic_delay_min); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1306 | } |
| 1307 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1308 | /* |
| 1309 | * Compensate the skew between DQS and DQs. |
| 1310 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1311 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1312 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1313 | * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1314 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1315 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1316 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1317 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1318 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1319 | * DQ in phase the data being read is expected to alternate on every byte: |
| 1320 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1321 | * 0xFF 0x00 0xFF ... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1322 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1323 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1324 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1325 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1326 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1327 | { |
| 1328 | int channel, slotrank, lane; |
| 1329 | int err; |
| 1330 | |
| 1331 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1332 | int all_high, some_high; |
| 1333 | int upperA[NUM_LANES]; |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1334 | int prev; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1335 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1336 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1337 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1338 | iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1339 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1340 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1341 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1342 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1343 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1344 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1345 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1346 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1347 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1348 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1349 | find_rcven_pi_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1350 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1351 | all_high = 1; |
| 1352 | some_high = 0; |
| 1353 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1354 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1355 | some_high = 1; |
| 1356 | else |
| 1357 | all_high = 0; |
| 1358 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1359 | |
| 1360 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1361 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1362 | printram("4028--;\n"); |
| 1363 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1364 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1365 | upperA[lane] -= 0x40; |
| 1366 | |
| 1367 | } |
| 1368 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1369 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1370 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1371 | printram("4024++;\n"); |
| 1372 | printram("4028++;\n"); |
| 1373 | } |
| 1374 | |
| 1375 | program_timings(ctrl, channel); |
| 1376 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1377 | prev = get_logic_delay_delta(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1378 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1379 | err = find_roundtrip_latency(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1380 | if (err) |
| 1381 | return err; |
| 1382 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1383 | prev = align_rt_io_latency(ctrl, channel, slotrank, prev); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1384 | |
Angel Pons | f305339 | 2020-11-13 23:31:12 +0100 | [diff] [blame] | 1385 | fine_tune_rcven_pi(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1386 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1387 | prev = align_rt_io_latency(ctrl, channel, slotrank, prev); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1388 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1389 | compute_final_logic_delay(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1390 | |
Angel Pons | 12bd8ab | 2020-11-13 23:10:52 +0100 | [diff] [blame] | 1391 | align_rt_io_latency(ctrl, channel, slotrank, prev); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1392 | |
| 1393 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1394 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1395 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1396 | |
| 1397 | printram("final results:\n"); |
| 1398 | FOR_ALL_LANES |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1399 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1400 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1401 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1402 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1403 | |
| 1404 | toggle_io_reset(); |
| 1405 | } |
| 1406 | |
| 1407 | FOR_ALL_POPULATED_CHANNELS { |
| 1408 | program_timings(ctrl, channel); |
| 1409 | } |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 1410 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1411 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1412 | } |
| 1413 | return 0; |
| 1414 | } |
| 1415 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1416 | static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1417 | { |
| 1418 | int lane; |
| 1419 | |
| 1420 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1421 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1422 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1423 | } |
| 1424 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1425 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1426 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1427 | iosav_write_misc_write_sequence(ctrl, channel, slotrank, |
| 1428 | MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1429 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1430 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1431 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1432 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1433 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1434 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1435 | const struct iosav_ssq rd_sequence[] = { |
| 1436 | /* DRAM command PREA */ |
| 1437 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1438 | .sp_cmd_ctrl = { |
| 1439 | .command = IOSAV_PRE, |
| 1440 | .ranksel_ap = 1, |
| 1441 | }, |
| 1442 | .subseq_ctrl = { |
| 1443 | .cmd_executions = 1, |
| 1444 | .cmd_delay_gap = 3, |
| 1445 | .post_ssq_wait = ctrl->tRP, |
| 1446 | .data_direction = SSQ_NA, |
| 1447 | }, |
| 1448 | .sp_cmd_addr = { |
| 1449 | .address = 1024, |
| 1450 | .rowbits = 6, |
| 1451 | .bank = 0, |
| 1452 | .rank = slotrank, |
| 1453 | }, |
| 1454 | .addr_update = { |
| 1455 | .addr_wrap = 18, |
| 1456 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1457 | }, |
| 1458 | /* DRAM command ACT */ |
| 1459 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1460 | .sp_cmd_ctrl = { |
| 1461 | .command = IOSAV_ACT, |
| 1462 | .ranksel_ap = 1, |
| 1463 | }, |
| 1464 | .subseq_ctrl = { |
| 1465 | .cmd_executions = 8, |
| 1466 | .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), |
| 1467 | .post_ssq_wait = ctrl->CAS, |
| 1468 | .data_direction = SSQ_NA, |
| 1469 | }, |
| 1470 | .sp_cmd_addr = { |
| 1471 | .address = 0, |
| 1472 | .rowbits = 6, |
| 1473 | .bank = 0, |
| 1474 | .rank = slotrank, |
| 1475 | }, |
| 1476 | .addr_update = { |
| 1477 | .inc_bank = 1, |
| 1478 | .addr_wrap = 18, |
| 1479 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1480 | }, |
| 1481 | /* DRAM command RD */ |
| 1482 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1483 | .sp_cmd_ctrl = { |
| 1484 | .command = IOSAV_RD, |
| 1485 | .ranksel_ap = 1, |
| 1486 | }, |
| 1487 | .subseq_ctrl = { |
| 1488 | .cmd_executions = 500, |
| 1489 | .cmd_delay_gap = 4, |
| 1490 | .post_ssq_wait = MAX(ctrl->tRTP, 8), |
| 1491 | .data_direction = SSQ_RD, |
| 1492 | }, |
| 1493 | .sp_cmd_addr = { |
| 1494 | .address = 0, |
| 1495 | .rowbits = 0, |
| 1496 | .bank = 0, |
| 1497 | .rank = slotrank, |
| 1498 | }, |
| 1499 | .addr_update = { |
| 1500 | .inc_addr_8 = 1, |
| 1501 | .addr_wrap = 18, |
| 1502 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1503 | }, |
| 1504 | /* DRAM command PREA */ |
| 1505 | [3] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1506 | .sp_cmd_ctrl = { |
| 1507 | .command = IOSAV_PRE, |
| 1508 | .ranksel_ap = 1, |
| 1509 | }, |
| 1510 | .subseq_ctrl = { |
| 1511 | .cmd_executions = 1, |
| 1512 | .cmd_delay_gap = 3, |
| 1513 | .post_ssq_wait = ctrl->tRP, |
| 1514 | .data_direction = SSQ_NA, |
| 1515 | }, |
| 1516 | .sp_cmd_addr = { |
| 1517 | .address = 1024, |
| 1518 | .rowbits = 6, |
| 1519 | .bank = 0, |
| 1520 | .rank = slotrank, |
| 1521 | }, |
| 1522 | .addr_update = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 1523 | .addr_wrap = 18, |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1524 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1525 | }, |
| 1526 | }; |
| 1527 | iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1528 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1529 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1530 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1531 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1532 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1533 | } |
| 1534 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1535 | static void tx_dq_threshold_process(int *data, const int count) |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1536 | { |
| 1537 | int min = data[0]; |
| 1538 | int max = min; |
| 1539 | int i; |
| 1540 | for (i = 1; i < count; i++) { |
| 1541 | if (min > data[i]) |
| 1542 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1543 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1544 | if (max < data[i]) |
| 1545 | max = data[i]; |
| 1546 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1547 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1548 | for (i = 0; i < count; i++) |
| 1549 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1550 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1551 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1552 | } |
| 1553 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1554 | static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1555 | { |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1556 | int tx_dq; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1557 | int stats[NUM_LANES][MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1558 | int lane; |
| 1559 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1560 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1561 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1562 | iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1563 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1564 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1565 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1566 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1567 | for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { |
| 1568 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = tx_dq; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1569 | program_timings(ctrl, channel); |
| 1570 | |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1571 | test_tx_dq(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1572 | |
| 1573 | FOR_ALL_LANES { |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1574 | stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1575 | } |
| 1576 | } |
| 1577 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1578 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1579 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1580 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1581 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1582 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1583 | /* |
| 1584 | * With command training not being done yet, the lane can be erroneous. |
| 1585 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1586 | */ |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 1587 | tx_dq_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1588 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1589 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1590 | if (rn.all || rn.length < 8) { |
| 1591 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1592 | return MAKE_ERR; |
| 1593 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1594 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1595 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1596 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1597 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1598 | } |
| 1599 | return 0; |
| 1600 | } |
| 1601 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1602 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1603 | { |
| 1604 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1605 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1606 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1607 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1608 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1609 | return ret; |
| 1610 | } |
| 1611 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1612 | /* Each cacheline is 64 bits long */ |
| 1613 | static void program_wdb_pattern_length(int channel, const unsigned int num_cachelines) |
| 1614 | { |
| 1615 | MCHBAR8(IOSAV_DATA_CTL_ch(channel)) = num_cachelines / 8 - 1; |
| 1616 | } |
| 1617 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1618 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1619 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1620 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1621 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1622 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1623 | for (j = 0; j < 16; j++) |
| 1624 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1625 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1626 | sfence(); |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1627 | |
| 1628 | program_wdb_pattern_length(channel, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1629 | } |
| 1630 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1631 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1632 | { |
| 1633 | int ret = 0; |
| 1634 | int channel; |
| 1635 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1636 | return ret; |
| 1637 | } |
| 1638 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1639 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1640 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1641 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1642 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1643 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1644 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1645 | for (j = 0; j < 16; j++) |
| 1646 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1647 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1648 | for (j = 0; j < 16; j++) |
| 1649 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1650 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1651 | sfence(); |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1652 | |
| 1653 | program_wdb_pattern_length(channel, 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1654 | } |
| 1655 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1656 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1657 | { |
| 1658 | int channel, slotrank, lane; |
| 1659 | |
| 1660 | FOR_ALL_POPULATED_CHANNELS { |
| 1661 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1662 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1663 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1664 | } |
| 1665 | |
| 1666 | program_timings(ctrl, channel); |
| 1667 | |
| 1668 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1669 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1670 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1671 | iosav_write_read_mpr_sequence( |
| 1672 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1673 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1674 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1675 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1676 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1677 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1678 | } |
| 1679 | |
| 1680 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1681 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 1682 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1683 | } |
| 1684 | |
| 1685 | program_timings(ctrl, channel); |
| 1686 | |
| 1687 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1688 | wait_for_iosav(channel); |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1689 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1690 | iosav_write_read_mpr_sequence( |
| 1691 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1692 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1693 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1694 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1695 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1696 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1697 | } |
| 1698 | } |
| 1699 | } |
| 1700 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1701 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1702 | { |
Angel Pons | 59996e0 | 2020-11-14 16:34:35 +0100 | [diff] [blame] | 1703 | /* First DQS/DQS# rising edge after write leveling mode is programmed */ |
| 1704 | const u32 tWLMRD = 40; |
| 1705 | |
| 1706 | u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; |
| 1707 | int bank = 1; |
| 1708 | |
| 1709 | if (ctrl->rank_mirror[channel][slotrank]) |
| 1710 | ddr3_mirror_mrreg(&bank, &mr1reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1711 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1712 | wait_for_iosav(channel); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1713 | |
| 1714 | const struct iosav_ssq sequence[] = { |
Angel Pons | 59996e0 | 2020-11-14 16:34:35 +0100 | [diff] [blame] | 1715 | /* DRAM command MRS: enable DQs on this slotrank */ |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1716 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1717 | .sp_cmd_ctrl = { |
Angel Pons | 59996e0 | 2020-11-14 16:34:35 +0100 | [diff] [blame] | 1718 | .command = IOSAV_MRS, |
| 1719 | .ranksel_ap = 1, |
| 1720 | }, |
| 1721 | .subseq_ctrl = { |
| 1722 | .cmd_executions = 1, |
| 1723 | .cmd_delay_gap = 3, |
| 1724 | .post_ssq_wait = tWLMRD, |
| 1725 | .data_direction = SSQ_NA, |
| 1726 | }, |
| 1727 | .sp_cmd_addr = { |
| 1728 | .address = mr1reg, |
| 1729 | .rowbits = 6, |
| 1730 | .bank = bank, |
| 1731 | .rank = slotrank, |
| 1732 | }, |
| 1733 | }, |
| 1734 | /* DRAM command NOP */ |
| 1735 | [1] = { |
| 1736 | .sp_cmd_ctrl = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1737 | .command = IOSAV_NOP, |
| 1738 | .ranksel_ap = 1, |
| 1739 | }, |
| 1740 | .subseq_ctrl = { |
| 1741 | .cmd_executions = 1, |
| 1742 | .cmd_delay_gap = 3, |
| 1743 | .post_ssq_wait = ctrl->CWL + ctrl->tWLO, |
| 1744 | .data_direction = SSQ_WR, |
| 1745 | }, |
| 1746 | .sp_cmd_addr = { |
| 1747 | .address = 8, |
| 1748 | .rowbits = 0, |
| 1749 | .bank = 0, |
| 1750 | .rank = slotrank, |
| 1751 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1752 | }, |
| 1753 | /* DRAM command NOP */ |
Angel Pons | 59996e0 | 2020-11-14 16:34:35 +0100 | [diff] [blame] | 1754 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1755 | .sp_cmd_ctrl = { |
| 1756 | .command = IOSAV_NOP_ALT, |
| 1757 | .ranksel_ap = 1, |
| 1758 | }, |
| 1759 | .subseq_ctrl = { |
| 1760 | .cmd_executions = 1, |
| 1761 | .cmd_delay_gap = 3, |
| 1762 | .post_ssq_wait = ctrl->CAS + 38, |
| 1763 | .data_direction = SSQ_RD, |
| 1764 | }, |
| 1765 | .sp_cmd_addr = { |
| 1766 | .address = 4, |
| 1767 | .rowbits = 0, |
| 1768 | .bank = 0, |
| 1769 | .rank = slotrank, |
| 1770 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1771 | }, |
Angel Pons | 59996e0 | 2020-11-14 16:34:35 +0100 | [diff] [blame] | 1772 | /* DRAM command MRS: disable DQs on this slotrank */ |
| 1773 | [3] = { |
| 1774 | .sp_cmd_ctrl = { |
| 1775 | .command = IOSAV_MRS, |
| 1776 | .ranksel_ap = 1, |
| 1777 | }, |
| 1778 | .subseq_ctrl = { |
| 1779 | .cmd_executions = 1, |
| 1780 | .cmd_delay_gap = 3, |
| 1781 | .post_ssq_wait = ctrl->tMOD, |
| 1782 | .data_direction = SSQ_NA, |
| 1783 | }, |
| 1784 | .sp_cmd_addr = { |
| 1785 | .address = mr1reg | 1 << 12, |
| 1786 | .rowbits = 6, |
| 1787 | .bank = bank, |
| 1788 | .rank = slotrank, |
| 1789 | }, |
| 1790 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1791 | }; |
| 1792 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1793 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1794 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1795 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1796 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1797 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1798 | } |
| 1799 | |
| 1800 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1801 | { |
| 1802 | int timB; |
| 1803 | int statistics[NUM_LANES][128]; |
| 1804 | int lane; |
| 1805 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1806 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1807 | |
| 1808 | for (timB = 0; timB < 128; timB++) { |
| 1809 | FOR_ALL_LANES { |
| 1810 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1811 | } |
| 1812 | program_timings(ctrl, channel); |
| 1813 | |
| 1814 | test_timB(ctrl, channel, slotrank); |
| 1815 | |
| 1816 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1817 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 1818 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 1819 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1820 | } |
| 1821 | } |
| 1822 | FOR_ALL_LANES { |
| 1823 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1824 | /* |
| 1825 | * timC is a direct function of timB's 6 LSBs. Some tests increments the value |
| 1826 | * of timB by a small value, which might cause the 6-bit value to overflow if |
| 1827 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 1828 | * to overflow, to make sure it won't overflow while running tests and bricks |
| 1829 | * the system due to a non matching timC. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1830 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1831 | * TODO: find out why some tests (edge write discovery) increment timB. |
| 1832 | */ |
| 1833 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1834 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1835 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1836 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1837 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1838 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1839 | if (rn.all) { |
| 1840 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1841 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1842 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1843 | return MAKE_ERR; |
| 1844 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1845 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1846 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1847 | } |
| 1848 | return 0; |
| 1849 | } |
| 1850 | |
| 1851 | static int get_timB_high_adjust(u64 val) |
| 1852 | { |
| 1853 | int i; |
| 1854 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1855 | /* DQS is good enough */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1856 | if (val == 0xffffffffffffffffLL) |
| 1857 | return 0; |
| 1858 | |
| 1859 | if (val >= 0xf000000000000000LL) { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1860 | /* DQS is late, needs negative adjustment */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1861 | for (i = 0; i < 8; i++) |
| 1862 | if (val << (8 * (7 - i) + 4)) |
| 1863 | return -i; |
| 1864 | } else { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1865 | /* DQS is early, needs positive adjustment */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1866 | for (i = 0; i < 8; i++) |
| 1867 | if (val >> (8 * (7 - i) + 4)) |
| 1868 | return i; |
| 1869 | } |
| 1870 | return 8; |
| 1871 | } |
| 1872 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 1873 | static void train_write_flyby(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1874 | { |
| 1875 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1876 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1877 | FOR_ALL_POPULATED_CHANNELS { |
| 1878 | fill_pattern1(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1879 | } |
| 1880 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1881 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 1882 | /* Reset read and write WDB pointers */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1883 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1884 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1885 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1886 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 1887 | iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1888 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1889 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1890 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1891 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1892 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1893 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1894 | const struct iosav_ssq rd_sequence[] = { |
| 1895 | /* DRAM command PREA */ |
| 1896 | [0] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1897 | .sp_cmd_ctrl = { |
| 1898 | .command = IOSAV_PRE, |
| 1899 | .ranksel_ap = 1, |
| 1900 | }, |
| 1901 | .subseq_ctrl = { |
| 1902 | .cmd_executions = 1, |
| 1903 | .cmd_delay_gap = 3, |
| 1904 | .post_ssq_wait = ctrl->tRP, |
| 1905 | .data_direction = SSQ_NA, |
| 1906 | }, |
| 1907 | .sp_cmd_addr = { |
| 1908 | .address = 1024, |
| 1909 | .rowbits = 6, |
| 1910 | .bank = 0, |
| 1911 | .rank = slotrank, |
| 1912 | }, |
| 1913 | .addr_update = { |
| 1914 | .addr_wrap = 18, |
| 1915 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1916 | }, |
| 1917 | /* DRAM command ACT */ |
| 1918 | [1] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1919 | .sp_cmd_ctrl = { |
| 1920 | .command = IOSAV_ACT, |
| 1921 | .ranksel_ap = 1, |
| 1922 | }, |
| 1923 | .subseq_ctrl = { |
| 1924 | .cmd_executions = 1, |
| 1925 | .cmd_delay_gap = 3, |
| 1926 | .post_ssq_wait = ctrl->tRCD, |
| 1927 | .data_direction = SSQ_NA, |
| 1928 | }, |
| 1929 | .sp_cmd_addr = { |
| 1930 | .address = 0, |
| 1931 | .rowbits = 6, |
| 1932 | .bank = 0, |
| 1933 | .rank = slotrank, |
| 1934 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1935 | }, |
| 1936 | /* DRAM command RD */ |
| 1937 | [2] = { |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1938 | .sp_cmd_ctrl = { |
| 1939 | .command = IOSAV_RD, |
| 1940 | .ranksel_ap = 3, |
| 1941 | }, |
| 1942 | .subseq_ctrl = { |
| 1943 | .cmd_executions = 1, |
| 1944 | .cmd_delay_gap = 3, |
| 1945 | .post_ssq_wait = ctrl->tRP + |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1946 | ctrl->timings[channel][slotrank].roundtrip_latency + |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1947 | ctrl->timings[channel][slotrank].io_latency, |
| 1948 | .data_direction = SSQ_RD, |
| 1949 | }, |
| 1950 | .sp_cmd_addr = { |
| 1951 | .address = 8, |
| 1952 | .rowbits = 6, |
| 1953 | .bank = 0, |
| 1954 | .rank = slotrank, |
| 1955 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 1956 | }, |
| 1957 | }; |
| 1958 | iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1959 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1960 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1961 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1962 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1963 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1964 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1965 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 1966 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1967 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1968 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 1969 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 1970 | get_timB_high_adjust(res) * 64; |
| 1971 | |
| 1972 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1973 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 1974 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1975 | } |
| 1976 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1977 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1978 | } |
| 1979 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1980 | static void disable_refresh_machine(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1981 | { |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1982 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1983 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1984 | FOR_ALL_POPULATED_CHANNELS { |
| 1985 | /* choose an existing rank */ |
| 1986 | const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1987 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1988 | iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1989 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1990 | /* Execute command queue */ |
| 1991 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1992 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1993 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1994 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 1995 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
| 1996 | } |
| 1997 | |
| 1998 | /* Refresh disable */ |
| 1999 | MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); |
| 2000 | |
| 2001 | FOR_ALL_POPULATED_CHANNELS { |
| 2002 | /* Execute the same command queue */ |
| 2003 | iosav_run_once(channel); |
| 2004 | |
| 2005 | wait_for_iosav(channel); |
| 2006 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2007 | } |
| 2008 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2009 | /* |
| 2010 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2011 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2012 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 2013 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 2014 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 2015 | * CLK/ADDR/CMD signals have the same routing delay. |
| 2016 | * |
| 2017 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 2018 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 2019 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2020 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2021 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2022 | { |
| 2023 | int channel, slotrank, lane; |
| 2024 | int err; |
| 2025 | |
| 2026 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2027 | MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2028 | |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 2029 | disable_refresh_machine(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2030 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2031 | /* Enable write leveling on all ranks |
| 2032 | Disable all DQ outputs |
| 2033 | Only NOP is allowed in this mode */ |
| 2034 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 2035 | write_mrreg(ctrl, channel, slotrank, 1, |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2036 | make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2037 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2038 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2039 | |
| 2040 | toggle_io_reset(); |
| 2041 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2042 | /* Set any valid value for timB, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2043 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2044 | err = discover_timB(ctrl, channel, slotrank); |
| 2045 | if (err) |
| 2046 | return err; |
| 2047 | } |
| 2048 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2049 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2050 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2051 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2052 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2053 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2054 | |
| 2055 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2056 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2057 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2058 | /* Refresh enable */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2059 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2060 | |
| 2061 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2062 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2063 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 2064 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2065 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2066 | iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2067 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2068 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2069 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2070 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2071 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2072 | } |
| 2073 | |
| 2074 | toggle_io_reset(); |
| 2075 | |
| 2076 | printram("CPE\n"); |
| 2077 | precharge(ctrl); |
| 2078 | printram("CPF\n"); |
| 2079 | |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 2080 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | cf5dd49 | 2020-11-14 01:12:24 +0100 | [diff] [blame] | 2081 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2082 | } |
| 2083 | |
| 2084 | FOR_ALL_POPULATED_CHANNELS { |
| 2085 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2086 | } |
| 2087 | |
| 2088 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 011661c | 2020-11-15 18:21:35 +0100 | [diff] [blame] | 2089 | err = tx_dq_write_leveling(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2090 | if (err) |
| 2091 | return err; |
| 2092 | } |
| 2093 | |
| 2094 | FOR_ALL_POPULATED_CHANNELS |
| 2095 | program_timings(ctrl, channel); |
| 2096 | |
| 2097 | /* measure and adjust timB timings */ |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2098 | train_write_flyby(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2099 | |
| 2100 | FOR_ALL_POPULATED_CHANNELS |
| 2101 | program_timings(ctrl, channel); |
| 2102 | |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 2103 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | cf5dd49 | 2020-11-14 01:12:24 +0100 | [diff] [blame] | 2104 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2105 | } |
| 2106 | return 0; |
| 2107 | } |
| 2108 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2109 | static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2110 | { |
| 2111 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2112 | int timC_delta; |
| 2113 | int lanes_ok = 0; |
| 2114 | int ctr = 0; |
| 2115 | int lane; |
| 2116 | |
| 2117 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2118 | FOR_ALL_LANES { |
| 2119 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2120 | saved_rt.lanes[lane].timC + timC_delta; |
| 2121 | } |
| 2122 | program_timings(ctrl, channel); |
| 2123 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2124 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2125 | } |
| 2126 | |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 2127 | /* Reset read WDB pointer */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2128 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2129 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2130 | wait_for_iosav(channel); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2131 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2132 | iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2133 | |
| 2134 | /* Program LFSR for the RD/WR subsequences */ |
| 2135 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
| 2136 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2137 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2138 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2139 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2140 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2141 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2142 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2143 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2144 | |
| 2145 | if (r32 == 0) |
| 2146 | lanes_ok |= 1 << lane; |
| 2147 | } |
| 2148 | ctr++; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2149 | if (lanes_ok == ((1 << ctrl->lanes) - 1)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2150 | break; |
| 2151 | } |
| 2152 | |
| 2153 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2154 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2155 | return lanes_ok != ((1 << ctrl->lanes) - 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2156 | } |
| 2157 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2158 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2159 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2160 | unsigned int i, j; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2161 | unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; |
| 2162 | unsigned int step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2163 | |
| 2164 | if (patno) { |
| 2165 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2166 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2167 | for (i = 0; i < 32; i++) { |
| 2168 | for (j = 0; j < 16; j++) { |
| 2169 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2170 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2171 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2172 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2173 | |
| 2174 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2175 | } |
| 2176 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2177 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2178 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 2179 | for (j = 0; j < 16; j++) { |
| 2180 | const u32 val = pattern[i][j]; |
| 2181 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 2182 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2183 | } |
| 2184 | sfence(); |
| 2185 | } |
Angel Pons | 765d465 | 2020-11-11 14:44:35 +0100 | [diff] [blame] | 2186 | |
| 2187 | program_wdb_pattern_length(channel, 256); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2188 | } |
| 2189 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2190 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2191 | { |
Angel Pons | 7d11513 | 2020-11-14 01:44:44 +0100 | [diff] [blame] | 2192 | disable_refresh_machine(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2193 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2194 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2195 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2196 | |
| 2197 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2198 | dram_mrscommands(ctrl); |
| 2199 | |
| 2200 | toggle_io_reset(); |
| 2201 | } |
| 2202 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2203 | #define CT_MIN_PI -127 |
| 2204 | #define CT_MAX_PI 128 |
| 2205 | #define CT_PI_LENGTH (CT_MAX_PI - CT_MIN_PI + 1) |
| 2206 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2207 | #define MIN_C320C_LEN 13 |
| 2208 | |
| 2209 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2210 | { |
| 2211 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2212 | int slotrank; |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2213 | int command_pi; |
| 2214 | int stat[NUM_SLOTRANKS][CT_PI_LENGTH]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2215 | int delta = 0; |
| 2216 | |
| 2217 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2218 | |
| 2219 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2220 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2221 | } |
| 2222 | |
| 2223 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2224 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 2225 | const union tc_rap_reg tc_rap = { |
| 2226 | .tRRD = ctrl->tRRD, |
| 2227 | .tRTP = ctrl->tRTP, |
| 2228 | .tCKE = ctrl->tCKE, |
| 2229 | .tWTR = ctrl->tWTR, |
| 2230 | .tFAW = ctrl->tFAW, |
| 2231 | .tWR = ctrl->tWR, |
| 2232 | .tCMD = ctrl->cmd_stretch[channel], |
| 2233 | }; |
| 2234 | MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2235 | |
| 2236 | if (ctrl->cmd_stretch[channel] == 2) |
| 2237 | delta = 2; |
| 2238 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2239 | delta = 4; |
| 2240 | |
| 2241 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2242 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2243 | } |
| 2244 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2245 | for (command_pi = CT_MIN_PI; command_pi < CT_MAX_PI; command_pi++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2246 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2247 | ctrl->timings[channel][slotrank].pi_coding = command_pi; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2248 | } |
| 2249 | program_timings(ctrl, channel); |
| 2250 | reprogram_320c(ctrl); |
| 2251 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2252 | stat[slotrank][command_pi - CT_MIN_PI] = |
| 2253 | test_command_training(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2254 | } |
| 2255 | } |
| 2256 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2257 | struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2258 | |
Angel Pons | bf13ef0 | 2020-11-11 18:40:06 +0100 | [diff] [blame] | 2259 | ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2260 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2261 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2262 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2263 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2264 | FOR_ALL_POPULATED_RANKS { |
| 2265 | ctrl->timings[channel][slotrank] = |
| 2266 | saved_timings[channel][slotrank]; |
| 2267 | } |
| 2268 | return MAKE_ERR; |
| 2269 | } |
| 2270 | } |
| 2271 | |
| 2272 | return 0; |
| 2273 | } |
| 2274 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2275 | /* |
| 2276 | * Adjust CMD phase shift and try multiple command rates. |
| 2277 | * A command rate of 2T doubles the time needed for address and command decode. |
| 2278 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2279 | int command_training(ramctr_timing *ctrl) |
| 2280 | { |
| 2281 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2282 | |
| 2283 | FOR_ALL_POPULATED_CHANNELS { |
| 2284 | fill_pattern5(ctrl, channel, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2285 | } |
| 2286 | |
| 2287 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2288 | int cmdrate, err; |
| 2289 | |
| 2290 | /* |
| 2291 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2292 | * Issue: |
| 2293 | * While c320c discovery seems to succeed raminit will fail in write training. |
| 2294 | * |
| 2295 | * Workaround: |
| 2296 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 2297 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2298 | * |
| 2299 | * Single DIMM per channel: |
| 2300 | * Try command rate 1T and 2T |
| 2301 | */ |
| 2302 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2303 | if (ctrl->tCMD) |
| 2304 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2305 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2306 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2307 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2308 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2309 | |
| 2310 | if (!err) |
| 2311 | break; |
| 2312 | } |
| 2313 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2314 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2315 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2316 | return err; |
| 2317 | } |
| 2318 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2319 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2320 | } |
| 2321 | |
| 2322 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 2323 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2324 | |
| 2325 | reprogram_320c(ctrl); |
| 2326 | return 0; |
| 2327 | } |
| 2328 | |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2329 | static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2330 | { |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2331 | int dqs_pi; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2332 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2333 | int lane; |
| 2334 | |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2335 | for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2336 | FOR_ALL_LANES { |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2337 | ctrl->timings[channel][slotrank].lanes[lane].rising = dqs_pi; |
| 2338 | ctrl->timings[channel][slotrank].lanes[lane].falling = dqs_pi; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2339 | } |
| 2340 | program_timings(ctrl, channel); |
| 2341 | |
| 2342 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2343 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2344 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2345 | } |
| 2346 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2347 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2348 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2349 | iosav_write_read_mpr_sequence( |
| 2350 | channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2351 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2352 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2353 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2354 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2355 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2356 | |
| 2357 | FOR_ALL_LANES { |
Angel Pons | 96a06dd | 2020-11-14 00:33:18 +0100 | [diff] [blame] | 2358 | stats[lane][dqs_pi] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2359 | } |
| 2360 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2361 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2362 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2363 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2364 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2365 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2366 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2367 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, |
| 2368 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2369 | return MAKE_ERR; |
| 2370 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2371 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2372 | } |
| 2373 | return 0; |
| 2374 | } |
| 2375 | |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2376 | static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) |
| 2377 | { |
| 2378 | int slotrank, lane; |
| 2379 | |
| 2380 | fill_pattern0(ctrl, channel, 0, 0); |
| 2381 | FOR_ALL_LANES { |
| 2382 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
| 2383 | } |
| 2384 | |
| 2385 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2386 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 2387 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
| 2388 | } |
| 2389 | |
| 2390 | program_timings(ctrl, channel); |
| 2391 | |
| 2392 | FOR_ALL_POPULATED_RANKS { |
| 2393 | wait_for_iosav(channel); |
| 2394 | |
| 2395 | iosav_write_read_mpr_sequence( |
| 2396 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
| 2397 | |
| 2398 | /* Execute command queue */ |
| 2399 | iosav_run_once(channel); |
| 2400 | |
| 2401 | wait_for_iosav(channel); |
| 2402 | } |
| 2403 | |
| 2404 | /* XXX: check any measured value ? */ |
| 2405 | |
| 2406 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2407 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 2408 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
| 2409 | } |
| 2410 | |
| 2411 | program_timings(ctrl, channel); |
| 2412 | |
| 2413 | FOR_ALL_POPULATED_RANKS { |
| 2414 | wait_for_iosav(channel); |
| 2415 | |
| 2416 | iosav_write_read_mpr_sequence( |
| 2417 | channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); |
| 2418 | |
| 2419 | /* Execute command queue */ |
| 2420 | iosav_run_once(channel); |
| 2421 | |
| 2422 | wait_for_iosav(channel); |
| 2423 | } |
| 2424 | |
| 2425 | /* XXX: check any measured value ? */ |
| 2426 | |
| 2427 | FOR_ALL_LANES { |
| 2428 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
| 2429 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
| 2430 | } |
| 2431 | } |
| 2432 | |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2433 | int read_mpr_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2434 | { |
| 2435 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2436 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2437 | int channel, slotrank, lane; |
| 2438 | int err; |
| 2439 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2440 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2441 | |
| 2442 | toggle_io_reset(); |
| 2443 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2444 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2445 | FOR_ALL_LANES { |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2446 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2447 | } |
| 2448 | |
Angel Pons | 60971dc | 2020-11-14 00:49:38 +0100 | [diff] [blame] | 2449 | find_predefined_pattern(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2450 | |
| 2451 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2452 | } |
| 2453 | |
Angel Pons | 0c3936e | 2020-03-22 12:49:27 +0100 | [diff] [blame] | 2454 | /* |
| 2455 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2456 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2457 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2458 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2459 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2460 | |
| 2461 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2462 | err = find_read_mpr_margin(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2463 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2464 | if (err) |
| 2465 | return err; |
| 2466 | } |
| 2467 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2468 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2469 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2470 | |
| 2471 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 2472 | err = find_read_mpr_margin(ctrl, channel, slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2473 | rising_edges[channel][slotrank]); |
| 2474 | if (err) |
| 2475 | return err; |
| 2476 | } |
| 2477 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2478 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2479 | |
| 2480 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2481 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2482 | falling_edges[channel][slotrank][lane]; |
| 2483 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2484 | rising_edges[channel][slotrank][lane]; |
| 2485 | } |
| 2486 | |
| 2487 | FOR_ALL_POPULATED_CHANNELS { |
| 2488 | program_timings(ctrl, channel); |
| 2489 | } |
| 2490 | |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 2491 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2492 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2493 | } |
| 2494 | return 0; |
| 2495 | } |
| 2496 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2497 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2498 | { |
| 2499 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2500 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
| 2501 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2502 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2503 | int lane, i; |
| 2504 | int lower[NUM_LANES]; |
| 2505 | int upper[NUM_LANES]; |
| 2506 | int pat; |
| 2507 | |
| 2508 | FOR_ALL_LANES { |
| 2509 | lower[lane] = 0; |
| 2510 | upper[lane] = MAX_EDGE_TIMING; |
| 2511 | } |
| 2512 | |
| 2513 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2514 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2515 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
| 2516 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2517 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2518 | fill_pattern5(ctrl, channel, pat); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2519 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2520 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2521 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2522 | FOR_ALL_LANES { |
| 2523 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2524 | rising = edge; |
| 2525 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2526 | falling = edge; |
| 2527 | } |
| 2528 | program_timings(ctrl, channel); |
| 2529 | |
| 2530 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2531 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2532 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2533 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2534 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2535 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2536 | iosav_write_data_write_sequence(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2537 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2538 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2539 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2540 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2541 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2542 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2543 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2544 | } |
| 2545 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2546 | /* FIXME: This register only exists on Ivy Bridge */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2547 | raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2548 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2549 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2550 | FOR_ALL_LANES { |
| 2551 | struct run rn; |
| 2552 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2553 | stats[edge] = !!(raw_stats[edge] & (1 << lane)); |
| 2554 | |
| 2555 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 2556 | |
| 2557 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " |
| 2558 | "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, |
| 2559 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2560 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2561 | |
| 2562 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2563 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2564 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2565 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2566 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2567 | printk(BIOS_EMERG, "edge write discovery failed: " |
| 2568 | "%d, %d, %d\n", channel, slotrank, lane); |
| 2569 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2570 | return MAKE_ERR; |
| 2571 | } |
| 2572 | } |
| 2573 | } |
| 2574 | } |
| 2575 | |
Angel Pons | a93f46e | 2020-11-17 16:54:01 +0100 | [diff] [blame] | 2576 | /* Restore nominal Vref after training */ |
| 2577 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2578 | printram("CPA\n"); |
| 2579 | return 0; |
| 2580 | } |
| 2581 | |
| 2582 | int discover_edges_write(ramctr_timing *ctrl) |
| 2583 | { |
| 2584 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2585 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2586 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2587 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2588 | /* |
| 2589 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2590 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2591 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2592 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2593 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2594 | |
| 2595 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2596 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2597 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2598 | if (err) |
| 2599 | return err; |
| 2600 | } |
| 2601 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2602 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2603 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2604 | |
| 2605 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2606 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2607 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2608 | if (err) |
| 2609 | return err; |
| 2610 | } |
| 2611 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2612 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2613 | |
| 2614 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2615 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2616 | falling_edges[channel][slotrank][lane]; |
| 2617 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2618 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2619 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2620 | } |
| 2621 | |
| 2622 | FOR_ALL_POPULATED_CHANNELS |
| 2623 | program_timings(ctrl, channel); |
| 2624 | |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 2625 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2626 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2627 | } |
| 2628 | return 0; |
| 2629 | } |
| 2630 | |
| 2631 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2632 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2633 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2634 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2635 | iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2636 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2637 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2638 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2639 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2640 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2641 | } |
| 2642 | |
| 2643 | int discover_timC_write(ramctr_timing *ctrl) |
| 2644 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2645 | const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2646 | int i, pat; |
| 2647 | |
| 2648 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2649 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2650 | int channel, slotrank, lane; |
| 2651 | |
| 2652 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2653 | lower[channel][slotrank][lane] = 0; |
| 2654 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2655 | } |
| 2656 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2657 | /* |
| 2658 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2659 | * FIXME: This must only be done on Ivy Bridge. |
| 2660 | */ |
| 2661 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2662 | printram("discover timC write:\n"); |
| 2663 | |
| 2664 | for (i = 0; i < 3; i++) |
| 2665 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2666 | |
| 2667 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
| 2668 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), |
| 2669 | ~0x3f000000, rege3c_b24[i] << 24); |
| 2670 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2671 | udelay(2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2672 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2673 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2674 | FOR_ALL_POPULATED_RANKS { |
| 2675 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2676 | u32 raw_stats[MAX_TIMC + 1]; |
| 2677 | int stats[MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2678 | |
| 2679 | /* Make sure rn.start < rn.end */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2680 | stats[MAX_TIMC] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2681 | |
| 2682 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2683 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2684 | for (timC = 0; timC < MAX_TIMC; timC++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2685 | FOR_ALL_LANES { |
| 2686 | ctrl->timings[channel][slotrank] |
| 2687 | .lanes[lane].timC = timC; |
| 2688 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2689 | program_timings(ctrl, channel); |
| 2690 | |
| 2691 | test_timC_write (ctrl, channel, slotrank); |
| 2692 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2693 | /* FIXME: Another IVB-only register! */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2694 | raw_stats[timC] = MCHBAR32( |
| 2695 | IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2696 | } |
| 2697 | FOR_ALL_LANES { |
| 2698 | struct run rn; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2699 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2700 | stats[timC] = !!(raw_stats[timC] |
| 2701 | & (1 << lane)); |
| 2702 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2703 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2704 | rn = get_longest_zero_run(stats, MAX_TIMC + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2705 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2706 | printk(BIOS_EMERG, |
| 2707 | "timC write discovery failed: " |
| 2708 | "%d, %d, %d\n", channel, |
| 2709 | slotrank, lane); |
| 2710 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2711 | return MAKE_ERR; |
| 2712 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2713 | printram("timC: %d, %d, %d: " |
| 2714 | "0x%02x-0x%02x-0x%02x, " |
| 2715 | "0x%02x-0x%02x\n", channel, slotrank, |
| 2716 | i, rn.start, rn.middle, rn.end, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2717 | rn.start + ctrl->timC_offset[i], |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2718 | rn.end - ctrl->timC_offset[i]); |
| 2719 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2720 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2721 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2722 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2723 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2724 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2725 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2726 | upper[channel][slotrank][lane]); |
| 2727 | |
| 2728 | } |
| 2729 | } |
| 2730 | } |
| 2731 | } |
| 2732 | |
| 2733 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2734 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2735 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2736 | udelay(2); |
| 2737 | } |
| 2738 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2739 | /* |
| 2740 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2741 | * FIXME: This must only be done on Ivy Bridge. |
| 2742 | */ |
| 2743 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2744 | |
| 2745 | printram("CPB\n"); |
| 2746 | |
| 2747 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2748 | printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2749 | (lower[channel][slotrank][lane] + |
| 2750 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2751 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2752 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2753 | (lower[channel][slotrank][lane] + |
| 2754 | upper[channel][slotrank][lane]) / 2; |
| 2755 | } |
| 2756 | FOR_ALL_POPULATED_CHANNELS { |
| 2757 | program_timings(ctrl, channel); |
| 2758 | } |
| 2759 | return 0; |
| 2760 | } |
| 2761 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2762 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2763 | { |
| 2764 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2765 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2766 | |
| 2767 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2768 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2769 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2770 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2771 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2772 | printram("normalize %d, %d, %d: mat %d\n", |
| 2773 | channel, slotrank, lane, mat); |
| 2774 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2775 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2776 | printram("normalize %d, %d, %d: delta %d\n", |
| 2777 | channel, slotrank, lane, delta); |
| 2778 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2779 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2780 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2781 | } |
| 2782 | |
| 2783 | FOR_ALL_POPULATED_CHANNELS { |
| 2784 | program_timings(ctrl, channel); |
| 2785 | } |
| 2786 | } |
| 2787 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2788 | int channel_test(ramctr_timing *ctrl) |
| 2789 | { |
| 2790 | int channel, slotrank, lane; |
| 2791 | |
| 2792 | slotrank = 0; |
| 2793 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2794 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2795 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2796 | return MAKE_ERR; |
| 2797 | } |
| 2798 | FOR_ALL_POPULATED_CHANNELS { |
| 2799 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2800 | } |
| 2801 | |
| 2802 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 2803 | FOR_ALL_CHANNELS |
| 2804 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 2805 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2806 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 2807 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2808 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2809 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2810 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 2811 | iosav_write_memory_test_sequence(ctrl, channel, slotrank); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2812 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2813 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2814 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2815 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2816 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2817 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2818 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2819 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 2820 | channel, slotrank, lane); |
| 2821 | return MAKE_ERR; |
| 2822 | } |
| 2823 | } |
| 2824 | return 0; |
| 2825 | } |
| 2826 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2827 | void channel_scrub(ramctr_timing *ctrl) |
| 2828 | { |
| 2829 | int channel, slotrank, row, rowsize; |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2830 | u8 bank; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2831 | |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2832 | FOR_ALL_POPULATED_CHANNELS { |
| 2833 | wait_for_iosav(channel); |
| 2834 | fill_pattern0(ctrl, channel, 0, 0); |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2835 | } |
| 2836 | |
| 2837 | /* |
| 2838 | * During runtime the "scrubber" will periodically scan through the memory in the |
| 2839 | * physical address space, to identify and fix CRC errors. |
| 2840 | * The following loops writes to every DRAM address, setting the ECC bits to the |
| 2841 | * correct value. A read from this location will no longer return a CRC error, |
| 2842 | * except when a bit has toggled due to external events. |
Angel Pons | 3b9d3e9 | 2020-11-11 19:10:39 +0100 | [diff] [blame] | 2843 | * The same could be achieved by writing to the physical memory map, but it's |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2844 | * much more difficult due to SMM remapping, ME stolen memory, GFX stolen memory, |
| 2845 | * and firmware running in x86_32. |
| 2846 | */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2847 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2848 | rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2849 | for (bank = 0; bank < 8; bank++) { |
| 2850 | for (row = 0; row < rowsize; row += 16) { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2851 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2852 | u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); |
| 2853 | const struct iosav_ssq sequence[] = { |
| 2854 | /* |
| 2855 | * DRAM command ACT |
| 2856 | * Opens the row for writing. |
| 2857 | */ |
| 2858 | [0] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2859 | .sp_cmd_ctrl = { |
| 2860 | .command = IOSAV_ACT, |
| 2861 | .ranksel_ap = 1, |
| 2862 | }, |
| 2863 | .subseq_ctrl = { |
| 2864 | .cmd_executions = 1, |
| 2865 | .cmd_delay_gap = gap, |
| 2866 | .post_ssq_wait = ctrl->tRCD, |
| 2867 | .data_direction = SSQ_NA, |
| 2868 | }, |
| 2869 | .sp_cmd_addr = { |
| 2870 | .address = row, |
| 2871 | .rowbits = 6, |
| 2872 | .bank = bank, |
| 2873 | .rank = slotrank, |
| 2874 | }, |
| 2875 | .addr_update = { |
| 2876 | .inc_addr_1 = 1, |
| 2877 | .addr_wrap = 18, |
| 2878 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2879 | }, |
| 2880 | /* |
| 2881 | * DRAM command WR |
| 2882 | * Writes (128 + 1) * 8 (burst length) * 8 (bus width) |
| 2883 | * bytes. |
| 2884 | */ |
| 2885 | [1] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2886 | .sp_cmd_ctrl = { |
| 2887 | .command = IOSAV_WR, |
| 2888 | .ranksel_ap = 1, |
| 2889 | }, |
| 2890 | .subseq_ctrl = { |
| 2891 | .cmd_executions = 129, |
| 2892 | .cmd_delay_gap = 4, |
| 2893 | .post_ssq_wait = ctrl->tWTR + |
| 2894 | ctrl->CWL + 8, |
| 2895 | .data_direction = SSQ_WR, |
| 2896 | }, |
| 2897 | .sp_cmd_addr = { |
| 2898 | .address = row, |
| 2899 | .rowbits = 0, |
| 2900 | .bank = bank, |
| 2901 | .rank = slotrank, |
| 2902 | }, |
| 2903 | .addr_update = { |
| 2904 | .inc_addr_8 = 1, |
| 2905 | .addr_wrap = 9, |
| 2906 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2907 | }, |
| 2908 | /* |
| 2909 | * DRAM command PRE |
| 2910 | * Closes the row. |
| 2911 | */ |
| 2912 | [2] = { |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2913 | .sp_cmd_ctrl = { |
| 2914 | .command = IOSAV_PRE, |
| 2915 | .ranksel_ap = 1, |
| 2916 | }, |
| 2917 | .subseq_ctrl = { |
| 2918 | .cmd_executions = 1, |
| 2919 | .cmd_delay_gap = 4, |
| 2920 | .post_ssq_wait = ctrl->tRP, |
| 2921 | .data_direction = SSQ_NA, |
| 2922 | }, |
| 2923 | .sp_cmd_addr = { |
| 2924 | .address = 0, |
| 2925 | .rowbits = 6, |
| 2926 | .bank = bank, |
| 2927 | .rank = slotrank, |
| 2928 | }, |
| 2929 | .addr_update = { |
Angel Pons | fd9a8b6 | 2020-11-13 13:56:30 +0100 | [diff] [blame] | 2930 | .addr_wrap = 18, |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2931 | }, |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 2932 | }, |
| 2933 | }; |
| 2934 | iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); |
Patrick Rudolph | b5fa9c8 | 2020-05-01 18:35:05 +0200 | [diff] [blame] | 2935 | |
| 2936 | /* Execute command queue */ |
| 2937 | iosav_run_queue(channel, 16, 0); |
| 2938 | |
| 2939 | wait_for_iosav(channel); |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2940 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2941 | } |
| 2942 | } |
| 2943 | } |
| 2944 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2945 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2946 | { |
| 2947 | int channel; |
| 2948 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2949 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2950 | static u32 seeds[NUM_CHANNELS][3] = { |
| 2951 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 2952 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 2953 | }; |
| 2954 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2955 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2956 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 2957 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 2958 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2959 | } |
| 2960 | } |
| 2961 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 2962 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2963 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2964 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2965 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2966 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2967 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2968 | } |
| 2969 | } |
| 2970 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2971 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2972 | { |
| 2973 | int channel; |
| 2974 | |
| 2975 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2976 | /* Always drive command bus */ |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 2977 | MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2978 | } |
| 2979 | |
| 2980 | udelay(1); |
| 2981 | |
| 2982 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2983 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2984 | } |
| 2985 | } |
| 2986 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2987 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2988 | { |
| 2989 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 2990 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2991 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2992 | int min_pi = 10000; |
| 2993 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2994 | |
| 2995 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2996 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 2997 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2998 | } |
| 2999 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 3000 | const u32 tWRDRDD = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3001 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 3002 | const u32 val = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 3 : 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3003 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3004 | dram_odt_stretch(ctrl, channel); |
| 3005 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 3006 | const union tc_rwp_reg tc_rwp = { |
| 3007 | .tRRDR = 0, |
| 3008 | .tRRDD = val, |
| 3009 | .tWWDR = val, |
| 3010 | .tWWDD = val, |
| 3011 | .tRWDRDD = ctrl->ref_card_offset[channel] + 2, |
| 3012 | .tWRDRDD = tWRDRDD, |
| 3013 | .tRWSR = 2, |
| 3014 | .dec_wrd = 1, |
| 3015 | }; |
| 3016 | MCHBAR32(TC_RWP_ch(channel)) = tc_rwp.raw; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3017 | } |
| 3018 | } |
| 3019 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3020 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3021 | { |
| 3022 | int channel; |
| 3023 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3024 | MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel]; |
| 3025 | MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3026 | } |
| 3027 | } |
| 3028 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3029 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 3030 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3031 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3032 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3033 | } |
| 3034 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3035 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3036 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3037 | { |
Angel Pons | b50ca57 | 2020-11-11 19:07:20 +0100 | [diff] [blame] | 3038 | const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3039 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3040 | int channel; |
| 3041 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 3042 | int t3_ns; |
| 3043 | u32 r32; |
| 3044 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3045 | /* FIXME: This register only exists on Ivy Bridge */ |
| 3046 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3047 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 3048 | FOR_ALL_CHANNELS { |
| 3049 | union tc_othp_reg tc_othp = { |
| 3050 | .raw = MCHBAR32(TC_OTHP_ch(channel)), |
| 3051 | }; |
| 3052 | tc_othp.tCPDED = 1; |
| 3053 | MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; |
| 3054 | } |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3055 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3056 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3057 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3058 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3059 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3060 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3061 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3062 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3063 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3064 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3065 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3066 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 3067 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3068 | |
| 3069 | FOR_ALL_CHANNELS { |
| 3070 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3071 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3072 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3073 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3074 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3075 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3076 | case 1: |
| 3077 | case 4: |
| 3078 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3079 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3080 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3081 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3082 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3083 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3084 | break; |
| 3085 | } |
| 3086 | } |
| 3087 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3088 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3089 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3090 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3091 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 3092 | FOR_ALL_CHANNELS { |
| 3093 | union tc_rfp_reg tc_rfp = { |
| 3094 | .raw = MCHBAR32(TC_RFP_ch(channel)), |
| 3095 | }; |
| 3096 | tc_rfp.refresh_2x_control = 1; |
| 3097 | MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; |
| 3098 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3099 | |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3100 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); |
| 3101 | MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3102 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3103 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3104 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3105 | FOR_ALL_POPULATED_CHANNELS |
| 3106 | break; |
| 3107 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3108 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 3109 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3110 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3111 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3112 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3113 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3114 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3115 | t1_ns += 500; |
| 3116 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3117 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3118 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3119 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3120 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3121 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3122 | t3_ns = 500; |
| 3123 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3124 | |
| 3125 | /* The graphics driver will use these watermark values */ |
| 3126 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3127 | MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3128 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 3129 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3130 | } |
| 3131 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3132 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3133 | { |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 3134 | int channel, lane; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3135 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3136 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame^] | 3137 | const union tc_rap_reg tc_rap = { |
| 3138 | .tRRD = ctrl->tRRD, |
| 3139 | .tRTP = ctrl->tRTP, |
| 3140 | .tCKE = ctrl->tCKE, |
| 3141 | .tWTR = ctrl->tWTR, |
| 3142 | .tFAW = ctrl->tFAW, |
| 3143 | .tWR = ctrl->tWR, |
| 3144 | .tCMD = ctrl->cmd_stretch[channel], |
| 3145 | }; |
| 3146 | MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3147 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3148 | |
| 3149 | udelay(1); |
| 3150 | |
| 3151 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3152 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3153 | } |
| 3154 | |
Angel Pons | 50a6fe7 | 2020-11-14 01:18:14 +0100 | [diff] [blame] | 3155 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3156 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3157 | } |
| 3158 | |
| 3159 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3160 | MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3161 | |
| 3162 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3163 | udelay(1); |
Angel Pons | dc5539f | 2020-11-12 12:44:25 +0100 | [diff] [blame] | 3164 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3165 | } |
| 3166 | |
| 3167 | printram("CPE\n"); |
| 3168 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3169 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 3170 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3171 | |
| 3172 | printram("CP5b\n"); |
| 3173 | |
| 3174 | FOR_ALL_POPULATED_CHANNELS { |
| 3175 | program_timings(ctrl, channel); |
| 3176 | } |
| 3177 | |
| 3178 | u32 reg, addr; |
| 3179 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3180 | /* Poll for RCOMP */ |
| 3181 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 3182 | ; |
| 3183 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3184 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3185 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3186 | } while ((reg & 0x14) == 0); |
| 3187 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3188 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3189 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3190 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3191 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3192 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3193 | udelay(500); |
| 3194 | |
| 3195 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3196 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3197 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3198 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3199 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3200 | MCHBAR32(addr) = reg; |
| 3201 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3202 | /* Wait 10ns for ranks to settle */ |
| 3203 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3204 | |
| 3205 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3206 | MCHBAR32(addr) = reg; |
| 3207 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3208 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3209 | write_reset(ctrl); |
| 3210 | } |
| 3211 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3212 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3213 | dram_mrscommands(ctrl); |
| 3214 | |
| 3215 | printram("CP5c\n"); |
| 3216 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3217 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3218 | |
| 3219 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3220 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3221 | udelay(2); |
| 3222 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3223 | } |