Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> |
| 6 | * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <console/usb.h> |
| 20 | #include <string.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <cbmem.h> |
| 23 | #include <arch/cbfs.h> |
| 24 | #include <cbfs.h> |
| 25 | #include <northbridge/intel/sandybridge/chip.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <delay.h> |
| 28 | #include <arch/cpu.h> |
| 29 | #include <cpu/x86/msr.h> |
| 30 | #include "raminit_native.h" |
| 31 | #include "raminit_common.h" |
| 32 | #include "sandybridge.h" |
| 33 | |
| 34 | /* FIXME: no ECC support. */ |
| 35 | /* FIXME: no support for 3-channel chipsets. */ |
| 36 | |
| 37 | /* |
| 38 | * Register description: |
| 39 | * Intel provides a command queue of depth four. |
| 40 | * Every command is configured by using multiple registers. |
| 41 | * On executing the command queue you have to provide the depth used. |
| 42 | * |
| 43 | * Known registers: |
| 44 | * Channel X = [0, 1] |
| 45 | * Command queue index Y = [0, 1, 2, 3] |
| 46 | * |
| 47 | * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register |
| 48 | * Controls the DRAM command signals |
| 49 | * Bit 0: !RAS |
| 50 | * Bit 1: !CAS |
| 51 | * Bit 2: !WE |
| 52 | * |
| 53 | * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register |
| 54 | * Controls the address, bank address and slotrank signals |
| 55 | * Bit 0-15 : Address |
| 56 | * Bit 20-22: Bank Address |
| 57 | * Bit 24-25: slotrank |
| 58 | * |
| 59 | * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register |
| 60 | * Controls the idle time after issuing this DRAM command |
| 61 | * Bit 16-32: number of clock-cylces to idle |
| 62 | * |
| 63 | * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue |
| 64 | * Starts to execute all queued commands |
| 65 | * Bit 0 : start DRAM command execution |
| 66 | * Bit 16-20: (number of queued commands - 1) * 4 |
| 67 | */ |
| 68 | |
| 69 | static void sfence(void) |
| 70 | { |
| 71 | asm volatile ("sfence"); |
| 72 | } |
| 73 | |
| 74 | static void toggle_io_reset(void) { |
| 75 | /* toggle IO reset bit */ |
| 76 | u32 r32 = read32(DEFAULT_MCHBAR + 0x5030); |
| 77 | write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); |
| 78 | udelay(1); |
| 79 | write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); |
| 80 | udelay(1); |
| 81 | } |
| 82 | |
| 83 | static u32 get_XOVER_CLK(u8 rankmap) |
| 84 | { |
| 85 | return rankmap << 24; |
| 86 | } |
| 87 | |
| 88 | static u32 get_XOVER_CMD(u8 rankmap) |
| 89 | { |
| 90 | u32 reg; |
| 91 | |
| 92 | // enable xover cmd |
| 93 | reg = 0x4000; |
| 94 | |
| 95 | // enable xover ctl |
| 96 | if (rankmap & 0x3) |
| 97 | reg |= 0x20000; |
| 98 | |
| 99 | if (rankmap & 0xc) |
| 100 | reg |= 0x4000000; |
| 101 | |
| 102 | return reg; |
| 103 | } |
| 104 | |
| 105 | /* CAS write latency. To be programmed in MR2. |
| 106 | * See DDR3 SPEC for MR2 documentation. */ |
| 107 | u8 get_CWL(u32 tCK) |
| 108 | { |
| 109 | /* Get CWL based on tCK using the following rule: */ |
| 110 | switch (tCK) { |
| 111 | case TCK_1333MHZ: |
| 112 | return 12; |
| 113 | case TCK_1200MHZ: |
| 114 | case TCK_1100MHZ: |
| 115 | return 11; |
| 116 | case TCK_1066MHZ: |
| 117 | case TCK_1000MHZ: |
| 118 | return 10; |
| 119 | case TCK_933MHZ: |
| 120 | case TCK_900MHZ: |
| 121 | return 9; |
| 122 | case TCK_800MHZ: |
| 123 | case TCK_700MHZ: |
| 124 | return 8; |
| 125 | case TCK_666MHZ: |
| 126 | return 7; |
| 127 | case TCK_533MHZ: |
| 128 | return 6; |
| 129 | default: |
| 130 | return 5; |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | void dram_find_common_params(ramctr_timing *ctrl) |
| 135 | { |
| 136 | size_t valid_dimms; |
| 137 | int channel, slot; |
| 138 | dimm_info *dimms = &ctrl->info; |
| 139 | |
| 140 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 141 | valid_dimms = 0; |
| 142 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
| 143 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 144 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 145 | continue; |
| 146 | valid_dimms++; |
| 147 | |
| 148 | /* Find all possible CAS combinations */ |
| 149 | ctrl->cas_supported &= dimm->cas_supported; |
| 150 | |
| 151 | /* Find the smallest common latencies supported by all DIMMs */ |
| 152 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 153 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 154 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
| 155 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 156 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
| 157 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
| 158 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 159 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 160 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 161 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 162 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
| 163 | } |
| 164 | |
| 165 | if (!ctrl->cas_supported) |
| 166 | die("Unsupported DIMM combination. " |
| 167 | "DIMMS do not support common CAS latency"); |
| 168 | if (!valid_dimms) |
| 169 | die("No valid DIMMs found"); |
| 170 | } |
| 171 | |
| 172 | void dram_xover(ramctr_timing * ctrl) |
| 173 | { |
| 174 | u32 reg; |
| 175 | int channel; |
| 176 | |
| 177 | FOR_ALL_CHANNELS { |
| 178 | // enable xover clk |
| 179 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 180 | printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14, |
| 181 | reg); |
| 182 | MCHBAR32(channel * 0x100 + 0xc14) = reg; |
| 183 | |
| 184 | // enable xover ctl & xover cmd |
| 185 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
| 186 | printram("XOVER CMD [%x] = %x\n", 0x100 * channel + 0x320c, |
| 187 | reg); |
| 188 | MCHBAR32(0x100 * channel + 0x320c) = reg; |
| 189 | } |
| 190 | } |
| 191 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 192 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 193 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 194 | struct cpuid_result cpures; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 195 | u32 reg, addr, cpu, stretch; |
| 196 | |
| 197 | stretch = ctrl->ref_card_offset[channel]; |
| 198 | /* ODT stretch: Delay ODT signal by stretch value. |
| 199 | * Useful for multi DIMM setups on the same channel. */ |
| 200 | cpures = cpuid(1); |
| 201 | cpu = cpures.eax; |
| 202 | if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { |
| 203 | if (stretch == 2) |
| 204 | stretch = 3; |
| 205 | addr = 0x400 * channel + 0x401c; |
| 206 | reg = MCHBAR32(addr) & 0xffffc3ff; |
| 207 | reg |= (stretch << 12); |
| 208 | reg |= (stretch << 10); |
| 209 | MCHBAR32(addr) = reg; |
| 210 | printram("OTHP Workaround [%x] = %x\n", addr, reg); |
| 211 | } else { |
| 212 | // OTHP |
| 213 | addr = 0x400 * channel + 0x400c; |
| 214 | reg = MCHBAR32(addr) & 0xfff0ffff; |
| 215 | reg |= (stretch << 16); |
| 216 | reg |= (stretch << 18); |
| 217 | MCHBAR32(addr) = reg; |
| 218 | printram("OTHP [%x] = %x\n", addr, reg); |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | void dram_timing_regs(ramctr_timing *ctrl) |
| 223 | { |
| 224 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 225 | int channel; |
| 226 | |
| 227 | FOR_ALL_CHANNELS { |
| 228 | // DBP |
| 229 | reg = 0; |
| 230 | reg |= ctrl->tRCD; |
| 231 | reg |= (ctrl->tRP << 4); |
| 232 | reg |= (ctrl->CAS << 8); |
| 233 | reg |= (ctrl->CWL << 12); |
| 234 | reg |= (ctrl->tRAS << 16); |
| 235 | printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); |
| 236 | MCHBAR32(0x400 * channel + 0x4000) = reg; |
| 237 | |
| 238 | // RAP |
| 239 | reg = 0; |
| 240 | reg |= ctrl->tRRD; |
| 241 | reg |= (ctrl->tRTP << 4); |
| 242 | reg |= (ctrl->tCKE << 8); |
| 243 | reg |= (ctrl->tWTR << 12); |
| 244 | reg |= (ctrl->tFAW << 16); |
| 245 | reg |= (ctrl->tWR << 24); |
| 246 | reg |= (3 << 30); |
| 247 | printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); |
| 248 | MCHBAR32(0x400 * channel + 0x4004) = reg; |
| 249 | |
| 250 | // OTHP |
| 251 | addr = 0x400 * channel + 0x400c; |
| 252 | reg = 0; |
| 253 | reg |= ctrl->tXPDLL; |
| 254 | reg |= (ctrl->tXP << 5); |
| 255 | reg |= (ctrl->tAONPD << 8); |
| 256 | reg |= 0xa0000; |
| 257 | printram("OTHP [%x] = %x\n", addr, reg); |
| 258 | MCHBAR32(addr) = reg; |
| 259 | |
| 260 | MCHBAR32(0x400 * channel + 0x4014) = 0; |
| 261 | |
| 262 | MCHBAR32(addr) |= 0x00020000; |
| 263 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 264 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 265 | |
| 266 | // REFI |
| 267 | reg = 0; |
| 268 | val32 = ctrl->tREFI; |
| 269 | reg = (reg & ~0xffff) | val32; |
| 270 | val32 = ctrl->tRFC; |
| 271 | reg = (reg & ~0x1ff0000) | (val32 << 16); |
| 272 | val32 = (u32) (ctrl->tREFI * 9) / 1024; |
| 273 | reg = (reg & ~0xfe000000) | (val32 << 25); |
| 274 | printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, |
| 275 | reg); |
| 276 | MCHBAR32(0x400 * channel + 0x4298) = reg; |
| 277 | |
| 278 | MCHBAR32(0x400 * channel + 0x4294) |= 0xff; |
| 279 | |
| 280 | // SRFTP |
| 281 | reg = 0; |
| 282 | val32 = tDLLK; |
| 283 | reg = (reg & ~0xfff) | val32; |
| 284 | val32 = ctrl->tXSOffset; |
| 285 | reg = (reg & ~0xf000) | (val32 << 12); |
| 286 | val32 = tDLLK - ctrl->tXSOffset; |
| 287 | reg = (reg & ~0x3ff0000) | (val32 << 16); |
| 288 | val32 = ctrl->tMOD - 8; |
| 289 | reg = (reg & ~0xf0000000) | (val32 << 28); |
| 290 | printram("SRFTP [%x] = %x\n", 0x400 * channel + 0x42a4, |
| 291 | reg); |
| 292 | MCHBAR32(0x400 * channel + 0x42a4) = reg; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 297 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 298 | int channel; |
| 299 | dimm_info *info = &ctrl->info; |
| 300 | |
| 301 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 302 | dimm_attr *dimmA, *dimmB; |
| 303 | u32 reg = 0; |
| 304 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 305 | if (info->dimm[channel][0].size_mb >= |
| 306 | info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 307 | dimmA = &info->dimm[channel][0]; |
| 308 | dimmB = &info->dimm[channel][1]; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 309 | reg |= 0 << 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 310 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 311 | dimmA = &info->dimm[channel][1]; |
| 312 | dimmB = &info->dimm[channel][0]; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 313 | reg |= 1 << 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 314 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 315 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 316 | if (dimmA && (dimmA->ranks > 0)) { |
| 317 | reg |= dimmA->size_mb / 256; |
| 318 | reg |= (dimmA->ranks - 1) << 17; |
| 319 | reg |= (dimmA->width / 8 - 1) << 19; |
| 320 | } |
| 321 | |
| 322 | if (dimmB && (dimmB->ranks > 0)) { |
| 323 | reg |= (dimmB->size_mb / 256) << 8; |
| 324 | reg |= (dimmB->ranks - 1) << 18; |
| 325 | reg |= (dimmB->width / 8 - 1) << 20; |
| 326 | } |
| 327 | |
| 328 | reg |= 1 << 21; /* rank interleave */ |
| 329 | reg |= 1 << 22; /* enhanced interleave */ |
| 330 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 331 | if ((dimmA && (dimmA->ranks > 0)) |
| 332 | || (dimmB && (dimmB->ranks > 0))) { |
| 333 | ctrl->mad_dimm[channel] = reg; |
| 334 | } else { |
| 335 | ctrl->mad_dimm[channel] = 0; |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | void dram_dimm_set_mapping(ramctr_timing * ctrl) |
| 341 | { |
| 342 | int channel; |
| 343 | FOR_ALL_CHANNELS { |
| 344 | MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel]; |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | void dram_zones(ramctr_timing * ctrl, int training) |
| 349 | { |
| 350 | u32 reg, ch0size, ch1size; |
| 351 | u8 val; |
| 352 | reg = 0; |
| 353 | val = 0; |
| 354 | if (training) { |
| 355 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 356 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 357 | } else { |
| 358 | ch0size = ctrl->channel_size_mb[0]; |
| 359 | ch1size = ctrl->channel_size_mb[1]; |
| 360 | } |
| 361 | |
| 362 | if (ch0size >= ch1size) { |
| 363 | reg = MCHBAR32(0x5014); |
| 364 | val = ch1size / 256; |
| 365 | reg = (reg & ~0xff000000) | val << 24; |
| 366 | reg = (reg & ~0xff0000) | (2 * val) << 16; |
| 367 | MCHBAR32(0x5014) = reg; |
| 368 | MCHBAR32(0x5000) = 0x24; |
| 369 | } else { |
| 370 | reg = MCHBAR32(0x5014); |
| 371 | val = ch0size / 256; |
| 372 | reg = (reg & ~0xff000000) | val << 24; |
| 373 | reg = (reg & ~0xff0000) | (2 * val) << 16; |
| 374 | MCHBAR32(0x5014) = reg; |
| 375 | MCHBAR32(0x5000) = 0x21; |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | #define HOST_BRIDGE PCI_DEVFN(0, 0) |
| 380 | #define DEFAULT_TCK TCK_800MHZ |
| 381 | |
| 382 | unsigned int get_mem_min_tck(void) |
| 383 | { |
| 384 | u32 reg32; |
| 385 | u8 rev; |
| 386 | const struct device *dev; |
| 387 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 388 | |
| 389 | dev = dev_find_slot(0, HOST_BRIDGE); |
| 390 | if (dev) |
| 391 | cfg = dev->chip_info; |
| 392 | |
| 393 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 394 | if (!cfg || cfg->max_mem_clock_mhz == 0) { |
Patrick Rudolph | b794a69 | 2017-08-08 13:13:51 +0200 | [diff] [blame] | 395 | if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) |
| 396 | return TCK_1333MHZ; |
| 397 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 398 | rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); |
| 399 | |
| 400 | if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { |
| 401 | /* read Capabilities A Register DMFC bits */ |
| 402 | reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); |
| 403 | reg32 &= 0x7; |
| 404 | |
| 405 | switch (reg32) { |
| 406 | case 7: return TCK_533MHZ; |
| 407 | case 6: return TCK_666MHZ; |
| 408 | case 5: return TCK_800MHZ; |
| 409 | /* reserved: */ |
| 410 | default: |
| 411 | break; |
| 412 | } |
| 413 | } else { |
| 414 | /* read Capabilities B Register DMFC bits */ |
| 415 | reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); |
| 416 | reg32 = (reg32 >> 4) & 0x7; |
| 417 | |
| 418 | switch (reg32) { |
| 419 | case 7: return TCK_533MHZ; |
| 420 | case 6: return TCK_666MHZ; |
| 421 | case 5: return TCK_800MHZ; |
| 422 | case 4: return TCK_933MHZ; |
| 423 | case 3: return TCK_1066MHZ; |
| 424 | case 2: return TCK_1200MHZ; |
| 425 | case 1: return TCK_1333MHZ; |
| 426 | /* reserved: */ |
| 427 | default: |
| 428 | break; |
| 429 | } |
| 430 | } |
| 431 | return DEFAULT_TCK; |
| 432 | } else { |
| 433 | if (cfg->max_mem_clock_mhz >= 1066) |
| 434 | return TCK_1066MHZ; |
| 435 | else if (cfg->max_mem_clock_mhz >= 933) |
| 436 | return TCK_933MHZ; |
| 437 | else if (cfg->max_mem_clock_mhz >= 800) |
| 438 | return TCK_800MHZ; |
| 439 | else if (cfg->max_mem_clock_mhz >= 666) |
| 440 | return TCK_666MHZ; |
| 441 | else if (cfg->max_mem_clock_mhz >= 533) |
| 442 | return TCK_533MHZ; |
| 443 | else |
| 444 | return TCK_400MHZ; |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 449 | |
| 450 | static unsigned int get_mmio_size(void) |
| 451 | { |
| 452 | const struct device *dev; |
| 453 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 454 | |
| 455 | dev = dev_find_slot(0, HOST_BRIDGE); |
| 456 | if (dev) |
| 457 | cfg = dev->chip_info; |
| 458 | |
| 459 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 460 | if (!cfg || cfg->pci_mmio_size == 0) |
| 461 | return DEFAULT_PCI_MMIO_SIZE; |
| 462 | else |
| 463 | return cfg->pci_mmio_size; |
| 464 | } |
| 465 | |
| 466 | void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) |
| 467 | { |
| 468 | u32 reg, val, reclaim; |
| 469 | u32 tom, gfxstolen, gttsize; |
| 470 | size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase, |
| 471 | tsegbase, mestolenbase; |
| 472 | size_t tsegbasedelta, remapbase, remaplimit; |
| 473 | uint16_t ggc; |
| 474 | |
| 475 | mmiosize = get_mmio_size(); |
| 476 | |
| 477 | ggc = pci_read_config16(NORTHBRIDGE, GGC); |
| 478 | if (!(ggc & 2)) { |
| 479 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
| 480 | gttsize = ((ggc >> 8) & 0x3); |
| 481 | } else { |
| 482 | gfxstolen = 0; |
| 483 | gttsize = 0; |
| 484 | } |
| 485 | |
| 486 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 487 | |
| 488 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 489 | |
| 490 | mestolenbase = tom - me_uma_size; |
| 491 | |
| 492 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, |
| 493 | tom - me_uma_size); |
| 494 | gfxstolenbase = toludbase - gfxstolen; |
| 495 | gttbase = gfxstolenbase - gttsize; |
| 496 | |
| 497 | tsegbase = gttbase - tsegsize; |
| 498 | |
| 499 | // Round tsegbase down to nearest address aligned to tsegsize |
| 500 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 501 | tsegbase &= ~(tsegsize - 1); |
| 502 | |
| 503 | gttbase -= tsegbasedelta; |
| 504 | gfxstolenbase -= tsegbasedelta; |
| 505 | toludbase -= tsegbasedelta; |
| 506 | |
| 507 | // Test if it is possible to reclaim a hole in the RAM addressing |
| 508 | if (tom - me_uma_size > toludbase) { |
| 509 | // Reclaim is possible |
| 510 | reclaim = 1; |
| 511 | remapbase = MAX(4096, tom - me_uma_size); |
| 512 | remaplimit = |
| 513 | remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 514 | touudbase = remaplimit + 1; |
| 515 | } else { |
| 516 | // Reclaim not possible |
| 517 | reclaim = 0; |
| 518 | touudbase = tom - me_uma_size; |
| 519 | } |
| 520 | |
| 521 | // Update memory map in pci-e configuration space |
| 522 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 523 | |
| 524 | // TOM (top of memory) |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 525 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 526 | val = tom & 0xfff; |
| 527 | reg = (reg & ~0xfff00000) | (val << 20); |
| 528 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 529 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 530 | |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 531 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 532 | val = tom & 0xfffff000; |
| 533 | reg = (reg & ~0x000fffff) | (val >> 12); |
| 534 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 535 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 536 | |
| 537 | // TOLUD (top of low used dram) |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 538 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xbc); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 539 | val = toludbase & 0xfff; |
| 540 | reg = (reg & ~0xfff00000) | (val << 20); |
| 541 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 542 | pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 543 | |
| 544 | // TOUUD LSB (top of upper usable dram) |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 545 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 546 | val = touudbase & 0xfff; |
| 547 | reg = (reg & ~0xfff00000) | (val << 20); |
| 548 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 549 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 550 | |
| 551 | // TOUUD MSB |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 552 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xac); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 553 | val = touudbase & 0xfffff000; |
| 554 | reg = (reg & ~0x000fffff) | (val >> 12); |
| 555 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 556 | pci_write_config32(PCI_DEV(0, 0, 0), 0xac, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 557 | |
| 558 | if (reclaim) { |
| 559 | // REMAP BASE |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 560 | pci_write_config32(PCI_DEV(0, 0, 0), 0x90, remapbase << 20); |
| 561 | pci_write_config32(PCI_DEV(0, 0, 0), 0x94, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 562 | |
| 563 | // REMAP LIMIT |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 564 | pci_write_config32(PCI_DEV(0, 0, 0), 0x98, remaplimit << 20); |
| 565 | pci_write_config32(PCI_DEV(0, 0, 0), 0x9c, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 566 | } |
| 567 | // TSEG |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 568 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 569 | val = tsegbase & 0xfff; |
| 570 | reg = (reg & ~0xfff00000) | (val << 20); |
| 571 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 572 | pci_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 573 | |
| 574 | // GFX stolen memory |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 575 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 576 | val = gfxstolenbase & 0xfff; |
| 577 | reg = (reg & ~0xfff00000) | (val << 20); |
| 578 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 579 | pci_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 580 | |
| 581 | // GTT stolen memory |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 582 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 583 | val = gttbase & 0xfff; |
| 584 | reg = (reg & ~0xfff00000) | (val << 20); |
| 585 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 586 | pci_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 587 | |
| 588 | if (me_uma_size) { |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 589 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 590 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 591 | reg = (reg & ~0x000fffff) | (val >> 12); |
| 592 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 593 | pci_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 594 | |
| 595 | // ME base |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 596 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x70); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 597 | val = mestolenbase & 0xfff; |
| 598 | reg = (reg & ~0xfff00000) | (val << 20); |
| 599 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 600 | pci_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 601 | |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 602 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x74); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 603 | val = mestolenbase & 0xfffff000; |
| 604 | reg = (reg & ~0x000fffff) | (val >> 12); |
| 605 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 606 | pci_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 607 | |
| 608 | // ME mask |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 609 | reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x78); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 610 | val = (0x80000 - me_uma_size) & 0xfff; |
| 611 | reg = (reg & ~0xfff00000) | (val << 20); |
| 612 | reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem |
| 613 | |
| 614 | reg = (reg & ~0x800) | (1 << 11); // set ME memory enable |
| 615 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 616 | pci_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 617 | } |
| 618 | } |
| 619 | |
| 620 | static void wait_428c(int channel) |
| 621 | { |
| 622 | while (1) { |
| 623 | if (read32(DEFAULT_MCHBAR + 0x428c + (channel << 10)) & 0x50) |
| 624 | return; |
| 625 | } |
| 626 | } |
| 627 | |
| 628 | static void write_reset(ramctr_timing * ctrl) |
| 629 | { |
| 630 | int channel, slotrank; |
| 631 | |
| 632 | /* choose a populated channel. */ |
| 633 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 634 | |
| 635 | wait_428c(channel); |
| 636 | |
| 637 | /* choose a populated rank. */ |
| 638 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 639 | |
| 640 | /* DRAM command ZQCS */ |
| 641 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); |
| 642 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01); |
| 643 | |
| 644 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 645 | (slotrank << 24) | 0x60000); |
| 646 | |
| 647 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 648 | |
| 649 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001); |
| 650 | wait_428c(channel); |
| 651 | } |
| 652 | |
| 653 | void dram_jedecreset(ramctr_timing * ctrl) |
| 654 | { |
| 655 | u32 reg, addr; |
| 656 | int channel; |
| 657 | |
| 658 | while (!(MCHBAR32(0x5084) & 0x10000)); |
| 659 | do { |
| 660 | reg = MCHBAR32(0x428c); |
| 661 | } while ((reg & 0x14) == 0); |
| 662 | |
| 663 | // Set state of memory controller |
| 664 | reg = 0x112; |
| 665 | MCHBAR32(0x5030) = reg; |
| 666 | MCHBAR32(0x4ea0) = 0; |
| 667 | reg |= 2; //ddr reset |
| 668 | MCHBAR32(0x5030) = reg; |
| 669 | |
| 670 | // Assert dimm reset signal |
| 671 | reg = MCHBAR32(0x5030); |
| 672 | reg &= ~0x2; |
| 673 | MCHBAR32(0x5030) = reg; |
| 674 | |
| 675 | // Wait 200us |
| 676 | udelay(200); |
| 677 | |
| 678 | // Deassert dimm reset signal |
| 679 | MCHBAR32(0x5030) |= 2; |
| 680 | |
| 681 | // Wait 500us |
| 682 | udelay(500); |
| 683 | |
| 684 | // Enable DCLK |
| 685 | MCHBAR32(0x5030) |= 4; |
| 686 | |
| 687 | // XXX Wait 20ns |
| 688 | udelay(1); |
| 689 | |
| 690 | FOR_ALL_CHANNELS { |
| 691 | // Set valid rank CKE |
| 692 | reg = 0; |
| 693 | reg = (reg & ~0xf) | ctrl->rankmap[channel]; |
| 694 | addr = 0x400 * channel + 0x42a0; |
| 695 | MCHBAR32(addr) = reg; |
| 696 | |
| 697 | // Wait 10ns for ranks to settle |
| 698 | //udelay(0.01); |
| 699 | |
| 700 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 701 | MCHBAR32(addr) = reg; |
| 702 | |
| 703 | // Write reset using a NOP |
| 704 | write_reset(ctrl); |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) |
| 709 | { |
| 710 | /* Get ODT based on rankmap: */ |
| 711 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) |
| 712 | + ((ctrl->rankmap[channel] >> 2) & 1); |
| 713 | |
| 714 | if (dimms_per_ch == 1) { |
| 715 | return (const odtmap){60, 60}; |
| 716 | } else { |
| 717 | return (const odtmap){120, 30}; |
| 718 | } |
| 719 | } |
| 720 | |
| 721 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, |
| 722 | int reg, u32 val) |
| 723 | { |
| 724 | wait_428c(channel); |
| 725 | |
| 726 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 727 | /* DDR3 Rank1 Address mirror |
| 728 | * swap the following pins: |
| 729 | * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
| 730 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
| 731 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) |
| 732 | | ((val & 0xa8) << 1); |
| 733 | } |
| 734 | |
| 735 | /* DRAM command MRS */ |
| 736 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); |
| 737 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); |
| 738 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 739 | (slotrank << 24) | (reg << 20) | val | 0x60000); |
| 740 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 741 | |
| 742 | /* DRAM command MRS */ |
| 743 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000); |
| 744 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001); |
| 745 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 746 | (slotrank << 24) | (reg << 20) | val | 0x60000); |
| 747 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 748 | |
| 749 | /* DRAM command MRS */ |
| 750 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000); |
| 751 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 752 | 0x1001 | (ctrl->tMOD << 16)); |
| 753 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 754 | (slotrank << 24) | (reg << 20) | val | 0x60000); |
| 755 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 756 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001); |
| 757 | } |
| 758 | |
| 759 | static u32 make_mr0(ramctr_timing * ctrl, u8 rank) |
| 760 | { |
| 761 | u16 mr0reg, mch_cas, mch_wr; |
| 762 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
| 763 | |
| 764 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 765 | mr0reg = 0x100; |
| 766 | |
| 767 | // Convert CAS to MCH register friendly |
| 768 | if (ctrl->CAS < 12) { |
| 769 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 770 | } else { |
| 771 | mch_cas = (u16) (ctrl->CAS - 12); |
| 772 | mch_cas = ((mch_cas << 1) | 0x1); |
| 773 | } |
| 774 | |
| 775 | // Convert tWR to MCH register friendly |
| 776 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 777 | |
| 778 | mr0reg = (mr0reg & ~0x4) | ((mch_cas & 0x1) << 2); |
| 779 | mr0reg = (mr0reg & ~0x70) | ((mch_cas & 0xe) << 3); |
| 780 | mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9); |
| 781 | |
| 782 | // Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature |
| 783 | mr0reg = (mr0reg & ~0x1000) | (!ctrl->mobile << 12); |
| 784 | return mr0reg; |
| 785 | } |
| 786 | |
| 787 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 788 | { |
| 789 | write_mrreg(ctrl, channel, rank, 0, |
| 790 | make_mr0(ctrl, rank)); |
| 791 | } |
| 792 | |
| 793 | static u32 encode_odt(u32 odt) |
| 794 | { |
| 795 | switch (odt) { |
| 796 | case 30: |
| 797 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 798 | case 60: |
| 799 | return (1 << 2); // RZQ/4 |
| 800 | case 120: |
| 801 | return (1 << 6); // RZQ/2 |
| 802 | default: |
| 803 | case 0: |
| 804 | return 0; |
| 805 | } |
| 806 | } |
| 807 | |
| 808 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 809 | { |
| 810 | odtmap odt; |
| 811 | u32 mr1reg; |
| 812 | |
| 813 | odt = get_ODT(ctrl, rank, channel); |
| 814 | mr1reg = 0x2; |
| 815 | |
| 816 | mr1reg |= encode_odt(odt.rttnom); |
| 817 | |
| 818 | return mr1reg; |
| 819 | } |
| 820 | |
| 821 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 822 | { |
| 823 | u16 mr1reg; |
| 824 | |
| 825 | mr1reg = make_mr1(ctrl, rank, channel); |
| 826 | |
| 827 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 828 | } |
| 829 | |
| 830 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 831 | { |
| 832 | u16 pasr, cwl, mr2reg; |
| 833 | odtmap odt; |
| 834 | int srt; |
| 835 | |
| 836 | pasr = 0; |
| 837 | cwl = ctrl->CWL - 5; |
| 838 | odt = get_ODT(ctrl, rank, channel); |
| 839 | |
| 840 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
| 841 | |
| 842 | mr2reg = 0; |
| 843 | mr2reg = (mr2reg & ~0x7) | pasr; |
| 844 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 845 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 846 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 847 | mr2reg |= (odt.rttwr / 60) << 9; |
| 848 | |
| 849 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
| 850 | } |
| 851 | |
| 852 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 853 | { |
| 854 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 855 | } |
| 856 | |
| 857 | void dram_mrscommands(ramctr_timing * ctrl) |
| 858 | { |
| 859 | u8 slotrank; |
| 860 | u32 reg, addr; |
| 861 | int channel; |
| 862 | |
| 863 | FOR_ALL_POPULATED_CHANNELS { |
| 864 | FOR_ALL_POPULATED_RANKS { |
| 865 | // MR2 |
| 866 | dram_mr2(ctrl, slotrank, channel); |
| 867 | |
| 868 | // MR3 |
| 869 | dram_mr3(ctrl, slotrank, channel); |
| 870 | |
| 871 | // MR1 |
| 872 | dram_mr1(ctrl, slotrank, channel); |
| 873 | |
| 874 | // MR0 |
| 875 | dram_mr0(ctrl, slotrank, channel); |
| 876 | } |
| 877 | } |
| 878 | |
| 879 | /* DRAM command NOP */ |
| 880 | write32(DEFAULT_MCHBAR + 0x4e20, 0x7); |
| 881 | write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001); |
| 882 | write32(DEFAULT_MCHBAR + 0x4e00, 0x60002); |
| 883 | write32(DEFAULT_MCHBAR + 0x4e10, 0); |
| 884 | |
| 885 | /* DRAM command ZQCL */ |
| 886 | write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003); |
| 887 | write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001); |
| 888 | write32(DEFAULT_MCHBAR + 0x4e04, 0x60400); |
| 889 | write32(DEFAULT_MCHBAR + 0x4e14, 0x288); |
| 890 | |
| 891 | /* execute command queue on all channels ? */ |
| 892 | write32(DEFAULT_MCHBAR + 0x4e84, 0x40004); |
| 893 | |
| 894 | // Drain |
| 895 | FOR_ALL_CHANNELS { |
| 896 | // Wait for ref drained |
| 897 | wait_428c(channel); |
| 898 | } |
| 899 | |
| 900 | // Refresh enable |
| 901 | MCHBAR32(0x5030) |= 8; |
| 902 | |
| 903 | FOR_ALL_POPULATED_CHANNELS { |
| 904 | addr = 0x400 * channel + 0x4020; |
| 905 | reg = MCHBAR32(addr); |
| 906 | reg &= ~0x200000; |
| 907 | MCHBAR32(addr) = reg; |
| 908 | |
| 909 | wait_428c(channel); |
| 910 | |
| 911 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 912 | |
| 913 | // Drain |
| 914 | wait_428c(channel); |
| 915 | |
| 916 | /* DRAM command ZQCS */ |
| 917 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); |
| 918 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); |
| 919 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 920 | (slotrank << 24) | 0x60000); |
| 921 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); |
| 922 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1); |
| 923 | |
| 924 | // Drain |
| 925 | wait_428c(channel); |
| 926 | } |
| 927 | } |
| 928 | |
| 929 | static const u32 lane_registers[] = { |
| 930 | 0x0000, 0x0200, 0x0400, 0x0600, |
| 931 | 0x1000, 0x1200, 0x1400, 0x1600, |
| 932 | 0x0800 |
| 933 | }; |
| 934 | |
| 935 | void program_timings(ramctr_timing * ctrl, int channel) |
| 936 | { |
| 937 | u32 reg32, reg_4024, reg_c14, reg_c18, reg_4028; |
| 938 | int lane; |
| 939 | int slotrank, slot; |
| 940 | int full_shift = 0; |
| 941 | u16 slot320c[NUM_SLOTS]; |
| 942 | |
| 943 | FOR_ALL_POPULATED_RANKS { |
| 944 | if (full_shift < -ctrl->timings[channel][slotrank].val_320c) |
| 945 | full_shift = -ctrl->timings[channel][slotrank].val_320c; |
| 946 | } |
| 947 | |
| 948 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 949 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 950 | case 0: |
| 951 | default: |
| 952 | slot320c[slot] = 0x7f; |
| 953 | break; |
| 954 | case 1: |
| 955 | slot320c[slot] = |
| 956 | ctrl->timings[channel][2 * slot + 0].val_320c + |
| 957 | full_shift; |
| 958 | break; |
| 959 | case 2: |
| 960 | slot320c[slot] = |
| 961 | ctrl->timings[channel][2 * slot + 1].val_320c + |
| 962 | full_shift; |
| 963 | break; |
| 964 | case 3: |
| 965 | slot320c[slot] = |
| 966 | (ctrl->timings[channel][2 * slot].val_320c + |
| 967 | ctrl->timings[channel][2 * slot + |
| 968 | 1].val_320c) / 2 + |
| 969 | full_shift; |
| 970 | break; |
| 971 | } |
| 972 | |
| 973 | /* enable CMD XOVER */ |
| 974 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
| 975 | reg32 |= ((slot320c[0] & 0x3f) << 6) | ((slot320c[0] & 0x40) << 9); |
| 976 | reg32 |= (slot320c[1] & 0x7f) << 18; |
| 977 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 978 | |
| 979 | MCHBAR32(0x320c + 0x100 * channel) = reg32; |
| 980 | |
| 981 | /* enable CLK XOVER */ |
| 982 | reg_c14 = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 983 | reg_c18 = 0; |
| 984 | |
| 985 | FOR_ALL_POPULATED_RANKS { |
| 986 | int shift = |
| 987 | ctrl->timings[channel][slotrank].val_320c + full_shift; |
| 988 | int offset_val_c14; |
| 989 | if (shift < 0) |
| 990 | shift = 0; |
| 991 | offset_val_c14 = ctrl->reg_c14_offset + shift; |
| 992 | /* set CLK phase shift */ |
| 993 | reg_c14 |= (offset_val_c14 & 0x3f) << (6 * slotrank); |
| 994 | reg_c18 |= ((offset_val_c14 >> 6) & 1) << slotrank; |
| 995 | } |
| 996 | |
| 997 | MCHBAR32(0xc14 + channel * 0x100) = reg_c14; |
| 998 | MCHBAR32(0xc18 + channel * 0x100) = reg_c18; |
| 999 | |
| 1000 | reg_4028 = MCHBAR32(0x4028 + 0x400 * channel); |
| 1001 | reg_4028 &= 0xffff0000; |
| 1002 | |
| 1003 | reg_4024 = 0; |
| 1004 | |
| 1005 | FOR_ALL_POPULATED_RANKS { |
| 1006 | int post_timA_min_high = 7, post_timA_max_high = 0; |
| 1007 | int pre_timA_min_high = 7, pre_timA_max_high = 0; |
| 1008 | int shift_402x = 0; |
| 1009 | int shift = |
| 1010 | ctrl->timings[channel][slotrank].val_320c + full_shift; |
| 1011 | |
| 1012 | if (shift < 0) |
| 1013 | shift = 0; |
| 1014 | |
| 1015 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 1016 | post_timA_min_high = MIN(post_timA_min_high, |
| 1017 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1018 | timA + shift) >> 6); |
| 1019 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 1020 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1021 | timA >> 6); |
| 1022 | post_timA_max_high = MAX(post_timA_max_high, |
| 1023 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1024 | timA + shift) >> 6); |
| 1025 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 1026 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1027 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1028 | } |
| 1029 | |
| 1030 | if (pre_timA_max_high - pre_timA_min_high < |
| 1031 | post_timA_max_high - post_timA_min_high) |
| 1032 | shift_402x = +1; |
| 1033 | else if (pre_timA_max_high - pre_timA_min_high > |
| 1034 | post_timA_max_high - post_timA_min_high) |
| 1035 | shift_402x = -1; |
| 1036 | |
| 1037 | reg_4028 |= |
| 1038 | (ctrl->timings[channel][slotrank].val_4028 + shift_402x - |
| 1039 | post_timA_min_high) << (4 * slotrank); |
| 1040 | reg_4024 |= |
| 1041 | (ctrl->timings[channel][slotrank].val_4024 + |
| 1042 | shift_402x) << (8 * slotrank); |
| 1043 | |
| 1044 | FOR_ALL_LANES { |
| 1045 | MCHBAR32(lane_registers[lane] + 0x10 + 0x100 * channel + |
| 1046 | 4 * slotrank) |
| 1047 | = |
| 1048 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1049 | timA + shift) & 0x3f) |
| 1050 | | |
| 1051 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1052 | rising + shift) << 8) |
| 1053 | | |
| 1054 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1055 | timA + shift - |
| 1056 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1057 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1058 | falling + shift) << 20)); |
| 1059 | |
| 1060 | MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel + |
| 1061 | 4 * slotrank) |
| 1062 | = |
| 1063 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1064 | timC + shift) & 0x3f) |
| 1065 | | |
| 1066 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1067 | timB + shift) & 0x3f) << 8) |
| 1068 | | |
| 1069 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1070 | timB + shift) & 0x1c0) << 9) |
| 1071 | | |
| 1072 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1073 | timC + shift) & 0x40) << 13)); |
| 1074 | } |
| 1075 | } |
| 1076 | MCHBAR32(0x4024 + 0x400 * channel) = reg_4024; |
| 1077 | MCHBAR32(0x4028 + 0x400 * channel) = reg_4028; |
| 1078 | } |
| 1079 | |
| 1080 | static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) |
| 1081 | { |
| 1082 | wait_428c(channel); |
| 1083 | |
| 1084 | /* DRAM command MRS |
| 1085 | * write MR3 MPR enable |
| 1086 | * in this mode only RD and RDA are allowed |
| 1087 | * all reads return a predefined pattern */ |
| 1088 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); |
| 1089 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1090 | (0xc01 | (ctrl->tMOD << 16))); |
| 1091 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1092 | (slotrank << 24) | 0x360004); |
| 1093 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 1094 | |
| 1095 | /* DRAM command RD */ |
| 1096 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); |
| 1097 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01); |
| 1098 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24)); |
| 1099 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 1100 | |
| 1101 | /* DRAM command RD */ |
| 1102 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); |
| 1103 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 1104 | 0x100f | ((ctrl->CAS + 36) << 16)); |
| 1105 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 1106 | (slotrank << 24) | 0x60000); |
| 1107 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 1108 | |
| 1109 | /* DRAM command MRS |
| 1110 | * write MR3 MPR disable */ |
| 1111 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); |
| 1112 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 1113 | (0xc01 | (ctrl->tMOD << 16))); |
| 1114 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 1115 | (slotrank << 24) | 0x360000); |
| 1116 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 1117 | |
| 1118 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); |
| 1119 | |
| 1120 | wait_428c(channel); |
| 1121 | } |
| 1122 | |
| 1123 | static int does_lane_work(ramctr_timing * ctrl, int channel, int slotrank, |
| 1124 | int lane) |
| 1125 | { |
| 1126 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
| 1127 | return ((read32 |
| 1128 | (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + |
| 1129 | ((timA / 32) & 1) * 4) |
| 1130 | >> (timA % 32)) & 1); |
| 1131 | } |
| 1132 | |
| 1133 | struct run { |
| 1134 | int middle; |
| 1135 | int end; |
| 1136 | int start; |
| 1137 | int all; |
| 1138 | int length; |
| 1139 | }; |
| 1140 | |
| 1141 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1142 | { |
| 1143 | int i, ls; |
| 1144 | int bl = 0, bs = 0; |
| 1145 | struct run ret; |
| 1146 | |
| 1147 | ls = 0; |
| 1148 | for (i = 0; i < 2 * sz; i++) |
| 1149 | if (seq[i % sz]) { |
| 1150 | if (i - ls > bl) { |
| 1151 | bl = i - ls; |
| 1152 | bs = ls; |
| 1153 | } |
| 1154 | ls = i + 1; |
| 1155 | } |
| 1156 | if (bl == 0) { |
| 1157 | ret.middle = sz / 2; |
| 1158 | ret.start = 0; |
| 1159 | ret.end = sz; |
| 1160 | ret.all = 1; |
| 1161 | return ret; |
| 1162 | } |
| 1163 | |
| 1164 | ret.start = bs % sz; |
| 1165 | ret.end = (bs + bl - 1) % sz; |
| 1166 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1167 | ret.length = bl; |
| 1168 | ret.all = 0; |
| 1169 | |
| 1170 | return ret; |
| 1171 | } |
| 1172 | |
| 1173 | static void discover_timA_coarse(ramctr_timing * ctrl, int channel, |
| 1174 | int slotrank, int *upperA) |
| 1175 | { |
| 1176 | int timA; |
| 1177 | int statistics[NUM_LANES][128]; |
| 1178 | int lane; |
| 1179 | |
| 1180 | for (timA = 0; timA < 128; timA++) { |
| 1181 | FOR_ALL_LANES { |
| 1182 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1183 | } |
| 1184 | program_timings(ctrl, channel); |
| 1185 | |
| 1186 | test_timA(ctrl, channel, slotrank); |
| 1187 | |
| 1188 | FOR_ALL_LANES { |
| 1189 | statistics[lane][timA] = |
| 1190 | !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1191 | } |
| 1192 | } |
| 1193 | FOR_ALL_LANES { |
| 1194 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1195 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1196 | upperA[lane] = rn.end; |
| 1197 | if (upperA[lane] < rn.middle) |
| 1198 | upperA[lane] += 128; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1199 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1200 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1201 | } |
| 1202 | } |
| 1203 | |
| 1204 | static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, |
| 1205 | int *upperA) |
| 1206 | { |
| 1207 | int timA_delta; |
| 1208 | int statistics[NUM_LANES][51]; |
| 1209 | int lane, i; |
| 1210 | |
| 1211 | memset(statistics, 0, sizeof(statistics)); |
| 1212 | |
| 1213 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
| 1214 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. |
| 1215 | timA = upperA[lane] + timA_delta + 0x40; |
| 1216 | program_timings(ctrl, channel); |
| 1217 | |
| 1218 | for (i = 0; i < 100; i++) { |
| 1219 | test_timA(ctrl, channel, slotrank); |
| 1220 | FOR_ALL_LANES { |
| 1221 | statistics[lane][timA_delta + 25] += |
| 1222 | does_lane_work(ctrl, channel, slotrank, |
| 1223 | lane); |
| 1224 | } |
| 1225 | } |
| 1226 | } |
| 1227 | FOR_ALL_LANES { |
| 1228 | int last_zero, first_all; |
| 1229 | |
| 1230 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1231 | if (statistics[lane][last_zero + 25]) |
| 1232 | break; |
| 1233 | last_zero--; |
| 1234 | for (first_all = -25; first_all <= 25; first_all++) |
| 1235 | if (statistics[lane][first_all + 25] == 100) |
| 1236 | break; |
| 1237 | |
| 1238 | printram("lane %d: %d, %d\n", lane, last_zero, |
| 1239 | first_all); |
| 1240 | |
| 1241 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
| 1242 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1243 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
| 1244 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
| 1245 | } |
| 1246 | } |
| 1247 | |
| 1248 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, |
| 1249 | int *upperA) |
| 1250 | { |
| 1251 | int works[NUM_LANES]; |
| 1252 | int lane; |
| 1253 | while (1) { |
| 1254 | int all_works = 1, some_works = 0; |
| 1255 | program_timings(ctrl, channel); |
| 1256 | test_timA(ctrl, channel, slotrank); |
| 1257 | FOR_ALL_LANES { |
| 1258 | works[lane] = |
| 1259 | !does_lane_work(ctrl, channel, slotrank, lane); |
| 1260 | if (works[lane]) |
| 1261 | some_works = 1; |
| 1262 | else |
| 1263 | all_works = 0; |
| 1264 | } |
| 1265 | if (all_works) |
| 1266 | return 0; |
| 1267 | if (!some_works) { |
| 1268 | if (ctrl->timings[channel][slotrank].val_4024 < 2) { |
| 1269 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1270 | channel, slotrank); |
| 1271 | return MAKE_ERR; |
| 1272 | } |
| 1273 | ctrl->timings[channel][slotrank].val_4024 -= 2; |
| 1274 | printram("4024 -= 2;\n"); |
| 1275 | continue; |
| 1276 | } |
| 1277 | ctrl->timings[channel][slotrank].val_4028 += 2; |
| 1278 | printram("4028 += 2;\n"); |
| 1279 | if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) { |
| 1280 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1281 | channel, slotrank); |
| 1282 | return MAKE_ERR; |
| 1283 | } |
| 1284 | FOR_ALL_LANES if (works[lane]) { |
| 1285 | ctrl->timings[channel][slotrank].lanes[lane].timA += |
| 1286 | 128; |
| 1287 | upperA[lane] += 128; |
| 1288 | printram("increment %d, %d, %d\n", channel, |
| 1289 | slotrank, lane); |
| 1290 | } |
| 1291 | } |
| 1292 | return 0; |
| 1293 | } |
| 1294 | |
| 1295 | struct timA_minmax { |
| 1296 | int timA_min_high, timA_max_high; |
| 1297 | }; |
| 1298 | |
| 1299 | static void pre_timA_change(ramctr_timing * ctrl, int channel, int slotrank, |
| 1300 | struct timA_minmax *mnmx) |
| 1301 | { |
| 1302 | int lane; |
| 1303 | mnmx->timA_min_high = 7; |
| 1304 | mnmx->timA_max_high = 0; |
| 1305 | |
| 1306 | FOR_ALL_LANES { |
| 1307 | if (mnmx->timA_min_high > |
| 1308 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1309 | mnmx->timA_min_high = |
| 1310 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1311 | timA >> 6); |
| 1312 | if (mnmx->timA_max_high < |
| 1313 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1314 | mnmx->timA_max_high = |
| 1315 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1316 | timA >> 6); |
| 1317 | } |
| 1318 | } |
| 1319 | |
| 1320 | static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank, |
| 1321 | struct timA_minmax *mnmx) |
| 1322 | { |
| 1323 | struct timA_minmax post; |
| 1324 | int shift_402x = 0; |
| 1325 | |
| 1326 | /* Get changed maxima. */ |
| 1327 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1328 | |
| 1329 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1330 | post.timA_max_high - post.timA_min_high) |
| 1331 | shift_402x = +1; |
| 1332 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1333 | post.timA_max_high - post.timA_min_high) |
| 1334 | shift_402x = -1; |
| 1335 | else |
| 1336 | shift_402x = 0; |
| 1337 | |
| 1338 | ctrl->timings[channel][slotrank].val_4028 += shift_402x; |
| 1339 | ctrl->timings[channel][slotrank].val_4024 += shift_402x; |
| 1340 | printram("4024 += %d;\n", shift_402x); |
| 1341 | printram("4028 += %d;\n", shift_402x); |
| 1342 | } |
| 1343 | |
| 1344 | /* Compensate the skew between DQS and DQs. |
| 1345 | * To ease PCB design a small skew between Data Strobe signals and |
| 1346 | * Data Signals is allowed. |
| 1347 | * The controller has to measure and compensate this skew for every byte-lane. |
| 1348 | * By delaying either all DQs signals or DQS signal, a full phase |
| 1349 | * shift can be introduced. |
| 1350 | * It is assumed that one byte-lane's DQs signals have the same routing delay. |
| 1351 | * |
| 1352 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. |
| 1353 | * In read leveling mode the DRAM-chip outputs an alternating periodic pattern. |
| 1354 | * The memory controller iterates over all possible values to do a full phase shift |
| 1355 | * and issues read commands. |
| 1356 | * With DQS and DQs in phase the data read is expected to alternate on every byte: |
| 1357 | * 0xFF 0x00 0xFF ... |
| 1358 | * Once the controller has detected this pattern a bit in the result register is |
| 1359 | * set for the current phase shift. |
| 1360 | */ |
| 1361 | int read_training(ramctr_timing * ctrl) |
| 1362 | { |
| 1363 | int channel, slotrank, lane; |
| 1364 | int err; |
| 1365 | |
| 1366 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1367 | int all_high, some_high; |
| 1368 | int upperA[NUM_LANES]; |
| 1369 | struct timA_minmax mnmx; |
| 1370 | |
| 1371 | wait_428c(channel); |
| 1372 | |
| 1373 | /* DRAM command PREA */ |
| 1374 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); |
| 1375 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1376 | 0xc01 | (ctrl->tRP << 16)); |
| 1377 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1378 | (slotrank << 24) | 0x60400); |
| 1379 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 1380 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); |
| 1381 | |
| 1382 | write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001); |
| 1383 | |
| 1384 | ctrl->timings[channel][slotrank].val_4028 = 4; |
| 1385 | ctrl->timings[channel][slotrank].val_4024 = 55; |
| 1386 | program_timings(ctrl, channel); |
| 1387 | |
| 1388 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
| 1389 | |
| 1390 | all_high = 1; |
| 1391 | some_high = 0; |
| 1392 | FOR_ALL_LANES { |
| 1393 | if (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1394 | timA >= 0x40) |
| 1395 | some_high = 1; |
| 1396 | else |
| 1397 | all_high = 0; |
| 1398 | } |
| 1399 | |
| 1400 | if (all_high) { |
| 1401 | ctrl->timings[channel][slotrank].val_4028--; |
| 1402 | printram("4028--;\n"); |
| 1403 | FOR_ALL_LANES { |
| 1404 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1405 | timA -= 0x40; |
| 1406 | upperA[lane] -= 0x40; |
| 1407 | |
| 1408 | } |
| 1409 | } else if (some_high) { |
| 1410 | ctrl->timings[channel][slotrank].val_4024++; |
| 1411 | ctrl->timings[channel][slotrank].val_4028++; |
| 1412 | printram("4024++;\n"); |
| 1413 | printram("4028++;\n"); |
| 1414 | } |
| 1415 | |
| 1416 | program_timings(ctrl, channel); |
| 1417 | |
| 1418 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1419 | |
| 1420 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1421 | if (err) |
| 1422 | return err; |
| 1423 | |
| 1424 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1425 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1426 | |
| 1427 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1428 | |
| 1429 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1430 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1431 | |
| 1432 | FOR_ALL_LANES { |
| 1433 | ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; |
| 1434 | } |
| 1435 | ctrl->timings[channel][slotrank].val_4028 -= mnmx.timA_min_high; |
| 1436 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1437 | |
| 1438 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1439 | |
| 1440 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
| 1441 | ctrl->timings[channel][slotrank].val_4024, |
| 1442 | ctrl->timings[channel][slotrank].val_4028); |
| 1443 | |
| 1444 | printram("final results:\n"); |
| 1445 | FOR_ALL_LANES |
| 1446 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
| 1447 | lane, |
| 1448 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
| 1449 | |
| 1450 | write32(DEFAULT_MCHBAR + 0x3400, 0); |
| 1451 | |
| 1452 | toggle_io_reset(); |
| 1453 | } |
| 1454 | |
| 1455 | FOR_ALL_POPULATED_CHANNELS { |
| 1456 | program_timings(ctrl, channel); |
| 1457 | } |
| 1458 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 1459 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel |
| 1460 | + 4 * lane, 0); |
| 1461 | } |
| 1462 | return 0; |
| 1463 | } |
| 1464 | |
| 1465 | static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) |
| 1466 | { |
| 1467 | int lane; |
| 1468 | |
| 1469 | FOR_ALL_LANES { |
| 1470 | write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane, 0); |
| 1471 | read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane); |
| 1472 | } |
| 1473 | |
| 1474 | wait_428c(channel); |
| 1475 | |
| 1476 | /* DRAM command ACT */ |
| 1477 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); |
| 1478 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1479 | (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) |
| 1480 | | 4 | (ctrl->tRCD << 16)); |
| 1481 | |
| 1482 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1483 | (slotrank << 24) | (6 << 16)); |
| 1484 | |
| 1485 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); |
| 1486 | |
| 1487 | /* DRAM command NOP */ |
| 1488 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); |
| 1489 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001); |
| 1490 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1491 | (slotrank << 24) | 8); |
| 1492 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); |
| 1493 | |
| 1494 | /* DRAM command WR */ |
| 1495 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); |
| 1496 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4); |
| 1497 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); |
| 1498 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); |
| 1499 | |
| 1500 | /* DRAM command NOP */ |
| 1501 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); |
| 1502 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 1503 | 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); |
| 1504 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 1505 | (slotrank << 24) | 8); |
| 1506 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0); |
| 1507 | |
| 1508 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); |
| 1509 | |
| 1510 | wait_428c(channel); |
| 1511 | |
| 1512 | /* DRAM command PREA */ |
| 1513 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); |
| 1514 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1515 | 0xc01 | (ctrl->tRP << 16)); |
| 1516 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1517 | (slotrank << 24) | 0x60400); |
| 1518 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); |
| 1519 | |
| 1520 | /* DRAM command ACT */ |
| 1521 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); |
| 1522 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 1523 | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) |
| 1524 | | 8 | (ctrl->CAS << 16)); |
| 1525 | |
| 1526 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1527 | (slotrank << 24) | 0x60000); |
| 1528 | |
| 1529 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244); |
| 1530 | |
| 1531 | /* DRAM command RD */ |
| 1532 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); |
| 1533 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 1534 | 0x40011f4 | (max(ctrl->tRTP, 8) << 16)); |
| 1535 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); |
| 1536 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); |
| 1537 | |
| 1538 | /* DRAM command PREA */ |
| 1539 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); |
| 1540 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 1541 | 0xc01 | (ctrl->tRP << 16)); |
| 1542 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 1543 | (slotrank << 24) | 0x60400); |
| 1544 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240); |
| 1545 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); |
| 1546 | wait_428c(channel); |
| 1547 | } |
| 1548 | |
| 1549 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1550 | { |
| 1551 | int timC; |
| 1552 | int statistics[NUM_LANES][MAX_TIMC + 1]; |
| 1553 | int lane; |
| 1554 | |
| 1555 | wait_428c(channel); |
| 1556 | |
| 1557 | /* DRAM command PREA */ |
| 1558 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); |
| 1559 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1560 | 0xc01 | (ctrl->tRP << 16)); |
| 1561 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1562 | (slotrank << 24) | 0x60400); |
| 1563 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); |
| 1564 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); |
| 1565 | |
| 1566 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
| 1567 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. |
| 1568 | timC = timC; |
| 1569 | program_timings(ctrl, channel); |
| 1570 | |
| 1571 | test_timC(ctrl, channel, slotrank); |
| 1572 | |
| 1573 | FOR_ALL_LANES { |
| 1574 | statistics[lane][timC] = |
| 1575 | read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + |
| 1576 | 0x400 * channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1577 | } |
| 1578 | } |
| 1579 | FOR_ALL_LANES { |
| 1580 | struct run rn = |
| 1581 | get_longest_zero_run(statistics[lane], MAX_TIMC + 1); |
| 1582 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
| 1583 | if (rn.all) { |
| 1584 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1585 | channel, slotrank, lane); |
| 1586 | return MAKE_ERR; |
| 1587 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1588 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1589 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1590 | } |
| 1591 | return 0; |
| 1592 | } |
| 1593 | |
| 1594 | static int get_precedening_channels(ramctr_timing * ctrl, int target_channel) |
| 1595 | { |
| 1596 | int channel, ret = 0; |
| 1597 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1598 | ret++; |
| 1599 | return ret; |
| 1600 | } |
| 1601 | |
| 1602 | static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b) |
| 1603 | { |
| 1604 | unsigned j; |
| 1605 | unsigned channel_offset = |
| 1606 | get_precedening_channels(ctrl, channel) * 0x40; |
| 1607 | for (j = 0; j < 16; j++) |
| 1608 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
| 1609 | sfence(); |
| 1610 | } |
| 1611 | |
| 1612 | static int num_of_channels(const ramctr_timing * ctrl) |
| 1613 | { |
| 1614 | int ret = 0; |
| 1615 | int channel; |
| 1616 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1617 | return ret; |
| 1618 | } |
| 1619 | |
| 1620 | static void fill_pattern1(ramctr_timing * ctrl, int channel) |
| 1621 | { |
| 1622 | unsigned j; |
| 1623 | unsigned channel_offset = |
| 1624 | get_precedening_channels(ctrl, channel) * 0x40; |
| 1625 | unsigned channel_step = 0x40 * num_of_channels(ctrl); |
| 1626 | for (j = 0; j < 16; j++) |
| 1627 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
| 1628 | for (j = 0; j < 16; j++) |
| 1629 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
| 1630 | sfence(); |
| 1631 | } |
| 1632 | |
| 1633 | static void precharge(ramctr_timing * ctrl) |
| 1634 | { |
| 1635 | int channel, slotrank, lane; |
| 1636 | |
| 1637 | FOR_ALL_POPULATED_CHANNELS { |
| 1638 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 1639 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 1640 | 16; |
| 1641 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 1642 | 16; |
| 1643 | } |
| 1644 | |
| 1645 | program_timings(ctrl, channel); |
| 1646 | |
| 1647 | FOR_ALL_POPULATED_RANKS { |
| 1648 | wait_428c(channel); |
| 1649 | |
| 1650 | /* DRAM command MRS |
| 1651 | * write MR3 MPR enable |
| 1652 | * in this mode only RD and RDA are allowed |
| 1653 | * all reads return a predefined pattern */ |
| 1654 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, |
| 1655 | 0x1f000); |
| 1656 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1657 | 0xc01 | (ctrl->tMOD << 16)); |
| 1658 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1659 | (slotrank << 24) | 0x360004); |
| 1660 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 1661 | |
| 1662 | /* DRAM command RD */ |
| 1663 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, |
| 1664 | 0x1f105); |
| 1665 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 1666 | 0x4041003); |
| 1667 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1668 | (slotrank << 24) | 0); |
| 1669 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 1670 | |
| 1671 | /* DRAM command RD */ |
| 1672 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, |
| 1673 | 0x1f105); |
| 1674 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 1675 | 0x1001 | ((ctrl->CAS + 8) << 16)); |
| 1676 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 1677 | (slotrank << 24) | 0x60000); |
| 1678 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 1679 | |
| 1680 | /* DRAM command MRS |
| 1681 | * write MR3 MPR disable */ |
| 1682 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, |
| 1683 | 0x1f000); |
| 1684 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 1685 | 0xc01 | (ctrl->tMOD << 16)); |
| 1686 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 1687 | (slotrank << 24) | 0x360000); |
| 1688 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 1689 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, |
| 1690 | 0xc0001); |
| 1691 | |
| 1692 | wait_428c(channel); |
| 1693 | } |
| 1694 | |
| 1695 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 1696 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 1697 | 48; |
| 1698 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 1699 | 48; |
| 1700 | } |
| 1701 | |
| 1702 | program_timings(ctrl, channel); |
| 1703 | |
| 1704 | FOR_ALL_POPULATED_RANKS { |
| 1705 | wait_428c(channel); |
| 1706 | /* DRAM command MRS |
| 1707 | * write MR3 MPR enable |
| 1708 | * in this mode only RD and RDA are allowed |
| 1709 | * all reads return a predefined pattern */ |
| 1710 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, |
| 1711 | 0x1f000); |
| 1712 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1713 | 0xc01 | (ctrl->tMOD << 16)); |
| 1714 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1715 | (slotrank << 24) | 0x360004); |
| 1716 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 1717 | |
| 1718 | /* DRAM command RD */ |
| 1719 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, |
| 1720 | 0x1f105); |
| 1721 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 1722 | 0x4041003); |
| 1723 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1724 | (slotrank << 24) | 0); |
| 1725 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 1726 | |
| 1727 | /* DRAM command RD */ |
| 1728 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, |
| 1729 | 0x1f105); |
| 1730 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 1731 | 0x1001 | ((ctrl->CAS + 8) << 16)); |
| 1732 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 1733 | (slotrank << 24) | 0x60000); |
| 1734 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 1735 | |
| 1736 | /* DRAM command MRS |
| 1737 | * write MR3 MPR disable */ |
| 1738 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, |
| 1739 | 0x1f000); |
| 1740 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 1741 | 0xc01 | (ctrl->tMOD << 16)); |
| 1742 | |
| 1743 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 1744 | (slotrank << 24) | 0x360000); |
| 1745 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 1746 | |
| 1747 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, |
| 1748 | 0xc0001); |
| 1749 | wait_428c(channel); |
| 1750 | } |
| 1751 | } |
| 1752 | } |
| 1753 | |
| 1754 | static void test_timB(ramctr_timing * ctrl, int channel, int slotrank) |
| 1755 | { |
| 1756 | /* enable DQs on this slotrank */ |
| 1757 | write_mrreg(ctrl, channel, slotrank, 1, |
| 1758 | 0x80 | make_mr1(ctrl, slotrank, channel)); |
| 1759 | |
| 1760 | wait_428c(channel); |
| 1761 | /* DRAM command NOP */ |
| 1762 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207); |
| 1763 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1764 | 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16)); |
| 1765 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1766 | 8 | (slotrank << 24)); |
| 1767 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 1768 | |
| 1769 | /* DRAM command NOP */ |
| 1770 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107); |
| 1771 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 1772 | 0x4000c01 | ((ctrl->CAS + 38) << 16)); |
| 1773 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1774 | (slotrank << 24) | 4); |
| 1775 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 1776 | |
| 1777 | write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001); |
| 1778 | wait_428c(channel); |
| 1779 | |
| 1780 | /* disable DQs on this slotrank */ |
| 1781 | write_mrreg(ctrl, channel, slotrank, 1, |
| 1782 | 0x1080 | make_mr1(ctrl, slotrank, channel)); |
| 1783 | } |
| 1784 | |
| 1785 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1786 | { |
| 1787 | int timB; |
| 1788 | int statistics[NUM_LANES][128]; |
| 1789 | int lane; |
| 1790 | |
| 1791 | write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2)); |
| 1792 | |
| 1793 | for (timB = 0; timB < 128; timB++) { |
| 1794 | FOR_ALL_LANES { |
| 1795 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1796 | } |
| 1797 | program_timings(ctrl, channel); |
| 1798 | |
| 1799 | test_timB(ctrl, channel, slotrank); |
| 1800 | |
| 1801 | FOR_ALL_LANES { |
| 1802 | statistics[lane][timB] = |
| 1803 | !((read32 |
| 1804 | (DEFAULT_MCHBAR + lane_registers[lane] + |
| 1805 | channel * 0x100 + 4 + ((timB / 32) & 1) * 4) |
| 1806 | >> (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1807 | } |
| 1808 | } |
| 1809 | FOR_ALL_LANES { |
| 1810 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1811 | /* timC is a direct function of timB's 6 LSBs. |
| 1812 | * Some tests increments the value of timB by a small value, |
| 1813 | * which might cause the 6bit value to overflow, if it's close |
| 1814 | * to 0x3F. Increment the value by a small offset if it's likely |
| 1815 | * to overflow, to make sure it won't overflow while running |
| 1816 | * tests and bricks the system due to a non matching timC. |
| 1817 | * |
| 1818 | * TODO: find out why some tests (edge write discovery) |
| 1819 | * increment timB. */ |
| 1820 | if ((rn.start & 0x3F) == 0x3E) |
| 1821 | rn.start += 2; |
| 1822 | else if ((rn.start & 0x3F) == 0x3F) |
| 1823 | rn.start += 1; |
| 1824 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1825 | if (rn.all) { |
| 1826 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1827 | channel, slotrank, lane); |
| 1828 | return MAKE_ERR; |
| 1829 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1830 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1831 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1832 | } |
| 1833 | return 0; |
| 1834 | } |
| 1835 | |
| 1836 | static int get_timB_high_adjust(u64 val) |
| 1837 | { |
| 1838 | int i; |
| 1839 | |
| 1840 | /* good */ |
| 1841 | if (val == 0xffffffffffffffffLL) |
| 1842 | return 0; |
| 1843 | |
| 1844 | if (val >= 0xf000000000000000LL) { |
| 1845 | /* needs negative adjustment */ |
| 1846 | for (i = 0; i < 8; i++) |
| 1847 | if (val << (8 * (7 - i) + 4)) |
| 1848 | return -i; |
| 1849 | } else { |
| 1850 | /* needs positive adjustment */ |
| 1851 | for (i = 0; i < 8; i++) |
| 1852 | if (val >> (8 * (7 - i) + 4)) |
| 1853 | return i; |
| 1854 | } |
| 1855 | return 8; |
| 1856 | } |
| 1857 | |
| 1858 | static void adjust_high_timB(ramctr_timing * ctrl) |
| 1859 | { |
| 1860 | int channel, slotrank, lane, old; |
| 1861 | write32(DEFAULT_MCHBAR + 0x3400, 0x200); |
| 1862 | FOR_ALL_POPULATED_CHANNELS { |
| 1863 | fill_pattern1(ctrl, channel); |
| 1864 | write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 1); |
| 1865 | } |
| 1866 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1867 | |
| 1868 | write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001); |
| 1869 | |
| 1870 | wait_428c(channel); |
| 1871 | |
| 1872 | /* DRAM command ACT */ |
| 1873 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); |
| 1874 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1875 | 0xc01 | (ctrl->tRCD << 16)); |
| 1876 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1877 | (slotrank << 24) | 0x60000); |
| 1878 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 1879 | |
| 1880 | /* DRAM command NOP */ |
| 1881 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); |
| 1882 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01); |
| 1883 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1884 | (slotrank << 24) | 0x8); |
| 1885 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); |
| 1886 | |
| 1887 | /* DRAM command WR */ |
| 1888 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); |
| 1889 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003); |
| 1890 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 1891 | (slotrank << 24)); |
| 1892 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2); |
| 1893 | |
| 1894 | /* DRAM command NOP */ |
| 1895 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); |
| 1896 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 1897 | 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); |
| 1898 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 1899 | (slotrank << 24) | 0x8); |
| 1900 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0); |
| 1901 | |
| 1902 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); |
| 1903 | |
| 1904 | wait_428c(channel); |
| 1905 | |
| 1906 | /* DRAM command PREA */ |
| 1907 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); |
| 1908 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 1909 | 0xc01 | ((ctrl->tRP) << 16)); |
| 1910 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1911 | (slotrank << 24) | 0x60400); |
| 1912 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); |
| 1913 | |
| 1914 | /* DRAM command ACT */ |
| 1915 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); |
| 1916 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 1917 | 0xc01 | ((ctrl->tRCD) << 16)); |
| 1918 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 1919 | (slotrank << 24) | 0x60000); |
| 1920 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 1921 | |
| 1922 | /* DRAM command RD */ |
| 1923 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105); |
| 1924 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 1925 | 0x4000c01 | |
| 1926 | ((ctrl->tRP + |
| 1927 | ctrl->timings[channel][slotrank].val_4024 + |
| 1928 | ctrl->timings[channel][slotrank].val_4028) << 16)); |
| 1929 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 1930 | (slotrank << 24) | 0x60008); |
| 1931 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 1932 | |
| 1933 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001); |
| 1934 | wait_428c(channel); |
| 1935 | FOR_ALL_LANES { |
| 1936 | u64 res = |
| 1937 | read32(DEFAULT_MCHBAR + lane_registers[lane] + |
| 1938 | 0x100 * channel + 4); |
| 1939 | res |= |
| 1940 | ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + |
| 1941 | 0x100 * channel + 8)) << 32; |
| 1942 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 1943 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 1944 | get_timB_high_adjust(res) * 64; |
| 1945 | |
| 1946 | printram("High adjust %d:%016llx\n", lane, res); |
| 1947 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, |
| 1948 | slotrank, lane, old, |
| 1949 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1950 | timB); |
| 1951 | } |
| 1952 | } |
| 1953 | write32(DEFAULT_MCHBAR + 0x3400, 0); |
| 1954 | } |
| 1955 | |
| 1956 | static void write_op(ramctr_timing * ctrl, int channel) |
| 1957 | { |
| 1958 | int slotrank; |
| 1959 | |
| 1960 | wait_428c(channel); |
| 1961 | |
| 1962 | /* choose an existing rank. */ |
| 1963 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 1964 | |
| 1965 | /* DRAM command ACT */ |
| 1966 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); |
| 1967 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); |
| 1968 | |
| 1969 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 1970 | (slotrank << 24) | 0x60000); |
| 1971 | |
| 1972 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); |
| 1973 | |
| 1974 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); |
| 1975 | wait_428c(channel); |
| 1976 | } |
| 1977 | |
| 1978 | /* Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
| 1979 | * DDR3 adopted the fly-by topology. The data and strobes signals reach |
| 1980 | * the chips at different times with respect to command, address and |
| 1981 | * clock signals. |
| 1982 | * By delaying either all DQ/DQs or all CMD/ADDR/CLK signals, a full phase |
| 1983 | * shift can be introduced. |
| 1984 | * It is assumed that the CLK/ADDR/CMD signals have the same routing delay. |
| 1985 | * |
| 1986 | * To find the required phase shift the DRAM is placed in "write leveling" mode. |
| 1987 | * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the |
| 1988 | * sampled value on the data lanes (DQs). |
| 1989 | */ |
| 1990 | int write_training(ramctr_timing * ctrl) |
| 1991 | { |
| 1992 | int channel, slotrank, lane; |
| 1993 | int err; |
| 1994 | |
| 1995 | FOR_ALL_POPULATED_CHANNELS |
| 1996 | write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, |
| 1997 | read32(DEFAULT_MCHBAR + 0x4008 + |
| 1998 | 0x400 * channel) | 0x8000000); |
| 1999 | |
| 2000 | FOR_ALL_POPULATED_CHANNELS { |
| 2001 | write_op(ctrl, channel); |
| 2002 | write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, |
| 2003 | read32(DEFAULT_MCHBAR + 0x4020 + |
| 2004 | 0x400 * channel) | 0x200000); |
| 2005 | } |
| 2006 | |
| 2007 | /* refresh disable */ |
| 2008 | write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); |
| 2009 | FOR_ALL_POPULATED_CHANNELS { |
| 2010 | write_op(ctrl, channel); |
| 2011 | } |
| 2012 | |
| 2013 | /* enable write leveling on all ranks |
| 2014 | * disable all DQ outputs |
| 2015 | * only NOP is allowed in this mode */ |
| 2016 | FOR_ALL_CHANNELS |
| 2017 | FOR_ALL_POPULATED_RANKS |
| 2018 | write_mrreg(ctrl, channel, slotrank, 1, |
| 2019 | make_mr1(ctrl, slotrank, channel) | 0x1080); |
| 2020 | |
| 2021 | write32(DEFAULT_MCHBAR + 0x3400, 0x108052); |
| 2022 | |
| 2023 | toggle_io_reset(); |
| 2024 | |
| 2025 | /* set any valid value for timB, it gets corrected later */ |
| 2026 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2027 | err = discover_timB(ctrl, channel, slotrank); |
| 2028 | if (err) |
| 2029 | return err; |
| 2030 | } |
| 2031 | |
| 2032 | /* disable write leveling on all ranks */ |
| 2033 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 2034 | write_mrreg(ctrl, channel, |
| 2035 | slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
| 2036 | |
| 2037 | write32(DEFAULT_MCHBAR + 0x3400, 0); |
| 2038 | |
| 2039 | FOR_ALL_POPULATED_CHANNELS |
| 2040 | wait_428c(channel); |
| 2041 | |
| 2042 | /* refresh enable */ |
| 2043 | write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8); |
| 2044 | |
| 2045 | FOR_ALL_POPULATED_CHANNELS { |
| 2046 | write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, |
| 2047 | ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 + |
| 2048 | 0x400 * channel)); |
| 2049 | read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel); |
| 2050 | wait_428c(channel); |
| 2051 | |
| 2052 | /* DRAM command ZQCS */ |
| 2053 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); |
| 2054 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); |
| 2055 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000); |
| 2056 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); |
| 2057 | |
| 2058 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); |
| 2059 | wait_428c(channel); |
| 2060 | } |
| 2061 | |
| 2062 | toggle_io_reset(); |
| 2063 | |
| 2064 | printram("CPE\n"); |
| 2065 | precharge(ctrl); |
| 2066 | printram("CPF\n"); |
| 2067 | |
| 2068 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2069 | read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); |
| 2070 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, |
| 2071 | 0); |
| 2072 | } |
| 2073 | |
| 2074 | FOR_ALL_POPULATED_CHANNELS { |
| 2075 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
| 2076 | write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); |
| 2077 | } |
| 2078 | |
| 2079 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2080 | err = discover_timC(ctrl, channel, slotrank); |
| 2081 | if (err) |
| 2082 | return err; |
| 2083 | } |
| 2084 | |
| 2085 | FOR_ALL_POPULATED_CHANNELS |
| 2086 | program_timings(ctrl, channel); |
| 2087 | |
| 2088 | /* measure and adjust timB timings */ |
| 2089 | adjust_high_timB(ctrl); |
| 2090 | |
| 2091 | FOR_ALL_POPULATED_CHANNELS |
| 2092 | program_timings(ctrl, channel); |
| 2093 | |
| 2094 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2095 | read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); |
| 2096 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, |
| 2097 | 0); |
| 2098 | } |
| 2099 | return 0; |
| 2100 | } |
| 2101 | |
| 2102 | static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) |
| 2103 | { |
| 2104 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2105 | int timC_delta; |
| 2106 | int lanes_ok = 0; |
| 2107 | int ctr = 0; |
| 2108 | int lane; |
| 2109 | |
| 2110 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2111 | FOR_ALL_LANES { |
| 2112 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2113 | saved_rt.lanes[lane].timC + timC_delta; |
| 2114 | } |
| 2115 | program_timings(ctrl, channel); |
| 2116 | FOR_ALL_LANES { |
| 2117 | write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0); |
| 2118 | } |
| 2119 | |
| 2120 | write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); |
| 2121 | |
| 2122 | wait_428c(channel); |
| 2123 | /* DRAM command ACT */ |
| 2124 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); |
| 2125 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 2126 | ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) |
| 2127 | | 8 | (ctrl->tRCD << 16)); |
| 2128 | |
| 2129 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2130 | (slotrank << 24) | ctr | 0x60000); |
| 2131 | |
| 2132 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); |
| 2133 | /* DRAM command WR */ |
| 2134 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); |
| 2135 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 2136 | 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16)); |
| 2137 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 2138 | (slotrank << 24)); |
| 2139 | write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd); |
| 2140 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42); |
| 2141 | |
| 2142 | /* DRAM command RD */ |
| 2143 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); |
| 2144 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 2145 | 0x4001020 | (max(ctrl->tRTP, 8) << 16)); |
| 2146 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 2147 | (slotrank << 24)); |
| 2148 | write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd); |
| 2149 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42); |
| 2150 | |
| 2151 | /* DRAM command PRE */ |
| 2152 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); |
| 2153 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001); |
| 2154 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 2155 | (slotrank << 24) | 0x60400); |
| 2156 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240); |
| 2157 | |
| 2158 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); |
| 2159 | wait_428c(channel); |
| 2160 | FOR_ALL_LANES { |
| 2161 | u32 r32 = |
| 2162 | read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + |
| 2163 | 0x400 * channel); |
| 2164 | |
| 2165 | if (r32 == 0) |
| 2166 | lanes_ok |= 1 << lane; |
| 2167 | } |
| 2168 | ctr++; |
| 2169 | if (lanes_ok == ((1 << NUM_LANES) - 1)) |
| 2170 | break; |
| 2171 | } |
| 2172 | |
| 2173 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2174 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2175 | return lanes_ok != ((1 << NUM_LANES) - 1); |
| 2176 | } |
| 2177 | |
| 2178 | #include "raminit_patterns.h" |
| 2179 | |
| 2180 | static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno) |
| 2181 | { |
| 2182 | unsigned i, j; |
| 2183 | unsigned channel_offset = |
| 2184 | get_precedening_channels(ctrl, channel) * 0x40; |
| 2185 | unsigned channel_step = 0x40 * num_of_channels(ctrl); |
| 2186 | |
| 2187 | if (patno) { |
| 2188 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2189 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2190 | for (i = 0; i < 32; i++) { |
| 2191 | for (j = 0; j < 16; j++) { |
| 2192 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
| 2193 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2194 | val = ~val; |
| 2195 | write32((void *)(0x04000000 + channel_offset + i * channel_step + |
| 2196 | j * 4), val); |
| 2197 | } |
| 2198 | } |
| 2199 | |
| 2200 | } else { |
| 2201 | for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) { |
| 2202 | for (j = 0; j < 16; j++) |
| 2203 | write32((void *)(0x04000000 + channel_offset + i * channel_step + |
| 2204 | j * 4), pattern[i][j]); |
| 2205 | } |
| 2206 | sfence(); |
| 2207 | } |
| 2208 | } |
| 2209 | |
| 2210 | static void reprogram_320c(ramctr_timing * ctrl) |
| 2211 | { |
| 2212 | int channel, slotrank; |
| 2213 | |
| 2214 | FOR_ALL_POPULATED_CHANNELS { |
| 2215 | wait_428c(channel); |
| 2216 | |
| 2217 | /* choose an existing rank. */ |
| 2218 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2219 | |
| 2220 | /* DRAM command ZQCS */ |
| 2221 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); |
| 2222 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); |
| 2223 | |
| 2224 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2225 | (slotrank << 24) | 0x60000); |
| 2226 | |
| 2227 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); |
| 2228 | |
| 2229 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); |
| 2230 | wait_428c(channel); |
| 2231 | write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, |
| 2232 | read32(DEFAULT_MCHBAR + 0x4020 + |
| 2233 | 0x400 * channel) | 0x200000); |
| 2234 | } |
| 2235 | |
| 2236 | /* refresh disable */ |
| 2237 | write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); |
| 2238 | FOR_ALL_POPULATED_CHANNELS { |
| 2239 | wait_428c(channel); |
| 2240 | |
| 2241 | /* choose an existing rank. */ |
| 2242 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2243 | |
| 2244 | /* DRAM command ZQCS */ |
| 2245 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); |
| 2246 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); |
| 2247 | |
| 2248 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2249 | (slotrank << 24) | 0x60000); |
| 2250 | |
| 2251 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); |
| 2252 | |
| 2253 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); |
| 2254 | wait_428c(channel); |
| 2255 | } |
| 2256 | |
| 2257 | /* jedec reset */ |
| 2258 | dram_jedecreset(ctrl); |
| 2259 | /* mrs commands. */ |
| 2260 | dram_mrscommands(ctrl); |
| 2261 | |
| 2262 | toggle_io_reset(); |
| 2263 | } |
| 2264 | |
| 2265 | #define MIN_C320C_LEN 13 |
| 2266 | |
| 2267 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2268 | { |
| 2269 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2270 | int slotrank; |
| 2271 | int c320c; |
| 2272 | int stat[NUM_SLOTRANKS][256]; |
| 2273 | int delta = 0; |
| 2274 | |
| 2275 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2276 | |
| 2277 | FOR_ALL_POPULATED_RANKS { |
| 2278 | saved_timings[channel][slotrank] = |
| 2279 | ctrl->timings[channel][slotrank]; |
| 2280 | } |
| 2281 | |
| 2282 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2283 | |
| 2284 | MCHBAR32(0x4004 + 0x400 * channel) = |
| 2285 | ctrl->tRRD |
| 2286 | | (ctrl->tRTP << 4) |
| 2287 | | (ctrl->tCKE << 8) |
| 2288 | | (ctrl->tWTR << 12) |
| 2289 | | (ctrl->tFAW << 16) |
| 2290 | | (ctrl->tWR << 24) |
| 2291 | | (ctrl->cmd_stretch[channel] << 30); |
| 2292 | |
| 2293 | if (ctrl->cmd_stretch[channel] == 2) |
| 2294 | delta = 2; |
| 2295 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2296 | delta = 4; |
| 2297 | |
| 2298 | FOR_ALL_POPULATED_RANKS { |
| 2299 | ctrl->timings[channel][slotrank].val_4024 -= delta; |
| 2300 | } |
| 2301 | |
| 2302 | for (c320c = -127; c320c <= 127; c320c++) { |
| 2303 | FOR_ALL_POPULATED_RANKS { |
| 2304 | ctrl->timings[channel][slotrank].val_320c = c320c; |
| 2305 | } |
| 2306 | program_timings(ctrl, channel); |
| 2307 | reprogram_320c(ctrl); |
| 2308 | FOR_ALL_POPULATED_RANKS { |
| 2309 | stat[slotrank][c320c + 127] = |
| 2310 | test_320c(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2311 | } |
| 2312 | } |
| 2313 | FOR_ALL_POPULATED_RANKS { |
| 2314 | struct run rn = |
| 2315 | get_longest_zero_run(stat[slotrank], 255); |
| 2316 | ctrl->timings[channel][slotrank].val_320c = |
| 2317 | rn.middle - 127; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2318 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2319 | channel, slotrank, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2320 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2321 | FOR_ALL_POPULATED_RANKS { |
| 2322 | ctrl->timings[channel][slotrank] = |
| 2323 | saved_timings[channel][slotrank]; |
| 2324 | } |
| 2325 | return MAKE_ERR; |
| 2326 | } |
| 2327 | } |
| 2328 | |
| 2329 | return 0; |
| 2330 | } |
| 2331 | |
| 2332 | /* Adjust CMD phase shift and try multiple command rates. |
| 2333 | * A command rate of 2T doubles the time needed for address and |
| 2334 | * command decode. */ |
| 2335 | int command_training(ramctr_timing *ctrl) |
| 2336 | { |
| 2337 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2338 | |
| 2339 | FOR_ALL_POPULATED_CHANNELS { |
| 2340 | fill_pattern5(ctrl, channel, 0); |
| 2341 | write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); |
| 2342 | } |
| 2343 | |
| 2344 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2345 | int cmdrate, err; |
| 2346 | |
| 2347 | /* |
| 2348 | * Dual DIMM per channel: |
| 2349 | * Issue: While c320c discovery seems to succeed raminit |
| 2350 | * will fail in write training. |
| 2351 | * Workaround: Skip 1T in dual DIMM mode, that's only |
| 2352 | * supported by a few DIMMs. |
| 2353 | * TODO: How to detect "1T" DIMMs ? |
| 2354 | * |
| 2355 | * Single DIMM per channel: |
| 2356 | * Try command rate 1T and 2T |
| 2357 | */ |
| 2358 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
| 2359 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame^] | 2360 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2361 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2362 | |
| 2363 | if (!err) |
| 2364 | break; |
| 2365 | } |
| 2366 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2367 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2368 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2369 | return err; |
| 2370 | } |
| 2371 | |
| 2372 | printram("Using CMD rate %uT on channel %u\n", |
| 2373 | cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2374 | } |
| 2375 | |
| 2376 | FOR_ALL_POPULATED_CHANNELS |
| 2377 | program_timings(ctrl, channel); |
| 2378 | |
| 2379 | reprogram_320c(ctrl); |
| 2380 | return 0; |
| 2381 | } |
| 2382 | |
| 2383 | |
| 2384 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, |
| 2385 | int *edges) |
| 2386 | { |
| 2387 | int edge; |
| 2388 | int statistics[NUM_LANES][MAX_EDGE_TIMING + 1]; |
| 2389 | int lane; |
| 2390 | |
| 2391 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2392 | FOR_ALL_LANES { |
| 2393 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2394 | edge; |
| 2395 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2396 | edge; |
| 2397 | } |
| 2398 | program_timings(ctrl, channel); |
| 2399 | |
| 2400 | FOR_ALL_LANES { |
| 2401 | write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + |
| 2402 | 4 * lane, 0); |
| 2403 | read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + |
| 2404 | 0x4140); |
| 2405 | } |
| 2406 | |
| 2407 | wait_428c(channel); |
| 2408 | /* DRAM command MRS |
| 2409 | * write MR3 MPR enable |
| 2410 | * in this mode only RD and RDA are allowed |
| 2411 | * all reads return a predefined pattern */ |
| 2412 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); |
| 2413 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 2414 | (0xc01 | (ctrl->tMOD << 16))); |
| 2415 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2416 | (slotrank << 24) | 0x360004); |
| 2417 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 2418 | |
| 2419 | /* DRAM command RD */ |
| 2420 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); |
| 2421 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4); |
| 2422 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 2423 | (slotrank << 24)); |
| 2424 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 2425 | |
| 2426 | /* DRAM command RD */ |
| 2427 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); |
| 2428 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 2429 | 0x1001 | ((ctrl->CAS + 8) << 16)); |
| 2430 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 2431 | (slotrank << 24) | 0x60000); |
| 2432 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 2433 | |
| 2434 | /* DRAM command MRS |
| 2435 | * MR3 disable MPR */ |
| 2436 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); |
| 2437 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 2438 | (0xc01 | (ctrl->tMOD << 16))); |
| 2439 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 2440 | (slotrank << 24) | 0x360000); |
| 2441 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 2442 | |
| 2443 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); |
| 2444 | |
| 2445 | wait_428c(channel); |
| 2446 | |
| 2447 | FOR_ALL_LANES { |
| 2448 | statistics[lane][edge] = |
| 2449 | read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + |
| 2450 | lane * 4); |
| 2451 | } |
| 2452 | } |
| 2453 | FOR_ALL_LANES { |
| 2454 | struct run rn = |
| 2455 | get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); |
| 2456 | edges[lane] = rn.middle; |
| 2457 | if (rn.all) { |
| 2458 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", |
| 2459 | channel, slotrank, lane); |
| 2460 | return MAKE_ERR; |
| 2461 | } |
| 2462 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, |
| 2463 | lane, edges[lane]); |
| 2464 | } |
| 2465 | return 0; |
| 2466 | } |
| 2467 | |
| 2468 | int discover_edges(ramctr_timing *ctrl) |
| 2469 | { |
| 2470 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2471 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2472 | int channel, slotrank, lane; |
| 2473 | int err; |
| 2474 | |
| 2475 | write32(DEFAULT_MCHBAR + 0x3400, 0); |
| 2476 | |
| 2477 | toggle_io_reset(); |
| 2478 | |
| 2479 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
| 2480 | write32(DEFAULT_MCHBAR + 4 * lane + |
| 2481 | 0x400 * channel + 0x4080, 0); |
| 2482 | } |
| 2483 | |
| 2484 | FOR_ALL_POPULATED_CHANNELS { |
| 2485 | fill_pattern0(ctrl, channel, 0, 0); |
| 2486 | write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); |
| 2487 | FOR_ALL_LANES { |
| 2488 | read32(DEFAULT_MCHBAR + 0x400 * channel + |
| 2489 | lane * 4 + 0x4140); |
| 2490 | } |
| 2491 | |
| 2492 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2493 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2494 | 16; |
| 2495 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2496 | 16; |
| 2497 | } |
| 2498 | |
| 2499 | program_timings(ctrl, channel); |
| 2500 | |
| 2501 | FOR_ALL_POPULATED_RANKS { |
| 2502 | wait_428c(channel); |
| 2503 | |
| 2504 | /* DRAM command MRS |
| 2505 | * MR3 enable MPR |
| 2506 | * write MR3 MPR enable |
| 2507 | * in this mode only RD and RDA are allowed |
| 2508 | * all reads return a predefined pattern */ |
| 2509 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, |
| 2510 | 0x1f000); |
| 2511 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 2512 | 0xc01 | (ctrl->tMOD << 16)); |
| 2513 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2514 | (slotrank << 24) | 0x360004); |
| 2515 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 2516 | |
| 2517 | /* DRAM command RD */ |
| 2518 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, |
| 2519 | 0x1f105); |
| 2520 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 2521 | 0x4041003); |
| 2522 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 2523 | (slotrank << 24) | 0); |
| 2524 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 2525 | |
| 2526 | /* DRAM command RD */ |
| 2527 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, |
| 2528 | 0x1f105); |
| 2529 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 2530 | 0x1001 | ((ctrl->CAS + 8) << 16)); |
| 2531 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 2532 | (slotrank << 24) | 0x60000); |
| 2533 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 2534 | |
| 2535 | /* DRAM command MRS |
| 2536 | * MR3 disable MPR */ |
| 2537 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, |
| 2538 | 0x1f000); |
| 2539 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 2540 | 0xc01 | (ctrl->tMOD << 16)); |
| 2541 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 2542 | (slotrank << 24) | 0x360000); |
| 2543 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 2544 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, |
| 2545 | 0xc0001); |
| 2546 | |
| 2547 | wait_428c(channel); |
| 2548 | } |
| 2549 | |
| 2550 | /* XXX: check any measured value ? */ |
| 2551 | |
| 2552 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2553 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2554 | 48; |
| 2555 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2556 | 48; |
| 2557 | } |
| 2558 | |
| 2559 | program_timings(ctrl, channel); |
| 2560 | |
| 2561 | FOR_ALL_POPULATED_RANKS { |
| 2562 | wait_428c(channel); |
| 2563 | |
| 2564 | /* DRAM command MRS |
| 2565 | * MR3 enable MPR |
| 2566 | * write MR3 MPR enable |
| 2567 | * in this mode only RD and RDA are allowed |
| 2568 | * all reads return a predefined pattern */ |
| 2569 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, |
| 2570 | 0x1f000); |
| 2571 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 2572 | 0xc01 | (ctrl->tMOD << 16)); |
| 2573 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2574 | (slotrank << 24) | 0x360004); |
| 2575 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); |
| 2576 | |
| 2577 | /* DRAM command RD */ |
| 2578 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, |
| 2579 | 0x1f105); |
| 2580 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 2581 | 0x4041003); |
| 2582 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 2583 | (slotrank << 24) | 0); |
| 2584 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); |
| 2585 | |
| 2586 | /* DRAM command RD */ |
| 2587 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, |
| 2588 | 0x1f105); |
| 2589 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 2590 | 0x1001 | ((ctrl->CAS + 8) << 16)); |
| 2591 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 2592 | (slotrank << 24) | 0x60000); |
| 2593 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); |
| 2594 | |
| 2595 | /* DRAM command MRS |
| 2596 | * MR3 disable MPR */ |
| 2597 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, |
| 2598 | 0x1f000); |
| 2599 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 2600 | 0xc01 | (ctrl->tMOD << 16)); |
| 2601 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 2602 | (slotrank << 24) | 0x360000); |
| 2603 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 2604 | |
| 2605 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, |
| 2606 | 0xc0001); |
| 2607 | wait_428c(channel); |
| 2608 | } |
| 2609 | |
| 2610 | /* XXX: check any measured value ? */ |
| 2611 | |
| 2612 | FOR_ALL_LANES { |
| 2613 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + |
| 2614 | lane * 4, |
| 2615 | ~read32(DEFAULT_MCHBAR + 0x4040 + |
| 2616 | 0x400 * channel + lane * 4) & 0xff); |
| 2617 | } |
| 2618 | |
| 2619 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
| 2620 | write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); |
| 2621 | } |
| 2622 | |
| 2623 | /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ |
| 2624 | write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); |
| 2625 | printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); |
| 2626 | |
| 2627 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2628 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2629 | falling_edges[channel][slotrank]); |
| 2630 | if (err) |
| 2631 | return err; |
| 2632 | } |
| 2633 | |
| 2634 | write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); |
| 2635 | printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); |
| 2636 | |
| 2637 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2638 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2639 | rising_edges[channel][slotrank]); |
| 2640 | if (err) |
| 2641 | return err; |
| 2642 | } |
| 2643 | |
| 2644 | write32(DEFAULT_MCHBAR + 0x4eb0, 0); |
| 2645 | |
| 2646 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2647 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2648 | falling_edges[channel][slotrank][lane]; |
| 2649 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2650 | rising_edges[channel][slotrank][lane]; |
| 2651 | } |
| 2652 | |
| 2653 | FOR_ALL_POPULATED_CHANNELS { |
| 2654 | program_timings(ctrl, channel); |
| 2655 | } |
| 2656 | |
| 2657 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2658 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, |
| 2659 | 0); |
| 2660 | } |
| 2661 | return 0; |
| 2662 | } |
| 2663 | |
| 2664 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, |
| 2665 | int slotrank, int *edges) |
| 2666 | { |
| 2667 | int edge; |
| 2668 | u32 raw_statistics[MAX_EDGE_TIMING + 1]; |
| 2669 | int statistics[MAX_EDGE_TIMING + 1]; |
| 2670 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2671 | int lane, i; |
| 2672 | int lower[NUM_LANES]; |
| 2673 | int upper[NUM_LANES]; |
| 2674 | int pat; |
| 2675 | |
| 2676 | FOR_ALL_LANES { |
| 2677 | lower[lane] = 0; |
| 2678 | upper[lane] = MAX_EDGE_TIMING; |
| 2679 | } |
| 2680 | |
| 2681 | for (i = 0; i < 3; i++) { |
| 2682 | write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel, |
| 2683 | reg3000b24[i] << 24); |
| 2684 | printram("[%x] = 0x%08x\n", |
| 2685 | 0x3000 + 0x100 * channel, reg3000b24[i] << 24); |
| 2686 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2687 | fill_pattern5(ctrl, channel, pat); |
| 2688 | write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); |
| 2689 | printram("using pattern %d\n", pat); |
| 2690 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2691 | FOR_ALL_LANES { |
| 2692 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2693 | rising = edge; |
| 2694 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2695 | falling = edge; |
| 2696 | } |
| 2697 | program_timings(ctrl, channel); |
| 2698 | |
| 2699 | FOR_ALL_LANES { |
| 2700 | write32(DEFAULT_MCHBAR + 0x4340 + |
| 2701 | 0x400 * channel + 4 * lane, 0); |
| 2702 | read32(DEFAULT_MCHBAR + 0x400 * channel + |
| 2703 | 4 * lane + 0x4140); |
| 2704 | } |
| 2705 | wait_428c(channel); |
| 2706 | |
| 2707 | /* DRAM command ACT */ |
| 2708 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, |
| 2709 | 0x1f006); |
| 2710 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 2711 | 0x4 | (ctrl->tRCD << 16) |
| 2712 | | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << |
| 2713 | 10)); |
| 2714 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2715 | (slotrank << 24) | 0x60000); |
| 2716 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, |
| 2717 | 0x240); |
| 2718 | |
| 2719 | /* DRAM command WR */ |
| 2720 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, |
| 2721 | 0x1f201); |
| 2722 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 2723 | 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << |
| 2724 | 16)); |
| 2725 | write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, |
| 2726 | (slotrank << 24)); |
| 2727 | write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, |
| 2728 | 0x242); |
| 2729 | |
| 2730 | /* DRAM command RD */ |
| 2731 | write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, |
| 2732 | 0x1f105); |
| 2733 | write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, |
| 2734 | 0x4005020 | (max(ctrl->tRTP, 8) << 16)); |
| 2735 | write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, |
| 2736 | (slotrank << 24)); |
| 2737 | write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, |
| 2738 | 0x242); |
| 2739 | |
| 2740 | /* DRAM command PRE */ |
| 2741 | write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, |
| 2742 | 0x1f002); |
| 2743 | write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, |
| 2744 | 0xc01 | (ctrl->tRP << 16)); |
| 2745 | write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, |
| 2746 | (slotrank << 24) | 0x60400); |
| 2747 | write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); |
| 2748 | |
| 2749 | write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, |
| 2750 | 0xc0001); |
| 2751 | wait_428c(channel); |
| 2752 | FOR_ALL_LANES { |
| 2753 | read32(DEFAULT_MCHBAR + 0x4340 + |
| 2754 | 0x400 * channel + lane * 4); |
| 2755 | } |
| 2756 | |
| 2757 | raw_statistics[edge] = |
| 2758 | MCHBAR32(0x436c + 0x400 * channel); |
| 2759 | } |
| 2760 | FOR_ALL_LANES { |
| 2761 | struct run rn; |
| 2762 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
| 2763 | statistics[edge] = |
| 2764 | ! !(raw_statistics[edge] & (1 << lane)); |
| 2765 | rn = get_longest_zero_run(statistics, |
| 2766 | MAX_EDGE_TIMING + 1); |
| 2767 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", |
| 2768 | channel, slotrank, i, rn.start, rn.middle, |
| 2769 | rn.end, rn.start + ctrl->edge_offset[i], |
| 2770 | rn.end - ctrl->edge_offset[i]); |
| 2771 | lower[lane] = |
| 2772 | max(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2773 | upper[lane] = |
| 2774 | min(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2775 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2776 | if (rn.all || (lower[lane] > upper[lane])) { |
| 2777 | printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", |
| 2778 | channel, slotrank, lane); |
| 2779 | return MAKE_ERR; |
| 2780 | } |
| 2781 | } |
| 2782 | } |
| 2783 | } |
| 2784 | |
| 2785 | write32(DEFAULT_MCHBAR + 0x3000, 0); |
| 2786 | printram("CPA\n"); |
| 2787 | return 0; |
| 2788 | } |
| 2789 | |
| 2790 | int discover_edges_write(ramctr_timing *ctrl) |
| 2791 | { |
| 2792 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2793 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2794 | int channel, slotrank, lane; |
| 2795 | int err; |
| 2796 | |
| 2797 | /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ |
| 2798 | write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); |
| 2799 | printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); |
| 2800 | |
| 2801 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2802 | err = discover_edges_write_real(ctrl, channel, slotrank, |
| 2803 | falling_edges[channel][slotrank]); |
| 2804 | if (err) |
| 2805 | return err; |
| 2806 | } |
| 2807 | |
| 2808 | write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); |
| 2809 | printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); |
| 2810 | |
| 2811 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2812 | err = discover_edges_write_real(ctrl, channel, slotrank, |
| 2813 | rising_edges[channel][slotrank]); |
| 2814 | if (err) |
| 2815 | return err; |
| 2816 | } |
| 2817 | |
| 2818 | write32(DEFAULT_MCHBAR + 0x4eb0, 0); |
| 2819 | |
| 2820 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2821 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2822 | falling_edges[channel][slotrank][lane]; |
| 2823 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2824 | rising_edges[channel][slotrank][lane]; |
| 2825 | } |
| 2826 | |
| 2827 | FOR_ALL_POPULATED_CHANNELS |
| 2828 | program_timings(ctrl, channel); |
| 2829 | |
| 2830 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2831 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, |
| 2832 | 0); |
| 2833 | } |
| 2834 | return 0; |
| 2835 | } |
| 2836 | |
| 2837 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2838 | { |
| 2839 | wait_428c(channel); |
| 2840 | /* DRAM command ACT */ |
| 2841 | write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); |
| 2842 | write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, |
| 2843 | (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) |
| 2844 | << 10) | (ctrl->tRCD << 16) | 4); |
| 2845 | write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, |
| 2846 | (slotrank << 24) | 0x60000); |
| 2847 | write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); |
| 2848 | |
| 2849 | /* DRAM command WR */ |
| 2850 | write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); |
| 2851 | write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, |
| 2852 | 0x80011e0 | |
| 2853 | ((ctrl->tWTR + ctrl->CWL + 8) << 16)); |
| 2854 | write32(DEFAULT_MCHBAR + 0x4204 + |
| 2855 | 0x400 * channel, (slotrank << 24)); |
| 2856 | write32(DEFAULT_MCHBAR + 0x4214 + |
| 2857 | 0x400 * channel, 0x242); |
| 2858 | |
| 2859 | /* DRAM command RD */ |
| 2860 | write32(DEFAULT_MCHBAR + 0x4228 + |
| 2861 | 0x400 * channel, 0x1f105); |
| 2862 | write32(DEFAULT_MCHBAR + 0x4238 + |
| 2863 | 0x400 * channel, |
| 2864 | 0x40011e0 | (max(ctrl->tRTP, 8) << 16)); |
| 2865 | write32(DEFAULT_MCHBAR + 0x4208 + |
| 2866 | 0x400 * channel, (slotrank << 24)); |
| 2867 | write32(DEFAULT_MCHBAR + 0x4218 + |
| 2868 | 0x400 * channel, 0x242); |
| 2869 | |
| 2870 | /* DRAM command PRE */ |
| 2871 | write32(DEFAULT_MCHBAR + 0x422c + |
| 2872 | 0x400 * channel, 0x1f002); |
| 2873 | write32(DEFAULT_MCHBAR + 0x423c + |
| 2874 | 0x400 * channel, |
| 2875 | 0x1001 | (ctrl->tRP << 16)); |
| 2876 | write32(DEFAULT_MCHBAR + 0x420c + |
| 2877 | 0x400 * channel, |
| 2878 | (slotrank << 24) | 0x60400); |
| 2879 | write32(DEFAULT_MCHBAR + 0x421c + |
| 2880 | 0x400 * channel, 0); |
| 2881 | |
| 2882 | write32(DEFAULT_MCHBAR + 0x4284 + |
| 2883 | 0x400 * channel, 0xc0001); |
| 2884 | wait_428c(channel); |
| 2885 | } |
| 2886 | |
| 2887 | int discover_timC_write(ramctr_timing *ctrl) |
| 2888 | { |
| 2889 | const u8 rege3c_b24[3] = { 0, 0xf, 0x2f }; |
| 2890 | int i, pat; |
| 2891 | |
| 2892 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2893 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2894 | int channel, slotrank, lane; |
| 2895 | |
| 2896 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2897 | lower[channel][slotrank][lane] = 0; |
| 2898 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2899 | } |
| 2900 | |
| 2901 | write32(DEFAULT_MCHBAR + 0x4ea8, 1); |
| 2902 | printram("discover timC write:\n"); |
| 2903 | |
| 2904 | for (i = 0; i < 3; i++) |
| 2905 | FOR_ALL_POPULATED_CHANNELS { |
| 2906 | write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100), |
| 2907 | (rege3c_b24[i] << 24) |
| 2908 | | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100)) |
| 2909 | & ~0x3f000000)); |
| 2910 | udelay(2); |
| 2911 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2912 | FOR_ALL_POPULATED_RANKS { |
| 2913 | int timC; |
| 2914 | u32 raw_statistics[MAX_TIMC + 1]; |
| 2915 | int statistics[MAX_TIMC + 1]; |
| 2916 | |
| 2917 | /* Make sure rn.start < rn.end */ |
| 2918 | statistics[MAX_TIMC] = 1; |
| 2919 | |
| 2920 | fill_pattern5(ctrl, channel, pat); |
| 2921 | write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); |
| 2922 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2923 | FOR_ALL_LANES |
| 2924 | ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
| 2925 | program_timings(ctrl, channel); |
| 2926 | |
| 2927 | test_timC_write (ctrl, channel, slotrank); |
| 2928 | |
| 2929 | raw_statistics[timC] = |
| 2930 | MCHBAR32(0x436c + 0x400 * channel); |
| 2931 | } |
| 2932 | FOR_ALL_LANES { |
| 2933 | struct run rn; |
| 2934 | for (timC = 0; timC < MAX_TIMC; timC++) |
| 2935 | statistics[timC] = |
| 2936 | !!(raw_statistics[timC] & |
| 2937 | (1 << lane)); |
| 2938 | |
| 2939 | rn = get_longest_zero_run(statistics, |
| 2940 | MAX_TIMC + 1); |
| 2941 | if (rn.all) { |
| 2942 | printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", |
| 2943 | channel, slotrank, lane); |
| 2944 | return MAKE_ERR; |
| 2945 | } |
| 2946 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", |
| 2947 | channel, slotrank, i, rn.start, |
| 2948 | rn.middle, rn.end, |
| 2949 | rn.start + ctrl->timC_offset[i], |
| 2950 | rn.end - ctrl->timC_offset[i]); |
| 2951 | lower[channel][slotrank][lane] = |
| 2952 | max(rn.start + ctrl->timC_offset[i], |
| 2953 | lower[channel][slotrank][lane]); |
| 2954 | upper[channel][slotrank][lane] = |
| 2955 | min(rn.end - ctrl->timC_offset[i], |
| 2956 | upper[channel][slotrank][lane]); |
| 2957 | |
| 2958 | } |
| 2959 | } |
| 2960 | } |
| 2961 | } |
| 2962 | |
| 2963 | FOR_ALL_CHANNELS { |
| 2964 | write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c, |
| 2965 | 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) & |
| 2966 | ~0x3f000000)); |
| 2967 | udelay(2); |
| 2968 | } |
| 2969 | |
| 2970 | write32(DEFAULT_MCHBAR + 0x4ea8, 0); |
| 2971 | |
| 2972 | printram("CPB\n"); |
| 2973 | |
| 2974 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2975 | printram("timC %d, %d, %d: %x\n", channel, |
| 2976 | slotrank, lane, |
| 2977 | (lower[channel][slotrank][lane] + |
| 2978 | upper[channel][slotrank][lane]) / 2); |
| 2979 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2980 | (lower[channel][slotrank][lane] + |
| 2981 | upper[channel][slotrank][lane]) / 2; |
| 2982 | } |
| 2983 | FOR_ALL_POPULATED_CHANNELS { |
| 2984 | program_timings(ctrl, channel); |
| 2985 | } |
| 2986 | return 0; |
| 2987 | } |
| 2988 | |
| 2989 | void normalize_training(ramctr_timing * ctrl) |
| 2990 | { |
| 2991 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2992 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2993 | |
| 2994 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2995 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2996 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2997 | FOR_ALL_LANES mat = |
| 2998 | max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2999 | printram("normalize %d, %d, %d: mat %d\n", |
| 3000 | channel, slotrank, lane, mat); |
| 3001 | |
| 3002 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; |
| 3003 | printram("normalize %d, %d, %d: delta %d\n", |
| 3004 | channel, slotrank, lane, delta); |
| 3005 | |
| 3006 | ctrl->timings[channel][slotrank].val_4024 += delta; |
| 3007 | ctrl->timings[channel][slotrank].val_4028 += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3008 | } |
| 3009 | |
| 3010 | FOR_ALL_POPULATED_CHANNELS { |
| 3011 | program_timings(ctrl, channel); |
| 3012 | } |
| 3013 | } |
| 3014 | |
| 3015 | void write_controller_mr(ramctr_timing * ctrl) |
| 3016 | { |
| 3017 | int channel, slotrank; |
| 3018 | |
| 3019 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 3020 | write32(DEFAULT_MCHBAR + 0x0004 + (channel << 8) + |
| 3021 | lane_registers[slotrank], make_mr0(ctrl, slotrank)); |
| 3022 | write32(DEFAULT_MCHBAR + 0x0008 + (channel << 8) + |
| 3023 | lane_registers[slotrank], |
| 3024 | make_mr1(ctrl, slotrank, channel)); |
| 3025 | } |
| 3026 | } |
| 3027 | |
| 3028 | int channel_test(ramctr_timing *ctrl) |
| 3029 | { |
| 3030 | int channel, slotrank, lane; |
| 3031 | |
| 3032 | slotrank = 0; |
| 3033 | FOR_ALL_POPULATED_CHANNELS |
| 3034 | if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { |
| 3035 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", |
| 3036 | channel); |
| 3037 | return MAKE_ERR; |
| 3038 | } |
| 3039 | FOR_ALL_POPULATED_CHANNELS { |
| 3040 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
| 3041 | |
| 3042 | write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); |
| 3043 | } |
| 3044 | |
| 3045 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 3046 | FOR_ALL_CHANNELS |
| 3047 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 3048 | FOR_ALL_LANES { |
| 3049 | write32(DEFAULT_MCHBAR + (0x4f40 + 4 * lane), 0); |
| 3050 | write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0); |
| 3051 | } |
| 3052 | wait_428c(channel); |
| 3053 | /* DRAM command ACT */ |
| 3054 | write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006); |
| 3055 | write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004); |
| 3056 | write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10), |
| 3057 | 0x00060000 | (slotrank << 24)); |
| 3058 | write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244); |
| 3059 | /* DRAM command WR */ |
| 3060 | write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201); |
| 3061 | write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064); |
| 3062 | write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10), |
| 3063 | 0x00000000 | (slotrank << 24)); |
| 3064 | write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242); |
| 3065 | /* DRAM command RD */ |
| 3066 | write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105); |
| 3067 | write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064); |
| 3068 | write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10), |
| 3069 | 0x00000000 | (slotrank << 24)); |
| 3070 | write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242); |
| 3071 | /* DRAM command PRE */ |
| 3072 | write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002); |
| 3073 | write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01); |
| 3074 | write32(DEFAULT_MCHBAR + 0x420c + (channel << 10), |
| 3075 | 0x00060400 | (slotrank << 24)); |
| 3076 | write32(DEFAULT_MCHBAR + 0x421c + (channel << 10), 0x00000240); |
| 3077 | write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); |
| 3078 | wait_428c(channel); |
| 3079 | FOR_ALL_LANES |
| 3080 | if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { |
| 3081 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 3082 | channel, slotrank, lane); |
| 3083 | return MAKE_ERR; |
| 3084 | } |
| 3085 | } |
| 3086 | return 0; |
| 3087 | } |
| 3088 | |
| 3089 | void set_scrambling_seed(ramctr_timing * ctrl) |
| 3090 | { |
| 3091 | int channel; |
| 3092 | |
| 3093 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? |
| 3094 | I don't think so. */ |
| 3095 | static u32 seeds[NUM_CHANNELS][3] = { |
| 3096 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 3097 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 3098 | }; |
| 3099 | FOR_ALL_POPULATED_CHANNELS { |
| 3100 | MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000; |
Arthur Heymans | 6af8aab | 2017-09-26 23:18:14 +0200 | [diff] [blame] | 3101 | MCHBAR32(0x4034 + 0x400 * channel) = seeds[channel][0]; |
| 3102 | MCHBAR32(0x403c + 0x400 * channel) = seeds[channel][1]; |
| 3103 | MCHBAR32(0x4038 + 0x400 * channel) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3104 | } |
| 3105 | } |
| 3106 | |
| 3107 | void set_4f8c(void) |
| 3108 | { |
| 3109 | struct cpuid_result cpures; |
| 3110 | u32 cpu; |
| 3111 | |
| 3112 | cpures = cpuid(1); |
| 3113 | cpu = (cpures.eax); |
| 3114 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
| 3115 | MCHBAR32(0x4f8c) = 0x141D1519; |
| 3116 | } else { |
| 3117 | MCHBAR32(0x4f8c) = 0x551D1519; |
| 3118 | } |
| 3119 | } |
| 3120 | |
| 3121 | void prepare_training(ramctr_timing * ctrl) |
| 3122 | { |
| 3123 | int channel; |
| 3124 | |
| 3125 | FOR_ALL_POPULATED_CHANNELS { |
| 3126 | // Always drive command bus |
| 3127 | MCHBAR32(0x4004 + 0x400 * channel) |= 0x20000000; |
| 3128 | } |
| 3129 | |
| 3130 | udelay(1); |
| 3131 | |
| 3132 | FOR_ALL_POPULATED_CHANNELS { |
| 3133 | wait_428c(channel); |
| 3134 | } |
| 3135 | } |
| 3136 | |
| 3137 | void set_4008c(ramctr_timing * ctrl) |
| 3138 | { |
| 3139 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3140 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3141 | FOR_ALL_POPULATED_CHANNELS { |
| 3142 | u32 b20, b4_8_12; |
| 3143 | int min_320c = 10000; |
| 3144 | int max_320c = -10000; |
| 3145 | |
| 3146 | FOR_ALL_POPULATED_RANKS { |
| 3147 | max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c); |
| 3148 | min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c); |
| 3149 | } |
| 3150 | |
| 3151 | if (max_320c - min_320c > 51) |
| 3152 | b20 = 0; |
| 3153 | else |
| 3154 | b20 = ctrl->ref_card_offset[channel]; |
| 3155 | |
| 3156 | if (ctrl->reg_320c_range_threshold < max_320c - min_320c) |
| 3157 | b4_8_12 = 0x3330; |
| 3158 | else |
| 3159 | b4_8_12 = 0x2220; |
| 3160 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3161 | dram_odt_stretch(ctrl, channel); |
| 3162 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3163 | write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10), |
| 3164 | 0x0a000000 |
| 3165 | | (b20 << 20) |
| 3166 | | ((ctrl->ref_card_offset[channel] + 2) << 16) |
| 3167 | | b4_8_12); |
| 3168 | } |
| 3169 | } |
| 3170 | |
| 3171 | void set_42a0(ramctr_timing * ctrl) |
| 3172 | { |
| 3173 | int channel; |
| 3174 | FOR_ALL_POPULATED_CHANNELS { |
| 3175 | write32(DEFAULT_MCHBAR + (0x42a0 + 0x400 * channel), |
| 3176 | 0x00001000 | ctrl->rankmap[channel]); |
| 3177 | MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK |
| 3178 | } |
| 3179 | } |
| 3180 | |
| 3181 | static int encode_5d10(int ns) |
| 3182 | { |
| 3183 | return (ns + 499) / 500; |
| 3184 | } |
| 3185 | |
| 3186 | /* FIXME: values in this function should be hardware revision-dependent. */ |
| 3187 | void final_registers(ramctr_timing * ctrl) |
| 3188 | { |
| 3189 | int channel; |
| 3190 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 3191 | int t3_ns; |
| 3192 | u32 r32; |
| 3193 | |
| 3194 | write32(DEFAULT_MCHBAR + 0x4cd4, 0x00000046); |
| 3195 | |
| 3196 | write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK |
| 3197 | write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK |
| 3198 | write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740); |
| 3199 | write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK |
| 3200 | write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK |
| 3201 | write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK |
| 3202 | write32(DEFAULT_MCHBAR + 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK |
| 3203 | |
| 3204 | FOR_ALL_CHANNELS { |
| 3205 | switch (ctrl->rankmap[channel]) { |
| 3206 | /* Unpopulated channel. */ |
| 3207 | case 0: |
| 3208 | write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0); |
| 3209 | break; |
| 3210 | /* Only single-ranked dimms. */ |
| 3211 | case 1: |
| 3212 | case 4: |
| 3213 | case 5: |
| 3214 | write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x373131); |
| 3215 | break; |
| 3216 | /* Dual-ranked dimms present. */ |
| 3217 | default: |
| 3218 | write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x9b6ea1); |
| 3219 | break; |
| 3220 | } |
| 3221 | } |
| 3222 | |
| 3223 | write32 (DEFAULT_MCHBAR + 0x5880, 0xca9171e5); |
| 3224 | write32 (DEFAULT_MCHBAR + 0x5888, |
| 3225 | (read32 (DEFAULT_MCHBAR + 0x5888) & ~0xffffff) | 0xe4d5d0); |
| 3226 | write32 (DEFAULT_MCHBAR + 0x58a8, read32 (DEFAULT_MCHBAR + 0x58a8) & ~0x1f); |
| 3227 | write32 (DEFAULT_MCHBAR + 0x4294, |
| 3228 | (read32 (DEFAULT_MCHBAR + 0x4294) & ~0x30000) |
| 3229 | | (1 << 16)); |
| 3230 | write32 (DEFAULT_MCHBAR + 0x4694, |
| 3231 | (read32 (DEFAULT_MCHBAR + 0x4694) & ~0x30000) |
| 3232 | | (1 << 16)); |
| 3233 | |
| 3234 | MCHBAR32(0x5030) |= 1; // OK |
| 3235 | MCHBAR32(0x5030) |= 0x80; // OK |
| 3236 | MCHBAR32(0x5f18) = 0xfa; // OK |
| 3237 | |
| 3238 | /* Find a populated channel. */ |
| 3239 | FOR_ALL_POPULATED_CHANNELS |
| 3240 | break; |
| 3241 | |
| 3242 | t1_cycles = ((read32(DEFAULT_MCHBAR + 0x4290 + channel * 0x400) >> 8) & 0xff); |
| 3243 | r32 = read32(DEFAULT_MCHBAR + 0x5064); |
| 3244 | if (r32 & 0x20000) |
| 3245 | t1_cycles += (r32 & 0xfff); |
| 3246 | t1_cycles += (read32(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4) & 0xfff); |
| 3247 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
| 3248 | if (!(r32 & 0x20000)) |
| 3249 | t1_ns += 500; |
| 3250 | |
| 3251 | t2_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f10) >> 8) & 0xfff); |
| 3252 | if ( read32(DEFAULT_MCHBAR + 0x5f00) & 8 ) |
| 3253 | { |
| 3254 | t3_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f20) >> 8) & 0xfff); |
| 3255 | t3_ns += 10 * (read32(DEFAULT_MCHBAR + 0x5f18) & 0xff); |
| 3256 | } |
| 3257 | else |
| 3258 | { |
| 3259 | t3_ns = 500; |
| 3260 | } |
| 3261 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", |
| 3262 | t1_ns, t2_ns, t3_ns); |
| 3263 | write32 (DEFAULT_MCHBAR + 0x5d10, |
| 3264 | ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) |
| 3265 | | (encode_5d10(t1_ns) << 8) |
| 3266 | | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) |
| 3267 | | (read32(DEFAULT_MCHBAR + 0x5d10) & 0xC0C0C0C0) |
| 3268 | | 0xc); |
| 3269 | } |
| 3270 | |
| 3271 | void restore_timings(ramctr_timing * ctrl) |
| 3272 | { |
| 3273 | int channel, slotrank, lane; |
| 3274 | |
| 3275 | FOR_ALL_POPULATED_CHANNELS |
| 3276 | MCHBAR32(0x4004 + 0x400 * channel) = |
| 3277 | ctrl->tRRD |
| 3278 | | (ctrl->tRTP << 4) |
| 3279 | | (ctrl->tCKE << 8) |
| 3280 | | (ctrl->tWTR << 12) |
| 3281 | | (ctrl->tFAW << 16) |
| 3282 | | (ctrl->tWR << 24) |
| 3283 | | (ctrl->cmd_stretch[channel] << 30); |
| 3284 | |
| 3285 | udelay(1); |
| 3286 | |
| 3287 | FOR_ALL_POPULATED_CHANNELS { |
| 3288 | wait_428c(channel); |
| 3289 | } |
| 3290 | |
| 3291 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 3292 | write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel |
| 3293 | + 4 * lane, 0); |
| 3294 | } |
| 3295 | |
| 3296 | FOR_ALL_POPULATED_CHANNELS |
| 3297 | write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, |
| 3298 | read32(DEFAULT_MCHBAR + 0x4008 + |
| 3299 | 0x400 * channel) | 0x8000000); |
| 3300 | |
| 3301 | FOR_ALL_POPULATED_CHANNELS { |
| 3302 | udelay (1); |
| 3303 | write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, |
| 3304 | read32(DEFAULT_MCHBAR + 0x4020 + |
| 3305 | 0x400 * channel) | 0x200000); |
| 3306 | } |
| 3307 | |
| 3308 | printram("CPE\n"); |
| 3309 | |
| 3310 | write32(DEFAULT_MCHBAR + 0x3400, 0); |
| 3311 | write32(DEFAULT_MCHBAR + 0x4eb0, 0); |
| 3312 | |
| 3313 | printram("CP5b\n"); |
| 3314 | |
| 3315 | FOR_ALL_POPULATED_CHANNELS { |
| 3316 | program_timings(ctrl, channel); |
| 3317 | } |
| 3318 | |
| 3319 | u32 reg, addr; |
| 3320 | |
| 3321 | while (!(MCHBAR32(0x5084) & 0x10000)); |
| 3322 | do { |
| 3323 | reg = MCHBAR32(0x428c); |
| 3324 | } while ((reg & 0x14) == 0); |
| 3325 | |
| 3326 | // Set state of memory controller |
| 3327 | MCHBAR32(0x5030) = 0x116; |
| 3328 | MCHBAR32(0x4ea0) = 0; |
| 3329 | |
| 3330 | // Wait 500us |
| 3331 | udelay(500); |
| 3332 | |
| 3333 | FOR_ALL_CHANNELS { |
| 3334 | // Set valid rank CKE |
| 3335 | reg = 0; |
| 3336 | reg = (reg & ~0xf) | ctrl->rankmap[channel]; |
| 3337 | addr = 0x400 * channel + 0x42a0; |
| 3338 | MCHBAR32(addr) = reg; |
| 3339 | |
| 3340 | // Wait 10ns for ranks to settle |
| 3341 | //udelay(0.01); |
| 3342 | |
| 3343 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3344 | MCHBAR32(addr) = reg; |
| 3345 | |
| 3346 | // Write reset using a NOP |
| 3347 | write_reset(ctrl); |
| 3348 | } |
| 3349 | |
| 3350 | /* mrs commands. */ |
| 3351 | dram_mrscommands(ctrl); |
| 3352 | |
| 3353 | printram("CP5c\n"); |
| 3354 | |
| 3355 | write32(DEFAULT_MCHBAR + 0x3000, 0); |
| 3356 | |
| 3357 | FOR_ALL_CHANNELS { |
| 3358 | write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c, |
| 3359 | 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) & |
| 3360 | ~0x3f000000)); |
| 3361 | udelay(2); |
| 3362 | } |
| 3363 | |
| 3364 | write32(DEFAULT_MCHBAR + 0x4ea8, 0); |
| 3365 | } |