Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> |
| 6 | * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 18 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 19 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 20 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 21 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 22 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 24 | #include <northbridge/intel/sandybridge/chip.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <delay.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 27 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 28 | #include "raminit_native.h" |
| 29 | #include "raminit_common.h" |
| 30 | #include "sandybridge.h" |
| 31 | |
| 32 | /* FIXME: no ECC support. */ |
| 33 | /* FIXME: no support for 3-channel chipsets. */ |
| 34 | |
| 35 | /* |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 36 | * ### IOSAV command queue notes ### |
| 37 | * |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 38 | * Intel provides a command queue of depth four. |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 39 | * Every command is configured by using multiple MCHBAR registers. |
| 40 | * On executing the command queue, you have to specify its depth (number of commands). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 41 | * |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 42 | * The macros for these registers can take some integer parameters, within these bounds: |
| 43 | * channel: [0..1] |
| 44 | * index: [0..3] |
| 45 | * lane: [0..8] |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 46 | * |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 47 | * Note that these ranges are 'closed': both endpoints are included. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 48 | * |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 49 | * |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 50 | * |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 51 | * ### Register description ### |
| 52 | * |
| 53 | * IOSAV_n_SP_CMD_ADDR_ch(channel, index) |
| 54 | * Sub-sequence command addresses. Controls the address, bank address and slotrank signals. |
| 55 | * |
| 56 | * Bitfields: |
| 57 | * [0..15] Row / Column Address. |
| 58 | * [16..18] The result of (10 + [16..18]) is the number of valid row bits. |
| 59 | * Note: Value 1 is not implemented. Not that it really matters, though. |
| 60 | * Value 7 is reserved, as the hardware does not support it. |
| 61 | * [20..22] Bank Address. |
| 62 | * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. |
| 63 | * |
| 64 | * IOSAV_n_ADDR_UPD_ch(channel, index) |
| 65 | * How the address shall be updated after executing the sub-sequence command. |
| 66 | * |
| 67 | * Bitfields: |
| 68 | * [0] Increment CAS/RAS by 1. |
| 69 | * [1] Increment CAS/RAS by 8. |
| 70 | * [2] Increment bank select by 1. |
| 71 | * [3..4] Increment rank select by 1, 2 or 3. |
| 72 | * [5..9] Known as "addr_wrap". Address bits will wrap around the [addr_wrap..0] range. |
| 73 | * [10..11] LFSR update: |
| 74 | * 00: Do not use the LFSR function. |
| 75 | * 01: Undefined, treat as Reserved. |
| 76 | * 10: Apply LFSR on the [addr_wrap..0] bit range. |
| 77 | * 11: Apply LFSR on the [addr_wrap..3] bit range. |
| 78 | * |
| 79 | * [12..15] Update rate. The number of command runs between address updates. For example: |
| 80 | * 0: Update every command run. |
| 81 | * 1: Update every second command run. That is, half of the command rate. |
| 82 | * N: Update after N command runs without updates. |
| 83 | * |
| 84 | * [16..17] LFSR behavior on the deselect cycles (when no sub-seq command is issued): |
| 85 | * 0: No change w.r.t. the last issued command. |
| 86 | * 1: LFSR XORs with address & command (excluding CS), but does not update. |
| 87 | * 2: LFSR XORs with address & command (excluding CS), and updates. |
| 88 | * |
| 89 | * IOSAV_n_SP_CMD_CTL_ch(channel, index) |
| 90 | * Special command control register. Controls the DRAM command signals. |
| 91 | * |
| 92 | * Bitfields: |
| 93 | * [0] !RAS signal. |
| 94 | * [1] !CAS signal. |
| 95 | * [2] !WE signal. |
| 96 | * [4..7] CKE, per rank and channel. |
| 97 | * [8..11] ODT, per rank and channel. |
| 98 | * [12] Chip Select mode control. |
| 99 | * [13..16] Chip select, per rank and channel. It works as follows: |
| 100 | * |
| 101 | * entity CS_BLOCK is |
| 102 | * port ( |
| 103 | * MODE : in std_logic; -- Mode select at [12] |
| 104 | * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value |
| 105 | * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [13..16] |
| 106 | * CS_Q : out std_logic_vector(0 to 3) -- CS signals |
| 107 | * ); |
| 108 | * end entity CS_BLOCK; |
| 109 | * |
| 110 | * architecture RTL of CS_BLOCK is |
| 111 | * begin |
| 112 | * if MODE = '1' then |
| 113 | * CS_Q <= not RANKSEL and CS_CTL; |
| 114 | * else |
| 115 | * CS_Q <= CS_CTL; |
| 116 | * end if; |
| 117 | * end architecture RTL; |
| 118 | * |
| 119 | * [17] Auto Precharge. Only valid when using 10 row bits! |
| 120 | * |
| 121 | * IOSAV_n_SUBSEQ_CTL_ch(channel, index) |
| 122 | * Sub-sequence parameters. Controls repetititons, delays and data orientation. |
| 123 | * |
| 124 | * Bitfields: |
| 125 | * [0..8] Number of repetitions of the sub-sequence command. |
| 126 | * [10..14] Gap, number of clock-cycles to wait before sending the next command. |
| 127 | * [16..24] Number of clock-cycles to idle between sub-sequence commands. |
| 128 | * [26..27] The direction of the data. |
| 129 | * 00: None, does not handle data |
| 130 | * 01: Read |
| 131 | * 10: Write |
| 132 | * 11: Read & Write |
| 133 | * |
| 134 | * IOSAV_n_ADDRESS_LFSR_ch(channel, index) |
| 135 | * 23-bit LFSR state register. It is written into the LFSR when the sub-sequence is loaded, |
| 136 | * and then read back from the LFSR when the sub-sequence is done. |
| 137 | * |
| 138 | * Bitfields: |
| 139 | * [0..22] LFSR state. |
| 140 | * |
| 141 | * IOSAV_SEQ_CTL_ch(channel) |
| 142 | * Control the sequence level in IOSAV: number of sub-sequences, iterations, maintenance... |
| 143 | * |
| 144 | * Bitfields: |
| 145 | * [0..7] Number of full sequence executions. When this field becomes non-zero, then the |
| 146 | * sequence starts running immediately. This value is decremented after completing |
| 147 | * a full sequence iteration. When it is zero, the sequence is done. No decrement |
| 148 | * is done if this field is set to 0xff. This is the "infinite repeat" mode, and |
| 149 | * it is manually aborted by clearing this field. |
| 150 | * |
| 151 | * [8..16] Number of wait cycles after each sequence iteration. This wait's purpose is to |
| 152 | * allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh |
| 153 | * and ZQXS operations can take place. |
| 154 | * |
| 155 | * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. |
| 156 | * [18..19] Number of sub-sequences. The programmed value is the index of the last sub-seq. |
| 157 | * [20] If set, keep refresh disabled until the next sequence execution. |
| 158 | * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! |
| 159 | * |
| 160 | * [22] If set, sequence execution will not prevent refresh. This cannot be set when |
| 161 | * bit [20] is also set, or was set on the previous sequence. This bit exists so |
| 162 | * that the sequence machine can be used as a timer without affecting the memory. |
| 163 | * |
| 164 | * [23] If set, a output pin is asserted on the first detected error. This output can |
| 165 | * be used as a trigger for an oscilloscope or a logic analyzer, which is handy. |
| 166 | * |
| 167 | * IOSAV_DATA_CTL_ch(channel) |
| 168 | * Data-related controls in IOSAV mode. |
| 169 | * |
| 170 | * Bitfields: |
| 171 | * [0..7] WDB (Write Data Buffer) pattern length: [0..7] = (length / 8) - 1; |
| 172 | * [8..15] WDB read pointer. Points at the data used for IOSAV write transactions. |
| 173 | * [16..23] Comparison pointer. Used to compare data from IOSAV read transactions. |
| 174 | * [24] If set, increment pointers only when micro-breakpoint is active. |
| 175 | * |
| 176 | * IOSAV_STATUS_ch(channel) |
| 177 | * State of the IOSAV sequence machine. Should be polled after sending an IOSAV sequence. |
| 178 | * |
| 179 | * Bitfields: |
| 180 | * [0] IDLE: IOSAV is sleeping. |
| 181 | * [1] BUSY: IOSAV is running a sequence. |
| 182 | * [2] DONE: IOSAV has completed a sequence. |
| 183 | * [3] ERROR: IOSAV detected an error and stopped on it, when using Stop-on-error. |
| 184 | * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. |
| 185 | * [5] RCOMP: RComp failure. Unused, consider Reserved. |
| 186 | * [6] Cleared with a new sequence, and set when done and refresh counter is drained. |
| 187 | * |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 188 | */ |
| 189 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 190 | /* length: [1..4] */ |
| 191 | #define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 192 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 193 | static void sfence(void) |
| 194 | { |
| 195 | asm volatile ("sfence"); |
| 196 | } |
| 197 | |
| 198 | static void toggle_io_reset(void) { |
| 199 | /* toggle IO reset bit */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 200 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
| 201 | MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 202 | udelay(1); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 203 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 204 | udelay(1); |
| 205 | } |
| 206 | |
| 207 | static u32 get_XOVER_CLK(u8 rankmap) |
| 208 | { |
| 209 | return rankmap << 24; |
| 210 | } |
| 211 | |
| 212 | static u32 get_XOVER_CMD(u8 rankmap) |
| 213 | { |
| 214 | u32 reg; |
| 215 | |
| 216 | // enable xover cmd |
| 217 | reg = 0x4000; |
| 218 | |
| 219 | // enable xover ctl |
| 220 | if (rankmap & 0x3) |
| 221 | reg |= 0x20000; |
| 222 | |
| 223 | if (rankmap & 0xc) |
| 224 | reg |= 0x4000000; |
| 225 | |
| 226 | return reg; |
| 227 | } |
| 228 | |
| 229 | /* CAS write latency. To be programmed in MR2. |
| 230 | * See DDR3 SPEC for MR2 documentation. */ |
| 231 | u8 get_CWL(u32 tCK) |
| 232 | { |
| 233 | /* Get CWL based on tCK using the following rule: */ |
| 234 | switch (tCK) { |
| 235 | case TCK_1333MHZ: |
| 236 | return 12; |
| 237 | case TCK_1200MHZ: |
| 238 | case TCK_1100MHZ: |
| 239 | return 11; |
| 240 | case TCK_1066MHZ: |
| 241 | case TCK_1000MHZ: |
| 242 | return 10; |
| 243 | case TCK_933MHZ: |
| 244 | case TCK_900MHZ: |
| 245 | return 9; |
| 246 | case TCK_800MHZ: |
| 247 | case TCK_700MHZ: |
| 248 | return 8; |
| 249 | case TCK_666MHZ: |
| 250 | return 7; |
| 251 | case TCK_533MHZ: |
| 252 | return 6; |
| 253 | default: |
| 254 | return 5; |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | void dram_find_common_params(ramctr_timing *ctrl) |
| 259 | { |
| 260 | size_t valid_dimms; |
| 261 | int channel, slot; |
| 262 | dimm_info *dimms = &ctrl->info; |
| 263 | |
| 264 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 265 | valid_dimms = 0; |
| 266 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
| 267 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 268 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 269 | continue; |
| 270 | valid_dimms++; |
| 271 | |
| 272 | /* Find all possible CAS combinations */ |
| 273 | ctrl->cas_supported &= dimm->cas_supported; |
| 274 | |
| 275 | /* Find the smallest common latencies supported by all DIMMs */ |
| 276 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 277 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 278 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
| 279 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 280 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
| 281 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
| 282 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 283 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 284 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 285 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 286 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 287 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 288 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | if (!ctrl->cas_supported) |
| 292 | die("Unsupported DIMM combination. " |
| 293 | "DIMMS do not support common CAS latency"); |
| 294 | if (!valid_dimms) |
| 295 | die("No valid DIMMs found"); |
| 296 | } |
| 297 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 298 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 299 | { |
| 300 | u32 reg; |
| 301 | int channel; |
| 302 | |
| 303 | FOR_ALL_CHANNELS { |
| 304 | // enable xover clk |
| 305 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 306 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 307 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 308 | |
| 309 | // enable xover ctl & xover cmd |
| 310 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 311 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 312 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 313 | } |
| 314 | } |
| 315 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 316 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 317 | { |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 318 | u32 addr, cpu, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 319 | |
| 320 | stretch = ctrl->ref_card_offset[channel]; |
| 321 | /* ODT stretch: Delay ODT signal by stretch value. |
| 322 | * Useful for multi DIMM setups on the same channel. */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 323 | cpu = cpu_get_cpuid(); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 324 | if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { |
| 325 | if (stretch == 2) |
| 326 | stretch = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 327 | addr = SCHED_SECOND_CBIT_ch(channel); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 328 | MCHBAR32_AND_OR(addr, 0xffffc3ff, |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 329 | (stretch << 12) | (stretch << 10)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 330 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, |
| 331 | MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 332 | } else { |
| 333 | // OTHP |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 334 | addr = TC_OTHP_ch(channel); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 335 | MCHBAR32_AND_OR(addr, 0xfff0ffff, |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 336 | (stretch << 16) | (stretch << 18)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 337 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | |
| 341 | void dram_timing_regs(ramctr_timing *ctrl) |
| 342 | { |
| 343 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 344 | int channel; |
| 345 | |
| 346 | FOR_ALL_CHANNELS { |
| 347 | // DBP |
| 348 | reg = 0; |
| 349 | reg |= ctrl->tRCD; |
| 350 | reg |= (ctrl->tRP << 4); |
| 351 | reg |= (ctrl->CAS << 8); |
| 352 | reg |= (ctrl->CWL << 12); |
| 353 | reg |= (ctrl->tRAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 354 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); |
| 355 | MCHBAR32(TC_DBP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 356 | |
| 357 | // RAP |
| 358 | reg = 0; |
| 359 | reg |= ctrl->tRRD; |
| 360 | reg |= (ctrl->tRTP << 4); |
| 361 | reg |= (ctrl->tCKE << 8); |
| 362 | reg |= (ctrl->tWTR << 12); |
| 363 | reg |= (ctrl->tFAW << 16); |
| 364 | reg |= (ctrl->tWR << 24); |
| 365 | reg |= (3 << 30); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 366 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); |
| 367 | MCHBAR32(TC_RAP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 368 | |
| 369 | // OTHP |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 370 | addr = TC_OTHP_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 371 | reg = 0; |
| 372 | reg |= ctrl->tXPDLL; |
| 373 | reg |= (ctrl->tXP << 5); |
| 374 | reg |= (ctrl->tAONPD << 8); |
| 375 | reg |= 0xa0000; |
| 376 | printram("OTHP [%x] = %x\n", addr, reg); |
| 377 | MCHBAR32(addr) = reg; |
| 378 | |
Angel Pons | 1aba2a3 | 2020-01-05 22:31:41 +0100 | [diff] [blame] | 379 | MCHBAR32(0x4014 + channel * 0x400) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 380 | |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 381 | MCHBAR32_OR(addr, 0x00020000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 382 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 383 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 384 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 385 | /* |
Patrick Rudolph | b009ac4 | 2018-07-25 15:27:50 +0200 | [diff] [blame] | 386 | * TC-Refresh timing parameters |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 387 | * The tREFIx9 field should be programmed to minimum of |
| 388 | * 8.9*tREFI (to allow for possible delays from ZQ or |
| 389 | * isoc) and tRASmax (70us) divided by 1024. |
| 390 | */ |
| 391 | val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 392 | |
| 393 | reg = ((ctrl->tREFI & 0xffff) << 0) | |
| 394 | ((ctrl->tRFC & 0x1ff) << 16) | |
| 395 | (((val32 / 1024) & 0x7f) << 25); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 396 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); |
| 397 | MCHBAR32(TC_RFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 398 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 399 | MCHBAR32_OR(TC_RFP_ch(channel), 0xff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 400 | |
| 401 | // SRFTP |
| 402 | reg = 0; |
| 403 | val32 = tDLLK; |
| 404 | reg = (reg & ~0xfff) | val32; |
| 405 | val32 = ctrl->tXSOffset; |
| 406 | reg = (reg & ~0xf000) | (val32 << 12); |
| 407 | val32 = tDLLK - ctrl->tXSOffset; |
| 408 | reg = (reg & ~0x3ff0000) | (val32 << 16); |
| 409 | val32 = ctrl->tMOD - 8; |
| 410 | reg = (reg & ~0xf0000000) | (val32 << 28); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 411 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 412 | reg); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 413 | MCHBAR32(TC_SRFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 414 | } |
| 415 | } |
| 416 | |
| 417 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 418 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 419 | int channel; |
| 420 | dimm_info *info = &ctrl->info; |
| 421 | |
| 422 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 423 | dimm_attr *dimmA, *dimmB; |
| 424 | u32 reg = 0; |
| 425 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 426 | if (info->dimm[channel][0].size_mb >= |
| 427 | info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 428 | dimmA = &info->dimm[channel][0]; |
| 429 | dimmB = &info->dimm[channel][1]; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 430 | reg |= 0 << 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 431 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 432 | dimmA = &info->dimm[channel][1]; |
| 433 | dimmB = &info->dimm[channel][0]; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 434 | reg |= 1 << 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 435 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 436 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 437 | if (dimmA && (dimmA->ranks > 0)) { |
| 438 | reg |= dimmA->size_mb / 256; |
| 439 | reg |= (dimmA->ranks - 1) << 17; |
| 440 | reg |= (dimmA->width / 8 - 1) << 19; |
| 441 | } |
| 442 | |
| 443 | if (dimmB && (dimmB->ranks > 0)) { |
| 444 | reg |= (dimmB->size_mb / 256) << 8; |
| 445 | reg |= (dimmB->ranks - 1) << 18; |
| 446 | reg |= (dimmB->width / 8 - 1) << 20; |
| 447 | } |
| 448 | |
| 449 | reg |= 1 << 21; /* rank interleave */ |
| 450 | reg |= 1 << 22; /* enhanced interleave */ |
| 451 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 452 | if ((dimmA && (dimmA->ranks > 0)) |
| 453 | || (dimmB && (dimmB->ranks > 0))) { |
| 454 | ctrl->mad_dimm[channel] = reg; |
| 455 | } else { |
| 456 | ctrl->mad_dimm[channel] = 0; |
| 457 | } |
| 458 | } |
| 459 | } |
| 460 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 461 | void dram_dimm_set_mapping(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 462 | { |
| 463 | int channel; |
| 464 | FOR_ALL_CHANNELS { |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 465 | MCHBAR32(MAD_DIMM_CH0 + channel * 4) = ctrl->mad_dimm[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 466 | } |
| 467 | } |
| 468 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 469 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 470 | { |
| 471 | u32 reg, ch0size, ch1size; |
| 472 | u8 val; |
| 473 | reg = 0; |
| 474 | val = 0; |
| 475 | if (training) { |
| 476 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 477 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 478 | } else { |
| 479 | ch0size = ctrl->channel_size_mb[0]; |
| 480 | ch1size = ctrl->channel_size_mb[1]; |
| 481 | } |
| 482 | |
| 483 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 484 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 485 | val = ch1size / 256; |
| 486 | reg = (reg & ~0xff000000) | val << 24; |
| 487 | reg = (reg & ~0xff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 488 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 489 | MCHBAR32(MAD_CHNL) = 0x24; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 490 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 491 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 492 | val = ch0size / 256; |
| 493 | reg = (reg & ~0xff000000) | val << 24; |
| 494 | reg = (reg & ~0xff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 495 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 496 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 497 | } |
| 498 | } |
| 499 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 500 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 501 | #define DEFAULT_TCK TCK_800MHZ |
| 502 | |
| 503 | unsigned int get_mem_min_tck(void) |
| 504 | { |
| 505 | u32 reg32; |
| 506 | u8 rev; |
| 507 | const struct device *dev; |
| 508 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 509 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 510 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 511 | if (dev) |
| 512 | cfg = dev->chip_info; |
| 513 | |
| 514 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 515 | if (!cfg || cfg->max_mem_clock_mhz == 0) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 516 | if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) |
Patrick Rudolph | b794a69 | 2017-08-08 13:13:51 +0200 | [diff] [blame] | 517 | return TCK_1333MHZ; |
| 518 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 519 | rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 520 | |
| 521 | if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { |
| 522 | /* read Capabilities A Register DMFC bits */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 523 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 524 | reg32 &= 0x7; |
| 525 | |
| 526 | switch (reg32) { |
| 527 | case 7: return TCK_533MHZ; |
| 528 | case 6: return TCK_666MHZ; |
| 529 | case 5: return TCK_800MHZ; |
| 530 | /* reserved: */ |
| 531 | default: |
| 532 | break; |
| 533 | } |
| 534 | } else { |
| 535 | /* read Capabilities B Register DMFC bits */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 536 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 537 | reg32 = (reg32 >> 4) & 0x7; |
| 538 | |
| 539 | switch (reg32) { |
| 540 | case 7: return TCK_533MHZ; |
| 541 | case 6: return TCK_666MHZ; |
| 542 | case 5: return TCK_800MHZ; |
| 543 | case 4: return TCK_933MHZ; |
| 544 | case 3: return TCK_1066MHZ; |
| 545 | case 2: return TCK_1200MHZ; |
| 546 | case 1: return TCK_1333MHZ; |
| 547 | /* reserved: */ |
| 548 | default: |
| 549 | break; |
| 550 | } |
| 551 | } |
| 552 | return DEFAULT_TCK; |
| 553 | } else { |
| 554 | if (cfg->max_mem_clock_mhz >= 1066) |
| 555 | return TCK_1066MHZ; |
| 556 | else if (cfg->max_mem_clock_mhz >= 933) |
| 557 | return TCK_933MHZ; |
| 558 | else if (cfg->max_mem_clock_mhz >= 800) |
| 559 | return TCK_800MHZ; |
| 560 | else if (cfg->max_mem_clock_mhz >= 666) |
| 561 | return TCK_666MHZ; |
| 562 | else if (cfg->max_mem_clock_mhz >= 533) |
| 563 | return TCK_533MHZ; |
| 564 | else |
| 565 | return TCK_400MHZ; |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 570 | |
| 571 | static unsigned int get_mmio_size(void) |
| 572 | { |
| 573 | const struct device *dev; |
| 574 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 575 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 576 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 577 | if (dev) |
| 578 | cfg = dev->chip_info; |
| 579 | |
| 580 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 581 | if (!cfg || cfg->pci_mmio_size == 0) |
| 582 | return DEFAULT_PCI_MMIO_SIZE; |
| 583 | else |
| 584 | return cfg->pci_mmio_size; |
| 585 | } |
| 586 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 587 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 588 | { |
| 589 | u32 reg, val, reclaim; |
| 590 | u32 tom, gfxstolen, gttsize; |
| 591 | size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase, |
| 592 | tsegbase, mestolenbase; |
| 593 | size_t tsegbasedelta, remapbase, remaplimit; |
| 594 | uint16_t ggc; |
| 595 | |
| 596 | mmiosize = get_mmio_size(); |
| 597 | |
| 598 | ggc = pci_read_config16(NORTHBRIDGE, GGC); |
| 599 | if (!(ggc & 2)) { |
| 600 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
| 601 | gttsize = ((ggc >> 8) & 0x3); |
| 602 | } else { |
| 603 | gfxstolen = 0; |
| 604 | gttsize = 0; |
| 605 | } |
| 606 | |
| 607 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 608 | |
| 609 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 610 | |
| 611 | mestolenbase = tom - me_uma_size; |
| 612 | |
| 613 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, |
| 614 | tom - me_uma_size); |
| 615 | gfxstolenbase = toludbase - gfxstolen; |
| 616 | gttbase = gfxstolenbase - gttsize; |
| 617 | |
| 618 | tsegbase = gttbase - tsegsize; |
| 619 | |
| 620 | // Round tsegbase down to nearest address aligned to tsegsize |
| 621 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 622 | tsegbase &= ~(tsegsize - 1); |
| 623 | |
| 624 | gttbase -= tsegbasedelta; |
| 625 | gfxstolenbase -= tsegbasedelta; |
| 626 | toludbase -= tsegbasedelta; |
| 627 | |
| 628 | // Test if it is possible to reclaim a hole in the RAM addressing |
| 629 | if (tom - me_uma_size > toludbase) { |
| 630 | // Reclaim is possible |
| 631 | reclaim = 1; |
| 632 | remapbase = MAX(4096, tom - me_uma_size); |
| 633 | remaplimit = |
| 634 | remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 635 | touudbase = remaplimit + 1; |
| 636 | } else { |
| 637 | // Reclaim not possible |
| 638 | reclaim = 0; |
| 639 | touudbase = tom - me_uma_size; |
| 640 | } |
| 641 | |
| 642 | // Update memory map in pci-e configuration space |
| 643 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 644 | |
| 645 | // TOM (top of memory) |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 646 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 647 | val = tom & 0xfff; |
| 648 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 649 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 650 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 651 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 652 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 653 | val = tom & 0xfffff000; |
| 654 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 655 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 656 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 657 | |
| 658 | // TOLUD (top of low used dram) |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 659 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 660 | val = toludbase & 0xfff; |
| 661 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 662 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 663 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 664 | |
| 665 | // TOUUD LSB (top of upper usable dram) |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 666 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 667 | val = touudbase & 0xfff; |
| 668 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 669 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 670 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 671 | |
| 672 | // TOUUD MSB |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 673 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 674 | val = touudbase & 0xfffff000; |
| 675 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 676 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 677 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 678 | |
| 679 | if (reclaim) { |
| 680 | // REMAP BASE |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 681 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
| 682 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 683 | |
| 684 | // REMAP LIMIT |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 685 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
| 686 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 687 | } |
| 688 | // TSEG |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 689 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 690 | val = tsegbase & 0xfff; |
| 691 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 692 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 693 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 694 | |
| 695 | // GFX stolen memory |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 696 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 697 | val = gfxstolenbase & 0xfff; |
| 698 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 699 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 700 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 701 | |
| 702 | // GTT stolen memory |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 703 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 704 | val = gttbase & 0xfff; |
| 705 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 706 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 707 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 708 | |
| 709 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 710 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 711 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 712 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 713 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 714 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 715 | |
| 716 | // ME base |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 717 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 718 | val = mestolenbase & 0xfff; |
| 719 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 720 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 721 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 722 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 723 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 724 | val = mestolenbase & 0xfffff000; |
| 725 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 726 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 727 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 728 | |
| 729 | // ME mask |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 730 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 731 | val = (0x80000 - me_uma_size) & 0xfff; |
| 732 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | f54ae38 | 2019-12-30 18:18:02 +0100 | [diff] [blame] | 733 | reg = reg | ME_STLEN_EN; // set ME memory enable |
| 734 | reg = reg | MELCK; // set lockbit on ME mem |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 735 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 736 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 737 | } |
| 738 | } |
| 739 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 740 | static void wait_for_iosav(int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 741 | { |
| 742 | while (1) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 743 | if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 744 | return; |
| 745 | } |
| 746 | } |
| 747 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 748 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 749 | { |
| 750 | int channel, slotrank; |
| 751 | |
| 752 | /* choose a populated channel. */ |
| 753 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 754 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 755 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 756 | |
| 757 | /* choose a populated rank. */ |
| 758 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 759 | |
| 760 | /* DRAM command ZQCS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 761 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; |
| 762 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x80c01; |
| 763 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 764 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 765 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 766 | // execute command queue - why is bit 22 set here?! |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 767 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = (1 << 22) | IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 768 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 769 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 770 | } |
| 771 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 772 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 773 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 774 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 775 | int channel; |
| 776 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 777 | while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 778 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 779 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 780 | } while ((reg & 0x14) == 0); |
| 781 | |
| 782 | // Set state of memory controller |
| 783 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 784 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 785 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 786 | reg |= 2; //ddr reset |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 787 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 788 | |
| 789 | // Assert dimm reset signal |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 790 | MCHBAR32_AND(MC_INIT_STATE_G, ~0x2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 791 | |
| 792 | // Wait 200us |
| 793 | udelay(200); |
| 794 | |
| 795 | // Deassert dimm reset signal |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 796 | MCHBAR32_OR(MC_INIT_STATE_G, 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 797 | |
| 798 | // Wait 500us |
| 799 | udelay(500); |
| 800 | |
| 801 | // Enable DCLK |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 802 | MCHBAR32_OR(MC_INIT_STATE_G, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 803 | |
| 804 | // XXX Wait 20ns |
| 805 | udelay(1); |
| 806 | |
| 807 | FOR_ALL_CHANNELS { |
| 808 | // Set valid rank CKE |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 809 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 810 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 811 | |
| 812 | // Wait 10ns for ranks to settle |
| 813 | //udelay(0.01); |
| 814 | |
| 815 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 816 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 817 | |
| 818 | // Write reset using a NOP |
| 819 | write_reset(ctrl); |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) |
| 824 | { |
| 825 | /* Get ODT based on rankmap: */ |
| 826 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) |
| 827 | + ((ctrl->rankmap[channel] >> 2) & 1); |
| 828 | |
| 829 | if (dimms_per_ch == 1) { |
| 830 | return (const odtmap){60, 60}; |
| 831 | } else { |
| 832 | return (const odtmap){120, 30}; |
| 833 | } |
| 834 | } |
| 835 | |
| 836 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, |
| 837 | int reg, u32 val) |
| 838 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 839 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 840 | |
| 841 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 842 | /* DDR3 Rank1 Address mirror |
| 843 | * swap the following pins: |
| 844 | * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
| 845 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
| 846 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) |
| 847 | | ((val & 0xa8) << 1); |
| 848 | } |
| 849 | |
| 850 | /* DRAM command MRS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 851 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f000; |
| 852 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; |
| 853 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 854 | (slotrank << 24) | (reg << 20) | val | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 855 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 856 | |
| 857 | /* DRAM command MRS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 858 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f000; |
| 859 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x41001; |
| 860 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 861 | (slotrank << 24) | (reg << 20) | val | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 862 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 863 | |
| 864 | /* DRAM command MRS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 865 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0f000; |
| 866 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); |
| 867 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 868 | (slotrank << 24) | (reg << 20) | val | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 869 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 870 | |
| 871 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 872 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 873 | } |
| 874 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 875 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 876 | { |
| 877 | u16 mr0reg, mch_cas, mch_wr; |
| 878 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 879 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 880 | |
| 881 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 882 | mr0reg = 0x100; |
| 883 | |
| 884 | // Convert CAS to MCH register friendly |
| 885 | if (ctrl->CAS < 12) { |
| 886 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 887 | } else { |
| 888 | mch_cas = (u16) (ctrl->CAS - 12); |
| 889 | mch_cas = ((mch_cas << 1) | 0x1); |
| 890 | } |
| 891 | |
| 892 | // Convert tWR to MCH register friendly |
| 893 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 894 | |
| 895 | mr0reg = (mr0reg & ~0x4) | ((mch_cas & 0x1) << 2); |
| 896 | mr0reg = (mr0reg & ~0x70) | ((mch_cas & 0xe) << 3); |
| 897 | mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9); |
| 898 | |
| 899 | // Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 900 | mr0reg = (mr0reg & ~0x1000) | (!is_mobile << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 901 | return mr0reg; |
| 902 | } |
| 903 | |
| 904 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 905 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 906 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 907 | } |
| 908 | |
| 909 | static u32 encode_odt(u32 odt) |
| 910 | { |
| 911 | switch (odt) { |
| 912 | case 30: |
| 913 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 914 | case 60: |
| 915 | return (1 << 2); // RZQ/4 |
| 916 | case 120: |
| 917 | return (1 << 6); // RZQ/2 |
| 918 | default: |
| 919 | case 0: |
| 920 | return 0; |
| 921 | } |
| 922 | } |
| 923 | |
| 924 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 925 | { |
| 926 | odtmap odt; |
| 927 | u32 mr1reg; |
| 928 | |
| 929 | odt = get_ODT(ctrl, rank, channel); |
| 930 | mr1reg = 0x2; |
| 931 | |
| 932 | mr1reg |= encode_odt(odt.rttnom); |
| 933 | |
| 934 | return mr1reg; |
| 935 | } |
| 936 | |
| 937 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 938 | { |
| 939 | u16 mr1reg; |
| 940 | |
| 941 | mr1reg = make_mr1(ctrl, rank, channel); |
| 942 | |
| 943 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 944 | } |
| 945 | |
| 946 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 947 | { |
| 948 | u16 pasr, cwl, mr2reg; |
| 949 | odtmap odt; |
| 950 | int srt; |
| 951 | |
| 952 | pasr = 0; |
| 953 | cwl = ctrl->CWL - 5; |
| 954 | odt = get_ODT(ctrl, rank, channel); |
| 955 | |
| 956 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
| 957 | |
| 958 | mr2reg = 0; |
| 959 | mr2reg = (mr2reg & ~0x7) | pasr; |
| 960 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 961 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 962 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 963 | mr2reg |= (odt.rttwr / 60) << 9; |
| 964 | |
| 965 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
| 966 | } |
| 967 | |
| 968 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 969 | { |
| 970 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 971 | } |
| 972 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 973 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 974 | { |
| 975 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 976 | int channel; |
| 977 | |
| 978 | FOR_ALL_POPULATED_CHANNELS { |
| 979 | FOR_ALL_POPULATED_RANKS { |
| 980 | // MR2 |
| 981 | dram_mr2(ctrl, slotrank, channel); |
| 982 | |
| 983 | // MR3 |
| 984 | dram_mr3(ctrl, slotrank, channel); |
| 985 | |
| 986 | // MR1 |
| 987 | dram_mr1(ctrl, slotrank, channel); |
| 988 | |
| 989 | // MR0 |
| 990 | dram_mr0(ctrl, slotrank, channel); |
| 991 | } |
| 992 | } |
| 993 | |
| 994 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 995 | MCHBAR32(IOSAV_n_SP_CMD_CTL(0)) = 0x7; |
| 996 | MCHBAR32(IOSAV_n_SUBSEQ_CTL(0)) = 0xf1001; |
| 997 | MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002; |
| 998 | MCHBAR32(IOSAV_n_ADDR_UPD(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 999 | |
| 1000 | /* DRAM command ZQCL */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1001 | MCHBAR32(IOSAV_n_SP_CMD_CTL(1)) = 0x1f003; |
| 1002 | MCHBAR32(IOSAV_n_SUBSEQ_CTL(1)) = 0x1901001; |
| 1003 | MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400; |
| 1004 | MCHBAR32(IOSAV_n_ADDR_UPD(1)) = 0x288; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1005 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1006 | // execute command queue on all channels? Why isn't bit 0 set here? |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1007 | MCHBAR32(IOSAV_SEQ_CTL) = 0x40004; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1008 | |
| 1009 | // Drain |
| 1010 | FOR_ALL_CHANNELS { |
| 1011 | // Wait for ref drained |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1012 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1013 | } |
| 1014 | |
| 1015 | // Refresh enable |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1016 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1017 | |
| 1018 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1019 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1020 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1021 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1022 | |
| 1023 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 1024 | |
| 1025 | // Drain |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1026 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1027 | |
| 1028 | /* DRAM command ZQCS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1029 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; |
| 1030 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x659001; |
| 1031 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1032 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1033 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1034 | |
| 1035 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1036 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1037 | |
| 1038 | // Drain |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1039 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1040 | } |
| 1041 | } |
| 1042 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 1043 | static const u32 lane_base[] = { |
| 1044 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 1045 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 1046 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1047 | }; |
| 1048 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1049 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1050 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1051 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1052 | int lane; |
| 1053 | int slotrank, slot; |
| 1054 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1055 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1056 | |
| 1057 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1058 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 1059 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1060 | } |
| 1061 | |
| 1062 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 1063 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 1064 | case 0: |
| 1065 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1066 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1067 | break; |
| 1068 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1069 | pi_coding_ctrl[slot] = |
| 1070 | ctrl->timings[channel][2 * slot + 0].pi_coding + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1071 | full_shift; |
| 1072 | break; |
| 1073 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1074 | pi_coding_ctrl[slot] = |
| 1075 | ctrl->timings[channel][2 * slot + 1].pi_coding + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1076 | full_shift; |
| 1077 | break; |
| 1078 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1079 | pi_coding_ctrl[slot] = |
| 1080 | (ctrl->timings[channel][2 * slot].pi_coding + |
| 1081 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1082 | full_shift; |
| 1083 | break; |
| 1084 | } |
| 1085 | |
| 1086 | /* enable CMD XOVER */ |
| 1087 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1088 | reg32 |= ((pi_coding_ctrl[0] & 0x3f) << 6) | ((pi_coding_ctrl[0] & 0x40) << 9); |
| 1089 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1090 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 1091 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1092 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1093 | |
| 1094 | /* enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1095 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 1096 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1097 | |
| 1098 | FOR_ALL_POPULATED_RANKS { |
| 1099 | int shift = |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1100 | ctrl->timings[channel][slotrank].pi_coding + full_shift; |
| 1101 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1102 | if (shift < 0) |
| 1103 | shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1104 | offset_pi_code = ctrl->pi_code_offset + shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1105 | /* set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1106 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 1107 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1108 | } |
| 1109 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1110 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 1111 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1112 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1113 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 1114 | reg_io_latency &= 0xffff0000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1115 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1116 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1117 | |
| 1118 | FOR_ALL_POPULATED_RANKS { |
| 1119 | int post_timA_min_high = 7, post_timA_max_high = 0; |
| 1120 | int pre_timA_min_high = 7, pre_timA_max_high = 0; |
| 1121 | int shift_402x = 0; |
| 1122 | int shift = |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1123 | ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1124 | |
| 1125 | if (shift < 0) |
| 1126 | shift = 0; |
| 1127 | |
| 1128 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 1129 | post_timA_min_high = MIN(post_timA_min_high, |
| 1130 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1131 | timA + shift) >> 6); |
| 1132 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 1133 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1134 | timA >> 6); |
| 1135 | post_timA_max_high = MAX(post_timA_max_high, |
| 1136 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1137 | timA + shift) >> 6); |
| 1138 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 1139 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1140 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1141 | } |
| 1142 | |
| 1143 | if (pre_timA_max_high - pre_timA_min_high < |
| 1144 | post_timA_max_high - post_timA_min_high) |
| 1145 | shift_402x = +1; |
| 1146 | else if (pre_timA_max_high - pre_timA_min_high > |
| 1147 | post_timA_max_high - post_timA_min_high) |
| 1148 | shift_402x = -1; |
| 1149 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 1150 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1151 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1152 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1153 | reg_roundtrip_latency |= |
| 1154 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1155 | shift_402x) << (8 * slotrank); |
| 1156 | |
| 1157 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 1158 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1159 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1160 | timA + shift) & 0x3f) |
| 1161 | | |
| 1162 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1163 | rising + shift) << 8) |
| 1164 | | |
| 1165 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1166 | timA + shift - |
| 1167 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1168 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1169 | falling + shift) << 20)); |
| 1170 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 1171 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1172 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1173 | timC + shift) & 0x3f) |
| 1174 | | |
| 1175 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1176 | timB + shift) & 0x3f) << 8) |
| 1177 | | |
| 1178 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1179 | timB + shift) & 0x1c0) << 9) |
| 1180 | | |
| 1181 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1182 | timC + shift) & 0x40) << 13)); |
| 1183 | } |
| 1184 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1185 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1186 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1187 | } |
| 1188 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1189 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1190 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1191 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1192 | |
| 1193 | /* DRAM command MRS |
| 1194 | * write MR3 MPR enable |
| 1195 | * in this mode only RD and RDA are allowed |
| 1196 | * all reads return a predefined pattern */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1197 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; |
| 1198 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); |
| 1199 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; |
| 1200 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1201 | |
| 1202 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1203 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; |
| 1204 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4040c01; |
| 1205 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); |
| 1206 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1207 | |
| 1208 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1209 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 1210 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); |
| 1211 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; |
| 1212 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1213 | |
| 1214 | /* DRAM command MRS |
| 1215 | * write MR3 MPR disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1216 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; |
| 1217 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); |
| 1218 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; |
| 1219 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1220 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1221 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1222 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1223 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1224 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1225 | } |
| 1226 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1227 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1228 | int lane) |
| 1229 | { |
| 1230 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 1231 | return ((MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> |
| 1232 | (timA % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1233 | } |
| 1234 | |
| 1235 | struct run { |
| 1236 | int middle; |
| 1237 | int end; |
| 1238 | int start; |
| 1239 | int all; |
| 1240 | int length; |
| 1241 | }; |
| 1242 | |
| 1243 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1244 | { |
| 1245 | int i, ls; |
| 1246 | int bl = 0, bs = 0; |
| 1247 | struct run ret; |
| 1248 | |
| 1249 | ls = 0; |
| 1250 | for (i = 0; i < 2 * sz; i++) |
| 1251 | if (seq[i % sz]) { |
| 1252 | if (i - ls > bl) { |
| 1253 | bl = i - ls; |
| 1254 | bs = ls; |
| 1255 | } |
| 1256 | ls = i + 1; |
| 1257 | } |
| 1258 | if (bl == 0) { |
| 1259 | ret.middle = sz / 2; |
| 1260 | ret.start = 0; |
| 1261 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1262 | ret.length = sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1263 | ret.all = 1; |
| 1264 | return ret; |
| 1265 | } |
| 1266 | |
| 1267 | ret.start = bs % sz; |
| 1268 | ret.end = (bs + bl - 1) % sz; |
| 1269 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1270 | ret.length = bl; |
| 1271 | ret.all = 0; |
| 1272 | |
| 1273 | return ret; |
| 1274 | } |
| 1275 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1276 | static void discover_timA_coarse(ramctr_timing *ctrl, int channel, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1277 | int slotrank, int *upperA) |
| 1278 | { |
| 1279 | int timA; |
| 1280 | int statistics[NUM_LANES][128]; |
| 1281 | int lane; |
| 1282 | |
| 1283 | for (timA = 0; timA < 128; timA++) { |
| 1284 | FOR_ALL_LANES { |
| 1285 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1286 | } |
| 1287 | program_timings(ctrl, channel); |
| 1288 | |
| 1289 | test_timA(ctrl, channel, slotrank); |
| 1290 | |
| 1291 | FOR_ALL_LANES { |
| 1292 | statistics[lane][timA] = |
| 1293 | !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1294 | } |
| 1295 | } |
| 1296 | FOR_ALL_LANES { |
| 1297 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1298 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1299 | upperA[lane] = rn.end; |
| 1300 | if (upperA[lane] < rn.middle) |
| 1301 | upperA[lane] += 128; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1302 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1303 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1304 | } |
| 1305 | } |
| 1306 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1307 | static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1308 | int *upperA) |
| 1309 | { |
| 1310 | int timA_delta; |
| 1311 | int statistics[NUM_LANES][51]; |
| 1312 | int lane, i; |
| 1313 | |
| 1314 | memset(statistics, 0, sizeof(statistics)); |
| 1315 | |
| 1316 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
| 1317 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. |
| 1318 | timA = upperA[lane] + timA_delta + 0x40; |
| 1319 | program_timings(ctrl, channel); |
| 1320 | |
| 1321 | for (i = 0; i < 100; i++) { |
| 1322 | test_timA(ctrl, channel, slotrank); |
| 1323 | FOR_ALL_LANES { |
| 1324 | statistics[lane][timA_delta + 25] += |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1325 | does_lane_work(ctrl, channel, slotrank, |
| 1326 | lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1327 | } |
| 1328 | } |
| 1329 | } |
| 1330 | FOR_ALL_LANES { |
| 1331 | int last_zero, first_all; |
| 1332 | |
| 1333 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1334 | if (statistics[lane][last_zero + 25]) |
| 1335 | break; |
| 1336 | last_zero--; |
| 1337 | for (first_all = -25; first_all <= 25; first_all++) |
| 1338 | if (statistics[lane][first_all + 25] == 100) |
| 1339 | break; |
| 1340 | |
| 1341 | printram("lane %d: %d, %d\n", lane, last_zero, |
| 1342 | first_all); |
| 1343 | |
| 1344 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
| 1345 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1346 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
| 1347 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
| 1348 | } |
| 1349 | } |
| 1350 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1351 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1352 | { |
| 1353 | int works[NUM_LANES]; |
| 1354 | int lane; |
| 1355 | while (1) { |
| 1356 | int all_works = 1, some_works = 0; |
| 1357 | program_timings(ctrl, channel); |
| 1358 | test_timA(ctrl, channel, slotrank); |
| 1359 | FOR_ALL_LANES { |
| 1360 | works[lane] = |
| 1361 | !does_lane_work(ctrl, channel, slotrank, lane); |
| 1362 | if (works[lane]) |
| 1363 | some_works = 1; |
| 1364 | else |
| 1365 | all_works = 0; |
| 1366 | } |
| 1367 | if (all_works) |
| 1368 | return 0; |
| 1369 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1370 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1371 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1372 | channel, slotrank); |
| 1373 | return MAKE_ERR; |
| 1374 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1375 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1376 | printram("4024 -= 2;\n"); |
| 1377 | continue; |
| 1378 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1379 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1380 | printram("4028 += 2;\n"); |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1381 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1382 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1383 | channel, slotrank); |
| 1384 | return MAKE_ERR; |
| 1385 | } |
| 1386 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1387 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1388 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1389 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1390 | } |
| 1391 | } |
| 1392 | return 0; |
| 1393 | } |
| 1394 | |
| 1395 | struct timA_minmax { |
| 1396 | int timA_min_high, timA_max_high; |
| 1397 | }; |
| 1398 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1399 | static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1400 | struct timA_minmax *mnmx) |
| 1401 | { |
| 1402 | int lane; |
| 1403 | mnmx->timA_min_high = 7; |
| 1404 | mnmx->timA_max_high = 0; |
| 1405 | |
| 1406 | FOR_ALL_LANES { |
| 1407 | if (mnmx->timA_min_high > |
| 1408 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1409 | mnmx->timA_min_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1410 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1411 | if (mnmx->timA_max_high < |
| 1412 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1413 | mnmx->timA_max_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1414 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1415 | } |
| 1416 | } |
| 1417 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1418 | static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1419 | struct timA_minmax *mnmx) |
| 1420 | { |
| 1421 | struct timA_minmax post; |
| 1422 | int shift_402x = 0; |
| 1423 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1424 | /* Get changed maxima. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1425 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1426 | |
| 1427 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1428 | post.timA_max_high - post.timA_min_high) |
| 1429 | shift_402x = +1; |
| 1430 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1431 | post.timA_max_high - post.timA_min_high) |
| 1432 | shift_402x = -1; |
| 1433 | else |
| 1434 | shift_402x = 0; |
| 1435 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1436 | ctrl->timings[channel][slotrank].io_latency += shift_402x; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1437 | ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1438 | printram("4024 += %d;\n", shift_402x); |
| 1439 | printram("4028 += %d;\n", shift_402x); |
| 1440 | } |
| 1441 | |
| 1442 | /* Compensate the skew between DQS and DQs. |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1443 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1444 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
| 1445 | * either all DQs signals or DQS signal, a full phase shift can be introduced. It is assumed |
| 1446 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1447 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1448 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1449 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1450 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
| 1451 | * DQs in phase the data read is expected to alternate on every byte: |
| 1452 | * 0xFF 0x00 0xFF ... |
| 1453 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1454 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1455 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1456 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1457 | { |
| 1458 | int channel, slotrank, lane; |
| 1459 | int err; |
| 1460 | |
| 1461 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1462 | int all_high, some_high; |
| 1463 | int upperA[NUM_LANES]; |
| 1464 | struct timA_minmax mnmx; |
| 1465 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1466 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1467 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1468 | /* DRAM command PREA */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1469 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; |
| 1470 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); |
| 1471 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
| 1472 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1473 | |
| 1474 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1475 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1476 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1477 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1478 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1479 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1480 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1481 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1482 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1483 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1484 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1485 | all_high = 1; |
| 1486 | some_high = 0; |
| 1487 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1488 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1489 | some_high = 1; |
| 1490 | else |
| 1491 | all_high = 0; |
| 1492 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1493 | |
| 1494 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1495 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1496 | printram("4028--;\n"); |
| 1497 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1498 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1499 | upperA[lane] -= 0x40; |
| 1500 | |
| 1501 | } |
| 1502 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1503 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1504 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1505 | printram("4024++;\n"); |
| 1506 | printram("4028++;\n"); |
| 1507 | } |
| 1508 | |
| 1509 | program_timings(ctrl, channel); |
| 1510 | |
| 1511 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1512 | |
| 1513 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1514 | if (err) |
| 1515 | return err; |
| 1516 | |
| 1517 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1518 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1519 | |
| 1520 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1521 | |
| 1522 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1523 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1524 | |
| 1525 | FOR_ALL_LANES { |
| 1526 | ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; |
| 1527 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1528 | ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1529 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1530 | |
| 1531 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1532 | |
| 1533 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1534 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1535 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1536 | |
| 1537 | printram("final results:\n"); |
| 1538 | FOR_ALL_LANES |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1539 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
| 1540 | lane, |
| 1541 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1542 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1543 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1544 | |
| 1545 | toggle_io_reset(); |
| 1546 | } |
| 1547 | |
| 1548 | FOR_ALL_POPULATED_CHANNELS { |
| 1549 | program_timings(ctrl, channel); |
| 1550 | } |
| 1551 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1552 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1553 | } |
| 1554 | return 0; |
| 1555 | } |
| 1556 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1557 | static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1558 | { |
| 1559 | int lane; |
| 1560 | |
| 1561 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1562 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1563 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1564 | } |
| 1565 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1566 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1567 | |
| 1568 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1569 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; |
| 1570 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 1571 | (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1572 | | 4 | (ctrl->tRCD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1573 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (6 << 16); |
| 1574 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1575 | |
| 1576 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1577 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f207; |
| 1578 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8041001; |
| 1579 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 8; |
| 1580 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1581 | |
| 1582 | /* DRAM command WR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1583 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f201; |
| 1584 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x80411f4; |
| 1585 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; |
| 1586 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1587 | |
| 1588 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1589 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f207; |
| 1590 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1591 | 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1592 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 8; |
| 1593 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1594 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1595 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1596 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1597 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1598 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1599 | |
| 1600 | /* DRAM command PREA */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1601 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; |
| 1602 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); |
| 1603 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
| 1604 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1605 | |
| 1606 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1607 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; |
| 1608 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 1609 | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1610 | | 8 | (ctrl->CAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1611 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; |
| 1612 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x244; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1613 | |
| 1614 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1615 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 1616 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 1617 | 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1618 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); |
| 1619 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1620 | |
| 1621 | /* DRAM command PREA */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1622 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; |
| 1623 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); |
| 1624 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; |
| 1625 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x240; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1626 | |
| 1627 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1628 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1629 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1630 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1631 | } |
| 1632 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1633 | static void timC_threshold_process(int *data, const int count) |
| 1634 | { |
| 1635 | int min = data[0]; |
| 1636 | int max = min; |
| 1637 | int i; |
| 1638 | for (i = 1; i < count; i++) { |
| 1639 | if (min > data[i]) |
| 1640 | min = data[i]; |
| 1641 | if (max < data[i]) |
| 1642 | max = data[i]; |
| 1643 | } |
| 1644 | int threshold = min/2 + max/2; |
| 1645 | for (i = 0; i < count; i++) |
| 1646 | data[i] = data[i] > threshold; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1647 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1648 | } |
| 1649 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1650 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1651 | { |
| 1652 | int timC; |
| 1653 | int statistics[NUM_LANES][MAX_TIMC + 1]; |
| 1654 | int lane; |
| 1655 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1656 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1657 | |
| 1658 | /* DRAM command PREA */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1659 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; |
| 1660 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); |
| 1661 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
| 1662 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1663 | |
| 1664 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1665 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1666 | |
| 1667 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1668 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1669 | program_timings(ctrl, channel); |
| 1670 | |
| 1671 | test_timC(ctrl, channel, slotrank); |
| 1672 | |
| 1673 | FOR_ALL_LANES { |
| 1674 | statistics[lane][timC] = |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1675 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1676 | } |
| 1677 | } |
| 1678 | FOR_ALL_LANES { |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1679 | struct run rn = get_longest_zero_run( |
| 1680 | statistics[lane], ARRAY_SIZE(statistics[lane])); |
| 1681 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1682 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1683 | channel, slotrank, lane); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1684 | /* With command training not happend yet, the lane can |
| 1685 | * be erroneous. Take the avarage as reference and try |
| 1686 | * again to find a run. |
| 1687 | */ |
| 1688 | timC_threshold_process(statistics[lane], |
| 1689 | ARRAY_SIZE(statistics[lane])); |
| 1690 | rn = get_longest_zero_run(statistics[lane], |
| 1691 | ARRAY_SIZE(statistics[lane])); |
| 1692 | if (rn.all || rn.length < 8) { |
| 1693 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1694 | return MAKE_ERR; |
| 1695 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1696 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1697 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1698 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1699 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1700 | } |
| 1701 | return 0; |
| 1702 | } |
| 1703 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1704 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1705 | { |
| 1706 | int channel, ret = 0; |
| 1707 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1708 | ret++; |
| 1709 | return ret; |
| 1710 | } |
| 1711 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1712 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1713 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1714 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1715 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1716 | for (j = 0; j < 16; j++) |
| 1717 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
| 1718 | sfence(); |
| 1719 | } |
| 1720 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1721 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1722 | { |
| 1723 | int ret = 0; |
| 1724 | int channel; |
| 1725 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1726 | return ret; |
| 1727 | } |
| 1728 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1729 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1730 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1731 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1732 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1733 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1734 | for (j = 0; j < 16; j++) |
| 1735 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
| 1736 | for (j = 0; j < 16; j++) |
| 1737 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
| 1738 | sfence(); |
| 1739 | } |
| 1740 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1741 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1742 | { |
| 1743 | int channel, slotrank, lane; |
| 1744 | |
| 1745 | FOR_ALL_POPULATED_CHANNELS { |
| 1746 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1747 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1748 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1749 | } |
| 1750 | |
| 1751 | program_timings(ctrl, channel); |
| 1752 | |
| 1753 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1754 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1755 | |
| 1756 | /* DRAM command MRS |
| 1757 | * write MR3 MPR enable |
| 1758 | * in this mode only RD and RDA are allowed |
| 1759 | * all reads return a predefined pattern */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1760 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; |
| 1761 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1762 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1763 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1764 | (slotrank << 24) | 0x360004; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1765 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1766 | |
| 1767 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1768 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; |
| 1769 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 1770 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1771 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1772 | |
| 1773 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1774 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 1775 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1776 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1777 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1778 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1779 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1780 | |
| 1781 | /* DRAM command MRS |
| 1782 | * write MR3 MPR disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1783 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; |
| 1784 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1785 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1786 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1787 | (slotrank << 24) | 0x360000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1788 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1789 | |
| 1790 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1791 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1792 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1793 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1794 | } |
| 1795 | |
| 1796 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1797 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 1798 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1799 | } |
| 1800 | |
| 1801 | program_timings(ctrl, channel); |
| 1802 | |
| 1803 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1804 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1805 | /* DRAM command MRS |
| 1806 | * write MR3 MPR enable |
| 1807 | * in this mode only RD and RDA are allowed |
| 1808 | * all reads return a predefined pattern */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1809 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; |
| 1810 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1811 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1812 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1813 | (slotrank << 24) | 0x360004; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1814 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1815 | |
| 1816 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1817 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; |
| 1818 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 1819 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1820 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1821 | |
| 1822 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1823 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 1824 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1825 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1826 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1827 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1828 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1829 | |
| 1830 | /* DRAM command MRS |
| 1831 | * write MR3 MPR disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1832 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; |
| 1833 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1834 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1835 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1836 | (slotrank << 24) | 0x360000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1837 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1838 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1839 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1840 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1841 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1842 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1843 | } |
| 1844 | } |
| 1845 | } |
| 1846 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1847 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1848 | { |
| 1849 | /* enable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1850 | write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1851 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1852 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1853 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1854 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f207; |
| 1855 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1856 | 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1857 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 8 | (slotrank << 24); |
| 1858 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1859 | |
| 1860 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1861 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f107; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1862 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1863 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; |
| 1864 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1865 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1866 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1867 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1868 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1869 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1870 | |
| 1871 | /* disable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1872 | write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1873 | } |
| 1874 | |
| 1875 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1876 | { |
| 1877 | int timB; |
| 1878 | int statistics[NUM_LANES][128]; |
| 1879 | int lane; |
| 1880 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1881 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1882 | |
| 1883 | for (timB = 0; timB < 128; timB++) { |
| 1884 | FOR_ALL_LANES { |
| 1885 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1886 | } |
| 1887 | program_timings(ctrl, channel); |
| 1888 | |
| 1889 | test_timB(ctrl, channel, slotrank); |
| 1890 | |
| 1891 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 1892 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 1893 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 1894 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1895 | } |
| 1896 | } |
| 1897 | FOR_ALL_LANES { |
| 1898 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1899 | /* timC is a direct function of timB's 6 LSBs. |
| 1900 | * Some tests increments the value of timB by a small value, |
| 1901 | * which might cause the 6bit value to overflow, if it's close |
| 1902 | * to 0x3F. Increment the value by a small offset if it's likely |
| 1903 | * to overflow, to make sure it won't overflow while running |
| 1904 | * tests and bricks the system due to a non matching timC. |
| 1905 | * |
| 1906 | * TODO: find out why some tests (edge write discovery) |
| 1907 | * increment timB. */ |
| 1908 | if ((rn.start & 0x3F) == 0x3E) |
| 1909 | rn.start += 2; |
| 1910 | else if ((rn.start & 0x3F) == 0x3F) |
| 1911 | rn.start += 1; |
| 1912 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1913 | if (rn.all) { |
| 1914 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1915 | channel, slotrank, lane); |
| 1916 | return MAKE_ERR; |
| 1917 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1918 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1919 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1920 | } |
| 1921 | return 0; |
| 1922 | } |
| 1923 | |
| 1924 | static int get_timB_high_adjust(u64 val) |
| 1925 | { |
| 1926 | int i; |
| 1927 | |
| 1928 | /* good */ |
| 1929 | if (val == 0xffffffffffffffffLL) |
| 1930 | return 0; |
| 1931 | |
| 1932 | if (val >= 0xf000000000000000LL) { |
| 1933 | /* needs negative adjustment */ |
| 1934 | for (i = 0; i < 8; i++) |
| 1935 | if (val << (8 * (7 - i) + 4)) |
| 1936 | return -i; |
| 1937 | } else { |
| 1938 | /* needs positive adjustment */ |
| 1939 | for (i = 0; i < 8; i++) |
| 1940 | if (val >> (8 * (7 - i) + 4)) |
| 1941 | return i; |
| 1942 | } |
| 1943 | return 8; |
| 1944 | } |
| 1945 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1946 | static void adjust_high_timB(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1947 | { |
| 1948 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1949 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1950 | FOR_ALL_POPULATED_CHANNELS { |
| 1951 | fill_pattern1(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1952 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1953 | } |
| 1954 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1955 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1956 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1957 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1958 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1959 | |
| 1960 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1961 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; |
| 1962 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); |
| 1963 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 1964 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1965 | |
| 1966 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1967 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f207; |
| 1968 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8040c01; |
| 1969 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x8; |
| 1970 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1971 | |
| 1972 | /* DRAM command WR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1973 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f201; |
| 1974 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x8041003; |
| 1975 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); |
| 1976 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x3e2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1977 | |
| 1978 | /* DRAM command NOP */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1979 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f207; |
| 1980 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1981 | 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1982 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x8; |
| 1983 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1984 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1985 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1986 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1987 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1988 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1989 | |
| 1990 | /* DRAM command PREA */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1991 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1992 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); |
| 1993 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1994 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1995 | |
| 1996 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1997 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1998 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1999 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; |
| 2000 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2001 | |
| 2002 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2003 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x3f105; |
| 2004 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + |
| 2005 | ctrl->timings[channel][slotrank].roundtrip_latency + |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2006 | ctrl->timings[channel][slotrank].io_latency) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2007 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60008; |
| 2008 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2009 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2010 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2011 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2012 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2013 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2014 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 2015 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 2016 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 2017 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2018 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 2019 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 2020 | get_timB_high_adjust(res) * 64; |
| 2021 | |
| 2022 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2023 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 2024 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2025 | } |
| 2026 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2027 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2028 | } |
| 2029 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2030 | static void write_op(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2031 | { |
| 2032 | int slotrank; |
| 2033 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2034 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2035 | |
| 2036 | /* choose an existing rank. */ |
| 2037 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2038 | |
| 2039 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2040 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; |
| 2041 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; |
| 2042 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 2043 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2044 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2045 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2046 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2047 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2048 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2049 | } |
| 2050 | |
| 2051 | /* Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
| 2052 | * DDR3 adopted the fly-by topology. The data and strobes signals reach |
| 2053 | * the chips at different times with respect to command, address and |
| 2054 | * clock signals. |
| 2055 | * By delaying either all DQ/DQs or all CMD/ADDR/CLK signals, a full phase |
| 2056 | * shift can be introduced. |
| 2057 | * It is assumed that the CLK/ADDR/CMD signals have the same routing delay. |
| 2058 | * |
| 2059 | * To find the required phase shift the DRAM is placed in "write leveling" mode. |
| 2060 | * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the |
| 2061 | * sampled value on the data lanes (DQs). |
| 2062 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2063 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2064 | { |
| 2065 | int channel, slotrank, lane; |
| 2066 | int err; |
| 2067 | |
| 2068 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2069 | MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2070 | |
| 2071 | FOR_ALL_POPULATED_CHANNELS { |
| 2072 | write_op(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2073 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2074 | } |
| 2075 | |
| 2076 | /* refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2077 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2078 | FOR_ALL_POPULATED_CHANNELS { |
| 2079 | write_op(ctrl, channel); |
| 2080 | } |
| 2081 | |
| 2082 | /* enable write leveling on all ranks |
| 2083 | * disable all DQ outputs |
| 2084 | * only NOP is allowed in this mode */ |
| 2085 | FOR_ALL_CHANNELS |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2086 | FOR_ALL_POPULATED_RANKS |
| 2087 | write_mrreg(ctrl, channel, slotrank, 1, |
| 2088 | make_mr1(ctrl, slotrank, channel) | 0x1080); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2089 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2090 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2091 | |
| 2092 | toggle_io_reset(); |
| 2093 | |
| 2094 | /* set any valid value for timB, it gets corrected later */ |
| 2095 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2096 | err = discover_timB(ctrl, channel, slotrank); |
| 2097 | if (err) |
| 2098 | return err; |
| 2099 | } |
| 2100 | |
| 2101 | /* disable write leveling on all ranks */ |
| 2102 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 2103 | write_mrreg(ctrl, channel, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2104 | slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2105 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2106 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2107 | |
| 2108 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2109 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2110 | |
| 2111 | /* refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2112 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2113 | |
| 2114 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2115 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); |
| 2116 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 2117 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2118 | |
| 2119 | /* DRAM command ZQCS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2120 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; |
| 2121 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x659001; |
| 2122 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x60000; |
| 2123 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2124 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2125 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2126 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2127 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2128 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2129 | } |
| 2130 | |
| 2131 | toggle_io_reset(); |
| 2132 | |
| 2133 | printram("CPE\n"); |
| 2134 | precharge(ctrl); |
| 2135 | printram("CPF\n"); |
| 2136 | |
| 2137 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2138 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2139 | } |
| 2140 | |
| 2141 | FOR_ALL_POPULATED_CHANNELS { |
| 2142 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2143 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2144 | } |
| 2145 | |
| 2146 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2147 | err = discover_timC(ctrl, channel, slotrank); |
| 2148 | if (err) |
| 2149 | return err; |
| 2150 | } |
| 2151 | |
| 2152 | FOR_ALL_POPULATED_CHANNELS |
| 2153 | program_timings(ctrl, channel); |
| 2154 | |
| 2155 | /* measure and adjust timB timings */ |
| 2156 | adjust_high_timB(ctrl); |
| 2157 | |
| 2158 | FOR_ALL_POPULATED_CHANNELS |
| 2159 | program_timings(ctrl, channel); |
| 2160 | |
| 2161 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2162 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2163 | } |
| 2164 | return 0; |
| 2165 | } |
| 2166 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2167 | static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2168 | { |
| 2169 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2170 | int timC_delta; |
| 2171 | int lanes_ok = 0; |
| 2172 | int ctr = 0; |
| 2173 | int lane; |
| 2174 | |
| 2175 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2176 | FOR_ALL_LANES { |
| 2177 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2178 | saved_rt.lanes[lane].timC + timC_delta; |
| 2179 | } |
| 2180 | program_timings(ctrl, channel); |
| 2181 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2182 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2183 | } |
| 2184 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2185 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2186 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2187 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2188 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2189 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; |
| 2190 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2191 | ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2192 | | 8 | (ctrl->tRCD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2193 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2194 | (slotrank << 24) | ctr | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2195 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 2196 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2197 | /* DRAM command WR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2198 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; |
| 2199 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2200 | 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2201 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); |
| 2202 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
| 2203 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x20e42; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2204 | |
| 2205 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2206 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 2207 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2208 | 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2209 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); |
| 2210 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
| 2211 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x20e42; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2212 | |
| 2213 | /* DRAM command PRE */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2214 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; |
| 2215 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xf1001; |
| 2216 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; |
| 2217 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2218 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2219 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2220 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2221 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2222 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2223 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2224 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2225 | |
| 2226 | if (r32 == 0) |
| 2227 | lanes_ok |= 1 << lane; |
| 2228 | } |
| 2229 | ctr++; |
| 2230 | if (lanes_ok == ((1 << NUM_LANES) - 1)) |
| 2231 | break; |
| 2232 | } |
| 2233 | |
| 2234 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2235 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2236 | return lanes_ok != ((1 << NUM_LANES) - 1); |
| 2237 | } |
| 2238 | |
| 2239 | #include "raminit_patterns.h" |
| 2240 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2241 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2242 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2243 | unsigned int i, j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2244 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2245 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2246 | |
| 2247 | if (patno) { |
| 2248 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2249 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2250 | for (i = 0; i < 32; i++) { |
| 2251 | for (j = 0; j < 16; j++) { |
| 2252 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
| 2253 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2254 | val = ~val; |
| 2255 | write32((void *)(0x04000000 + channel_offset + i * channel_step + |
| 2256 | j * 4), val); |
| 2257 | } |
| 2258 | } |
| 2259 | |
| 2260 | } else { |
| 2261 | for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) { |
| 2262 | for (j = 0; j < 16; j++) |
| 2263 | write32((void *)(0x04000000 + channel_offset + i * channel_step + |
| 2264 | j * 4), pattern[i][j]); |
| 2265 | } |
| 2266 | sfence(); |
| 2267 | } |
| 2268 | } |
| 2269 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2270 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2271 | { |
| 2272 | int channel, slotrank; |
| 2273 | |
| 2274 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2275 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2276 | |
| 2277 | /* choose an existing rank. */ |
| 2278 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2279 | |
| 2280 | /* DRAM command ZQCS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2281 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; |
| 2282 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; |
| 2283 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 2284 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2285 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2286 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2287 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2288 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2289 | wait_for_iosav(channel); |
| 2290 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2291 | } |
| 2292 | |
| 2293 | /* refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2294 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2295 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2296 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2297 | |
| 2298 | /* choose an existing rank. */ |
| 2299 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2300 | |
| 2301 | /* DRAM command ZQCS */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2302 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; |
| 2303 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; |
| 2304 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 2305 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2306 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2307 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2308 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2309 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2310 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2311 | } |
| 2312 | |
| 2313 | /* jedec reset */ |
| 2314 | dram_jedecreset(ctrl); |
| 2315 | /* mrs commands. */ |
| 2316 | dram_mrscommands(ctrl); |
| 2317 | |
| 2318 | toggle_io_reset(); |
| 2319 | } |
| 2320 | |
| 2321 | #define MIN_C320C_LEN 13 |
| 2322 | |
| 2323 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2324 | { |
| 2325 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2326 | int slotrank; |
| 2327 | int c320c; |
| 2328 | int stat[NUM_SLOTRANKS][256]; |
| 2329 | int delta = 0; |
| 2330 | |
| 2331 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2332 | |
| 2333 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2334 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2335 | } |
| 2336 | |
| 2337 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2338 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2339 | MCHBAR32(TC_RAP_ch(channel)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2340 | ctrl->tRRD |
| 2341 | | (ctrl->tRTP << 4) |
| 2342 | | (ctrl->tCKE << 8) |
| 2343 | | (ctrl->tWTR << 12) |
| 2344 | | (ctrl->tFAW << 16) |
| 2345 | | (ctrl->tWR << 24) |
| 2346 | | (ctrl->cmd_stretch[channel] << 30); |
| 2347 | |
| 2348 | if (ctrl->cmd_stretch[channel] == 2) |
| 2349 | delta = 2; |
| 2350 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2351 | delta = 4; |
| 2352 | |
| 2353 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2354 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2355 | } |
| 2356 | |
| 2357 | for (c320c = -127; c320c <= 127; c320c++) { |
| 2358 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2359 | ctrl->timings[channel][slotrank].pi_coding = c320c; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2360 | } |
| 2361 | program_timings(ctrl, channel); |
| 2362 | reprogram_320c(ctrl); |
| 2363 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2364 | stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2365 | } |
| 2366 | } |
| 2367 | FOR_ALL_POPULATED_RANKS { |
| 2368 | struct run rn = |
| 2369 | get_longest_zero_run(stat[slotrank], 255); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2370 | ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2371 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2372 | channel, slotrank, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2373 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2374 | FOR_ALL_POPULATED_RANKS { |
| 2375 | ctrl->timings[channel][slotrank] = |
| 2376 | saved_timings[channel][slotrank]; |
| 2377 | } |
| 2378 | return MAKE_ERR; |
| 2379 | } |
| 2380 | } |
| 2381 | |
| 2382 | return 0; |
| 2383 | } |
| 2384 | |
| 2385 | /* Adjust CMD phase shift and try multiple command rates. |
| 2386 | * A command rate of 2T doubles the time needed for address and |
| 2387 | * command decode. */ |
| 2388 | int command_training(ramctr_timing *ctrl) |
| 2389 | { |
| 2390 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2391 | |
| 2392 | FOR_ALL_POPULATED_CHANNELS { |
| 2393 | fill_pattern5(ctrl, channel, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2394 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2395 | } |
| 2396 | |
| 2397 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2398 | int cmdrate, err; |
| 2399 | |
| 2400 | /* |
| 2401 | * Dual DIMM per channel: |
| 2402 | * Issue: While c320c discovery seems to succeed raminit |
| 2403 | * will fail in write training. |
| 2404 | * Workaround: Skip 1T in dual DIMM mode, that's only |
| 2405 | * supported by a few DIMMs. |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2406 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM |
| 2407 | * mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2408 | * |
| 2409 | * Single DIMM per channel: |
| 2410 | * Try command rate 1T and 2T |
| 2411 | */ |
| 2412 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2413 | if (ctrl->tCMD) |
| 2414 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2415 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2416 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2417 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2418 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2419 | |
| 2420 | if (!err) |
| 2421 | break; |
| 2422 | } |
| 2423 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2424 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2425 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2426 | return err; |
| 2427 | } |
| 2428 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2429 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2430 | } |
| 2431 | |
| 2432 | FOR_ALL_POPULATED_CHANNELS |
| 2433 | program_timings(ctrl, channel); |
| 2434 | |
| 2435 | reprogram_320c(ctrl); |
| 2436 | return 0; |
| 2437 | } |
| 2438 | |
| 2439 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2440 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2441 | { |
| 2442 | int edge; |
| 2443 | int statistics[NUM_LANES][MAX_EDGE_TIMING + 1]; |
| 2444 | int lane; |
| 2445 | |
| 2446 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2447 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2448 | ctrl->timings[channel][slotrank].lanes[lane].rising = edge; |
| 2449 | ctrl->timings[channel][slotrank].lanes[lane].falling = edge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2450 | } |
| 2451 | program_timings(ctrl, channel); |
| 2452 | |
| 2453 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2454 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2455 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2456 | } |
| 2457 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2458 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2459 | /* DRAM command MRS |
| 2460 | * write MR3 MPR enable |
| 2461 | * in this mode only RD and RDA are allowed |
| 2462 | * all reads return a predefined pattern */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2463 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; |
| 2464 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2465 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2466 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2467 | |
| 2468 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2469 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; |
| 2470 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x40411f4; |
| 2471 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
| 2472 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2473 | |
| 2474 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2475 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2476 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2477 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; |
| 2478 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2479 | |
| 2480 | /* DRAM command MRS |
| 2481 | * MR3 disable MPR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2482 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; |
| 2483 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2484 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2485 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2486 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2487 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2488 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2489 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2490 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2491 | |
| 2492 | FOR_ALL_LANES { |
| 2493 | statistics[lane][edge] = |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2494 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2495 | } |
| 2496 | } |
| 2497 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2498 | struct run rn = get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2499 | edges[lane] = rn.middle; |
| 2500 | if (rn.all) { |
| 2501 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", |
| 2502 | channel, slotrank, lane); |
| 2503 | return MAKE_ERR; |
| 2504 | } |
| 2505 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, |
| 2506 | lane, edges[lane]); |
| 2507 | } |
| 2508 | return 0; |
| 2509 | } |
| 2510 | |
| 2511 | int discover_edges(ramctr_timing *ctrl) |
| 2512 | { |
| 2513 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2514 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2515 | int channel, slotrank, lane; |
| 2516 | int err; |
| 2517 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2518 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2519 | |
| 2520 | toggle_io_reset(); |
| 2521 | |
| 2522 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2523 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2524 | } |
| 2525 | |
| 2526 | FOR_ALL_POPULATED_CHANNELS { |
| 2527 | fill_pattern0(ctrl, channel, 0, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2528 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2529 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2530 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2531 | } |
| 2532 | |
| 2533 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2534 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 2535 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2536 | } |
| 2537 | |
| 2538 | program_timings(ctrl, channel); |
| 2539 | |
| 2540 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2541 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2542 | |
| 2543 | /* DRAM command MRS |
| 2544 | * MR3 enable MPR |
| 2545 | * write MR3 MPR enable |
| 2546 | * in this mode only RD and RDA are allowed |
| 2547 | * all reads return a predefined pattern */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2548 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; |
| 2549 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2550 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2551 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2552 | (slotrank << 24) | 0x360004; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2553 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2554 | |
| 2555 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2556 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; |
| 2557 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 2558 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2559 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2560 | |
| 2561 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2562 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 2563 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2564 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2565 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2566 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2567 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2568 | |
| 2569 | /* DRAM command MRS |
| 2570 | * MR3 disable MPR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2571 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; |
| 2572 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2573 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2574 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2575 | (slotrank << 24) | 0x360000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2576 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2577 | |
| 2578 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2579 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2580 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2581 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2582 | } |
| 2583 | |
| 2584 | /* XXX: check any measured value ? */ |
| 2585 | |
| 2586 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2587 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 2588 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2589 | } |
| 2590 | |
| 2591 | program_timings(ctrl, channel); |
| 2592 | |
| 2593 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2594 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2595 | |
| 2596 | /* DRAM command MRS |
| 2597 | * MR3 enable MPR |
| 2598 | * write MR3 MPR enable |
| 2599 | * in this mode only RD and RDA are allowed |
| 2600 | * all reads return a predefined pattern */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2601 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; |
| 2602 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2603 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2604 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2605 | (slotrank << 24) | 0x360004; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2606 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2607 | |
| 2608 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2609 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; |
| 2610 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; |
| 2611 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 2612 | (slotrank << 24); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2613 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2614 | |
| 2615 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2616 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 2617 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2618 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2619 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2620 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2621 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2622 | |
| 2623 | /* DRAM command MRS |
| 2624 | * MR3 disable MPR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2625 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; |
| 2626 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2627 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2628 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2629 | (slotrank << 24) | 0x360000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2630 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2631 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2632 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2633 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2634 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2635 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2636 | } |
| 2637 | |
| 2638 | /* XXX: check any measured value ? */ |
| 2639 | |
| 2640 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2641 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2642 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2643 | } |
| 2644 | |
| 2645 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2646 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2647 | } |
| 2648 | |
| 2649 | /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2650 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2651 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2652 | |
| 2653 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2654 | err = discover_edges_real(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2655 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2656 | if (err) |
| 2657 | return err; |
| 2658 | } |
| 2659 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2660 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2661 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2662 | |
| 2663 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2664 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2665 | rising_edges[channel][slotrank]); |
| 2666 | if (err) |
| 2667 | return err; |
| 2668 | } |
| 2669 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2670 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2671 | |
| 2672 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2673 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2674 | falling_edges[channel][slotrank][lane]; |
| 2675 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2676 | rising_edges[channel][slotrank][lane]; |
| 2677 | } |
| 2678 | |
| 2679 | FOR_ALL_POPULATED_CHANNELS { |
| 2680 | program_timings(ctrl, channel); |
| 2681 | } |
| 2682 | |
| 2683 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2684 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2685 | } |
| 2686 | return 0; |
| 2687 | } |
| 2688 | |
| 2689 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, |
| 2690 | int slotrank, int *edges) |
| 2691 | { |
| 2692 | int edge; |
| 2693 | u32 raw_statistics[MAX_EDGE_TIMING + 1]; |
| 2694 | int statistics[MAX_EDGE_TIMING + 1]; |
| 2695 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2696 | int lane, i; |
| 2697 | int lower[NUM_LANES]; |
| 2698 | int upper[NUM_LANES]; |
| 2699 | int pat; |
| 2700 | |
| 2701 | FOR_ALL_LANES { |
| 2702 | lower[lane] = 0; |
| 2703 | upper[lane] = MAX_EDGE_TIMING; |
| 2704 | } |
| 2705 | |
| 2706 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2707 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2708 | printram("[%x] = 0x%08x\n", |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2709 | GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2710 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2711 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2712 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2713 | printram("using pattern %d\n", pat); |
| 2714 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2715 | FOR_ALL_LANES { |
| 2716 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2717 | rising = edge; |
| 2718 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2719 | falling = edge; |
| 2720 | } |
| 2721 | program_timings(ctrl, channel); |
| 2722 | |
| 2723 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2724 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2725 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2726 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2727 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2728 | |
| 2729 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2730 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; |
| 2731 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2732 | 0x4 | (ctrl->tRCD << 16) | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2733 | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2734 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2735 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2736 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2737 | |
| 2738 | /* DRAM command WR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2739 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; |
| 2740 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8005020 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2741 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2742 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2743 | slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2744 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2745 | |
| 2746 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2747 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
| 2748 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2749 | 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2750 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2751 | slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2752 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2753 | |
| 2754 | /* DRAM command PRE */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2755 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; |
| 2756 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2757 | 0xc01 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2758 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2759 | (slotrank << 24) | 0x60400; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2760 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2761 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2762 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2763 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = |
| 2764 | IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2765 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2766 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2767 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2768 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2769 | } |
| 2770 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2771 | raw_statistics[edge] = MCHBAR32(0x436c + channel * 0x400); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2772 | } |
| 2773 | FOR_ALL_LANES { |
| 2774 | struct run rn; |
| 2775 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
| 2776 | statistics[edge] = |
| 2777 | ! !(raw_statistics[edge] & (1 << lane)); |
| 2778 | rn = get_longest_zero_run(statistics, |
| 2779 | MAX_EDGE_TIMING + 1); |
| 2780 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", |
| 2781 | channel, slotrank, i, rn.start, rn.middle, |
| 2782 | rn.end, rn.start + ctrl->edge_offset[i], |
| 2783 | rn.end - ctrl->edge_offset[i]); |
| 2784 | lower[lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2785 | MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2786 | upper[lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2787 | MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2788 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2789 | if (rn.all || (lower[lane] > upper[lane])) { |
| 2790 | printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", |
| 2791 | channel, slotrank, lane); |
| 2792 | return MAKE_ERR; |
| 2793 | } |
| 2794 | } |
| 2795 | } |
| 2796 | } |
| 2797 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2798 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2799 | printram("CPA\n"); |
| 2800 | return 0; |
| 2801 | } |
| 2802 | |
| 2803 | int discover_edges_write(ramctr_timing *ctrl) |
| 2804 | { |
| 2805 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2806 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2807 | int channel, slotrank, lane; |
| 2808 | int err; |
| 2809 | |
| 2810 | /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2811 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2812 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2813 | |
| 2814 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2815 | err = discover_edges_write_real(ctrl, channel, slotrank, |
| 2816 | falling_edges[channel][slotrank]); |
| 2817 | if (err) |
| 2818 | return err; |
| 2819 | } |
| 2820 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2821 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2822 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2823 | |
| 2824 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2825 | err = discover_edges_write_real(ctrl, channel, slotrank, |
| 2826 | rising_edges[channel][slotrank]); |
| 2827 | if (err) |
| 2828 | return err; |
| 2829 | } |
| 2830 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2831 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2832 | |
| 2833 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2834 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2835 | falling_edges[channel][slotrank][lane]; |
| 2836 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2837 | rising_edges[channel][slotrank][lane]; |
| 2838 | } |
| 2839 | |
| 2840 | FOR_ALL_POPULATED_CHANNELS |
| 2841 | program_timings(ctrl, channel); |
| 2842 | |
| 2843 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2844 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2845 | } |
| 2846 | return 0; |
| 2847 | } |
| 2848 | |
| 2849 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2850 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2851 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2852 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2853 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; |
| 2854 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2855 | (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2856 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2857 | (slotrank << 24) | 0x60000; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2858 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2859 | |
| 2860 | /* DRAM command WR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2861 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; |
| 2862 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2863 | 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2864 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
| 2865 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2866 | |
| 2867 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2868 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2869 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2870 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; |
| 2871 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2872 | |
| 2873 | /* DRAM command PRE */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2874 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; |
| 2875 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); |
| 2876 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; |
| 2877 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2878 | |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2879 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2880 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2881 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2882 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2883 | } |
| 2884 | |
| 2885 | int discover_timC_write(ramctr_timing *ctrl) |
| 2886 | { |
| 2887 | const u8 rege3c_b24[3] = { 0, 0xf, 0x2f }; |
| 2888 | int i, pat; |
| 2889 | |
| 2890 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2891 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2892 | int channel, slotrank, lane; |
| 2893 | |
| 2894 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2895 | lower[channel][slotrank][lane] = 0; |
| 2896 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2897 | } |
| 2898 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2899 | /* |
| 2900 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2901 | * FIXME: This must only be done on Ivy Bridge. |
| 2902 | */ |
| 2903 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2904 | printram("discover timC write:\n"); |
| 2905 | |
| 2906 | for (i = 0; i < 3; i++) |
| 2907 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2908 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000, |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 2909 | rege3c_b24[i] << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2910 | udelay(2); |
| 2911 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2912 | FOR_ALL_POPULATED_RANKS { |
| 2913 | int timC; |
| 2914 | u32 raw_statistics[MAX_TIMC + 1]; |
| 2915 | int statistics[MAX_TIMC + 1]; |
| 2916 | |
| 2917 | /* Make sure rn.start < rn.end */ |
| 2918 | statistics[MAX_TIMC] = 1; |
| 2919 | |
| 2920 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2921 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2922 | 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2923 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2924 | FOR_ALL_LANES |
| 2925 | ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
| 2926 | program_timings(ctrl, channel); |
| 2927 | |
| 2928 | test_timC_write (ctrl, channel, slotrank); |
| 2929 | |
| 2930 | raw_statistics[timC] = |
Angel Pons | 1aba2a3 | 2020-01-05 22:31:41 +0100 | [diff] [blame] | 2931 | MCHBAR32(0x436c + channel * 0x400); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2932 | } |
| 2933 | FOR_ALL_LANES { |
| 2934 | struct run rn; |
| 2935 | for (timC = 0; timC < MAX_TIMC; timC++) |
| 2936 | statistics[timC] = |
| 2937 | !!(raw_statistics[timC] & |
| 2938 | (1 << lane)); |
| 2939 | |
| 2940 | rn = get_longest_zero_run(statistics, |
| 2941 | MAX_TIMC + 1); |
| 2942 | if (rn.all) { |
| 2943 | printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", |
| 2944 | channel, slotrank, lane); |
| 2945 | return MAKE_ERR; |
| 2946 | } |
| 2947 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", |
| 2948 | channel, slotrank, i, rn.start, |
| 2949 | rn.middle, rn.end, |
| 2950 | rn.start + ctrl->timC_offset[i], |
| 2951 | rn.end - ctrl->timC_offset[i]); |
| 2952 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2953 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2954 | lower[channel][slotrank][lane]); |
| 2955 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2956 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2957 | upper[channel][slotrank][lane]); |
| 2958 | |
| 2959 | } |
| 2960 | } |
| 2961 | } |
| 2962 | } |
| 2963 | |
| 2964 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2965 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2966 | udelay(2); |
| 2967 | } |
| 2968 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2969 | /* |
| 2970 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2971 | * FIXME: This must only be done on Ivy Bridge. |
| 2972 | */ |
| 2973 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2974 | |
| 2975 | printram("CPB\n"); |
| 2976 | |
| 2977 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2978 | printram("timC %d, %d, %d: %x\n", channel, |
| 2979 | slotrank, lane, |
| 2980 | (lower[channel][slotrank][lane] + |
| 2981 | upper[channel][slotrank][lane]) / 2); |
| 2982 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2983 | (lower[channel][slotrank][lane] + |
| 2984 | upper[channel][slotrank][lane]) / 2; |
| 2985 | } |
| 2986 | FOR_ALL_POPULATED_CHANNELS { |
| 2987 | program_timings(ctrl, channel); |
| 2988 | } |
| 2989 | return 0; |
| 2990 | } |
| 2991 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2992 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2993 | { |
| 2994 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2995 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2996 | |
| 2997 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2998 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2999 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3000 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 3001 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 3002 | printram("normalize %d, %d, %d: mat %d\n", |
| 3003 | channel, slotrank, lane, mat); |
| 3004 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 3005 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 3006 | printram("normalize %d, %d, %d: delta %d\n", |
| 3007 | channel, slotrank, lane, delta); |
| 3008 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3009 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 3010 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3011 | } |
| 3012 | |
| 3013 | FOR_ALL_POPULATED_CHANNELS { |
| 3014 | program_timings(ctrl, channel); |
| 3015 | } |
| 3016 | } |
| 3017 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3018 | void write_controller_mr(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3019 | { |
| 3020 | int channel, slotrank; |
| 3021 | |
| 3022 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 3023 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 3024 | make_mr0(ctrl, slotrank); |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame^] | 3025 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 3026 | make_mr1(ctrl, slotrank, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3027 | } |
| 3028 | } |
| 3029 | |
| 3030 | int channel_test(ramctr_timing *ctrl) |
| 3031 | { |
| 3032 | int channel, slotrank, lane; |
| 3033 | |
| 3034 | slotrank = 0; |
| 3035 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3036 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3037 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3038 | return MAKE_ERR; |
| 3039 | } |
| 3040 | FOR_ALL_POPULATED_CHANNELS { |
| 3041 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
| 3042 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3043 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3044 | } |
| 3045 | |
| 3046 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 3047 | FOR_ALL_CHANNELS |
| 3048 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 3049 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3050 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 3051 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3052 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3053 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3054 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3055 | /* DRAM command ACT */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3056 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0001f006; |
| 3057 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x0028a004; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3058 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3059 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x00000244; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3060 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3061 | /* DRAM command WR */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3062 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x0001f201; |
| 3063 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x08281064; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 3064 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3065 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x00000242; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3066 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3067 | /* DRAM command RD */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3068 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0001f105; |
| 3069 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x04281064; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 3070 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3071 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x00000242; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3072 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3073 | /* DRAM command PRE */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3074 | MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x0001f002; |
| 3075 | MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x00280c01; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3076 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3077 | MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x00000240; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3078 | |
| 3079 | // execute command queue |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3080 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3081 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3082 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3083 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3084 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3085 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 3086 | channel, slotrank, lane); |
| 3087 | return MAKE_ERR; |
| 3088 | } |
| 3089 | } |
| 3090 | return 0; |
| 3091 | } |
| 3092 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3093 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3094 | { |
| 3095 | int channel; |
| 3096 | |
| 3097 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? |
| 3098 | I don't think so. */ |
| 3099 | static u32 seeds[NUM_CHANNELS][3] = { |
| 3100 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 3101 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 3102 | }; |
| 3103 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3104 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; |
| 3105 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 3106 | MCHBAR32(SCRAMBLING_SEED_2_HIGH_ch(channel)) = seeds[channel][1]; |
| 3107 | MCHBAR32(SCRAMBLING_SEED_2_LOW_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3108 | } |
| 3109 | } |
| 3110 | |
| 3111 | void set_4f8c(void) |
| 3112 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3113 | u32 cpu; |
| 3114 | |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 3115 | cpu = cpu_get_cpuid(); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3116 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3117 | MCHBAR32(SC_WDBWM) = 0x141D1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3118 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3119 | MCHBAR32(SC_WDBWM) = 0x551D1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3120 | } |
| 3121 | } |
| 3122 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3123 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3124 | { |
| 3125 | int channel; |
| 3126 | |
| 3127 | FOR_ALL_POPULATED_CHANNELS { |
| 3128 | // Always drive command bus |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3129 | MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3130 | } |
| 3131 | |
| 3132 | udelay(1); |
| 3133 | |
| 3134 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3135 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3136 | } |
| 3137 | } |
| 3138 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3139 | void set_4008c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3140 | { |
| 3141 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3142 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3143 | FOR_ALL_POPULATED_CHANNELS { |
| 3144 | u32 b20, b4_8_12; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3145 | int min_pi = 10000; |
| 3146 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3147 | |
| 3148 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3149 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 3150 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3151 | } |
| 3152 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3153 | if (max_pi - min_pi > 51) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3154 | b20 = 0; |
| 3155 | else |
| 3156 | b20 = ctrl->ref_card_offset[channel]; |
| 3157 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3158 | if (ctrl->pi_coding_threshold < max_pi - min_pi) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3159 | b4_8_12 = 0x3330; |
| 3160 | else |
| 3161 | b4_8_12 = 0x2220; |
| 3162 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3163 | dram_odt_stretch(ctrl, channel); |
| 3164 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3165 | MCHBAR32(TC_RWP_ch(channel)) = |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 3166 | 0x0a000000 | (b20 << 20) | |
| 3167 | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3168 | } |
| 3169 | } |
| 3170 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3171 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3172 | { |
| 3173 | int channel; |
| 3174 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3175 | MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; |
| 3176 | MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3177 | } |
| 3178 | } |
| 3179 | |
| 3180 | static int encode_5d10(int ns) |
| 3181 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3182 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3183 | } |
| 3184 | |
| 3185 | /* FIXME: values in this function should be hardware revision-dependent. */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3186 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3187 | { |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3188 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
| 3189 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3190 | int channel; |
| 3191 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 3192 | int t3_ns; |
| 3193 | u32 r32; |
| 3194 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3195 | /* FIXME: This register only exists on Ivy Bridge. */ |
| 3196 | MCHBAR32(WMM_READ_CONFIG) = 0x00000046; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3197 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3198 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3199 | MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xFFFFCFFF, 0x1000); |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3200 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3201 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3202 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3203 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3204 | else |
| 3205 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3206 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3207 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3208 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3209 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3210 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3211 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 3212 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3213 | |
| 3214 | FOR_ALL_CHANNELS { |
| 3215 | switch (ctrl->rankmap[channel]) { |
| 3216 | /* Unpopulated channel. */ |
| 3217 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3218 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3219 | break; |
| 3220 | /* Only single-ranked dimms. */ |
| 3221 | case 1: |
| 3222 | case 4: |
| 3223 | case 5: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3224 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3225 | break; |
| 3226 | /* Dual-ranked dimms present. */ |
| 3227 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3228 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x9b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3229 | break; |
| 3230 | } |
| 3231 | } |
| 3232 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3233 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
| 3234 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0xffffff, 0xe4d5d0); |
| 3235 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3236 | |
| 3237 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3238 | MCHBAR32_AND_OR(TC_RFP_ch(channel), ~0x30000, 1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3239 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3240 | MCHBAR32_OR(MC_INIT_STATE_G, 1); |
| 3241 | MCHBAR32_OR(MC_INIT_STATE_G, 0x80); |
| 3242 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3243 | |
| 3244 | /* Find a populated channel. */ |
| 3245 | FOR_ALL_POPULATED_CHANNELS |
| 3246 | break; |
| 3247 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3248 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 3249 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3250 | if (r32 & 0x20000) |
| 3251 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3252 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3253 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
| 3254 | if (!(r32 & 0x20000)) |
| 3255 | t1_ns += 500; |
| 3256 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3257 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3258 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3259 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
| 3260 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3261 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3262 | t3_ns = 500; |
| 3263 | } |
| 3264 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", |
| 3265 | t1_ns, t2_ns, t3_ns); |
Felix Held | b802c07 | 2018-07-29 21:46:19 +0200 | [diff] [blame] | 3266 | MCHBAR32_AND_OR(0x5d10, 0xC0C0C0C0, |
| 3267 | ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 3268 | (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + |
Felix Held | b802c07 | 2018-07-29 21:46:19 +0200 | [diff] [blame] | 3269 | encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | 0xc); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3270 | } |
| 3271 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3272 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3273 | { |
| 3274 | int channel, slotrank, lane; |
| 3275 | |
| 3276 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3277 | MCHBAR32(TC_RAP_ch(channel)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3278 | ctrl->tRRD |
| 3279 | | (ctrl->tRTP << 4) |
| 3280 | | (ctrl->tCKE << 8) |
| 3281 | | (ctrl->tWTR << 12) |
| 3282 | | (ctrl->tFAW << 16) |
| 3283 | | (ctrl->tWR << 24) |
| 3284 | | (ctrl->cmd_stretch[channel] << 30); |
| 3285 | |
| 3286 | udelay(1); |
| 3287 | |
| 3288 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3289 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3290 | } |
| 3291 | |
| 3292 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3293 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3294 | } |
| 3295 | |
| 3296 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3297 | MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3298 | |
| 3299 | FOR_ALL_POPULATED_CHANNELS { |
| 3300 | udelay (1); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3301 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3302 | } |
| 3303 | |
| 3304 | printram("CPE\n"); |
| 3305 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3306 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 3307 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3308 | |
| 3309 | printram("CP5b\n"); |
| 3310 | |
| 3311 | FOR_ALL_POPULATED_CHANNELS { |
| 3312 | program_timings(ctrl, channel); |
| 3313 | } |
| 3314 | |
| 3315 | u32 reg, addr; |
| 3316 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3317 | while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3318 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3319 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3320 | } while ((reg & 0x14) == 0); |
| 3321 | |
| 3322 | // Set state of memory controller |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3323 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
| 3324 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3325 | |
| 3326 | // Wait 500us |
| 3327 | udelay(500); |
| 3328 | |
| 3329 | FOR_ALL_CHANNELS { |
| 3330 | // Set valid rank CKE |
| 3331 | reg = 0; |
| 3332 | reg = (reg & ~0xf) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3333 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3334 | MCHBAR32(addr) = reg; |
| 3335 | |
| 3336 | // Wait 10ns for ranks to settle |
| 3337 | //udelay(0.01); |
| 3338 | |
| 3339 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3340 | MCHBAR32(addr) = reg; |
| 3341 | |
| 3342 | // Write reset using a NOP |
| 3343 | write_reset(ctrl); |
| 3344 | } |
| 3345 | |
| 3346 | /* mrs commands. */ |
| 3347 | dram_mrscommands(ctrl); |
| 3348 | |
| 3349 | printram("CP5c\n"); |
| 3350 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3351 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3352 | |
| 3353 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3354 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3355 | udelay(2); |
| 3356 | } |
| 3357 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3358 | /* |
| 3359 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 3360 | * FIXME: This must only be done on Ivy Bridge. Moreover, this instance seems to be |
| 3361 | * spurious, because nothing else enabled this optimization before. |
| 3362 | */ |
| 3363 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3364 | } |