nb/intel/sandybridge: Always wait for IOSAV after starting it
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 9308ed5..ccf2403 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -680,7 +680,7 @@
};
iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence));
- iosav_run_once(channel);
+ iosav_run_once_and_wait(channel);
}
/* Obtain optimal power down mode for current configuration */
@@ -1332,7 +1332,7 @@
iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0);
- iosav_run_once(channel);
+ iosav_run_once_and_wait(channel);
const union gdcr_training_mod_reg training_mod = {
.receive_enable_mode = 1,
@@ -1460,7 +1460,7 @@
iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18);
- iosav_run_once(channel);
+ iosav_run_once_and_wait(channel);
for (tx_dq = 0; tx_dq <= MAX_TX_DQ; tx_dq++) {
FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].tx_dq = tx_dq;