nb/intel/sandybridge: Correct TC_DTP handling
It is only for Ivy Bridge, and needs to be set on certain circumstances.
Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 620c574..9e27400 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -216,8 +216,22 @@
printram("OTHP [%x] = %x\n", addr, reg);
MCHBAR32(addr) = reg;
- /* FIXME: This register only exists on Ivy Bridge! */
- MCHBAR32(TC_DTP_ch(channel)) = 0;
+ /* Debug parameters - only applies to Ivy Bridge */
+ if (IS_IVY_CPU(ctrl->cpu)) {
+ reg = 0;
+
+ /*
+ * If tXP and tXPDLL are very high, we need to increase them by one.
+ * This can only happen on Ivy Bridge, and when overclocking the RAM.
+ */
+ if (ctrl->tXP >= 8)
+ reg |= (1 << 12);
+
+ if (ctrl->tXPDLL >= 32)
+ reg |= (1 << 13);
+
+ MCHBAR32(TC_DTP_ch(channel)) = reg;
+ }
MCHBAR32_OR(addr, 0x00020000);