| commit | 4d192820cd22b019b916cbaab16f0384c661038d | [log] [tgz] |
|---|---|---|
| author | Angel Pons <th3fanbus@gmail.com> | Sat Dec 12 13:54:37 2020 +0100 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Wed Dec 23 16:05:06 2020 +0000 |
| tree | fea02ac8c8a504dccde4bc5ac45858b9766a369b | |
| parent | 30791639f88b2256000bb03733c3cbab7677795b [diff] [blame] |
nb/intel/sandybridge: Add comment to TC_RWP write Change-Id: I164daa59696f2fe8de3a4b3e7da46c7c723778eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48602 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9b364ab..a21caea 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1885,6 +1885,10 @@ int channel, slotrank; int err; + /* + * Set the DEC_WRD bit, required for the write flyby algorithm. + * Needs to be done before starting the write training procedure. + */ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);