Martin Roth | 5bdac84 | 2024-02-16 10:45:54 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 3 | config SOUTHBRIDGE_INTEL_COMMON_RESET |
Arthur Heymans | 23a6c79 | 2019-10-13 22:36:04 +0200 | [diff] [blame] | 4 | def_bool n |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 5 | select HAVE_CF9_RESET |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 6 | |
Arthur Heymans | 074730c | 2019-06-04 14:05:53 +0200 | [diff] [blame] | 7 | config SOUTHBRIDGE_INTEL_COMMON_RTC |
| 8 | def_bool n |
Arthur Heymans | 074730c | 2019-06-04 14:05:53 +0200 | [diff] [blame] | 9 | |
Patrick Rudolph | 1ae592b | 2019-03-24 14:41:45 +0100 | [diff] [blame] | 10 | config SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
| 11 | def_bool n |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame] | 12 | depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE |
| 13 | |
| 14 | config SOUTHBRIDGE_INTEL_COMMON_PMBASE |
| 15 | def_bool n |
Patrick Rudolph | 1ae592b | 2019-03-24 14:41:45 +0100 | [diff] [blame] | 16 | |
Patrick Rudolph | 59de6c9 | 2015-12-26 08:33:16 +0100 | [diff] [blame] | 17 | config SOUTHBRIDGE_INTEL_COMMON_GPIO |
| 18 | def_bool n |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 19 | |
Angel Pons | 20a609f | 2021-02-06 23:22:33 +0100 | [diff] [blame] | 20 | config SOUTHBRIDGE_INTEL_COMMON_ME |
| 21 | def_bool n |
| 22 | |
Angel Pons | eef4343 | 2021-01-12 22:25:28 +0100 | [diff] [blame] | 23 | config SOUTHBRIDGE_INTEL_COMMON_HPET |
| 24 | def_bool n |
| 25 | |
Angel Pons | 90e9f54 | 2020-06-01 19:31:53 +0200 | [diff] [blame] | 26 | config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS |
| 27 | def_bool n |
| 28 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 29 | config SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 30 | def_bool n |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 31 | select HAVE_DEBUG_SMBUS |
| 32 | |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 33 | config SOUTHBRIDGE_INTEL_COMMON_SPI |
| 34 | def_bool n |
| 35 | select SPI_FLASH |
Arthur Heymans | 4c80425 | 2018-12-03 01:28:18 +0100 | [diff] [blame] | 36 | select BOOT_DEVICE_SUPPORTS_WRITES |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 37 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 38 | config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 |
| 39 | def_bool n |
| 40 | select SOUTHBRIDGE_INTEL_COMMON_SPI |
| 41 | |
| 42 | config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
| 43 | def_bool n |
| 44 | select SOUTHBRIDGE_INTEL_COMMON_SPI |
| 45 | |
| 46 | config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT |
| 47 | def_bool n |
| 48 | select SOUTHBRIDGE_INTEL_COMMON_SPI |
| 49 | |
Tobias Diedrich | 9d8be5a | 2017-12-13 23:25:32 +0100 | [diff] [blame] | 50 | config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 51 | def_bool n |
| 52 | |
| 53 | config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| 54 | def_bool n |
| 55 | select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 56 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 57 | config HAVE_INTEL_CHIPSET_LOCKDOWN |
| 58 | def_bool n |
| 59 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 60 | config SOUTHBRIDGE_INTEL_COMMON_SMM |
| 61 | def_bool n |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 62 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 63 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
Kyösti Mälkki | 8647153 | 2023-04-21 21:43:24 +0300 | [diff] [blame] | 64 | depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 65 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 66 | config SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| 67 | bool |
| 68 | |
Arthur Heymans | 3457df1 | 2019-11-16 10:04:41 +0100 | [diff] [blame] | 69 | config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG |
| 70 | def_bool n |
| 71 | select HAVE_USBDEBUG |
| 72 | |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 73 | config INTEL_DESCRIPTOR_MODE_CAPABLE |
| 74 | def_bool n |
| 75 | help |
| 76 | This config simply states that the platform is *capable* of running in |
| 77 | descriptor mode (when the descriptor in flash is valid). |
| 78 | |
Angel Pons | a52016c | 2018-09-11 13:49:45 +0200 | [diff] [blame] | 79 | config INTEL_DESCRIPTOR_MODE_REQUIRED |
| 80 | def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE |
| 81 | help |
| 82 | This config states descriptor mode is *required* for the platform to |
| 83 | function properly, or to function at all. |
| 84 | |
Mathew King | d8b150f | 2019-08-09 10:55:37 -0600 | [diff] [blame] | 85 | config VALIDATE_INTEL_DESCRIPTOR |
| 86 | depends on INTEL_DESCRIPTOR_MODE_CAPABLE |
| 87 | bool "Validate Intel firmware descriptor" |
| 88 | default n |
| 89 | help |
| 90 | This config enables validating the Intel firmware descriptor against the |
| 91 | fmap layout. If the firmware descriptor layout does not match the fmap |
| 92 | then the bootimage cannot be built. |
| 93 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 94 | config INTEL_CHIPSET_LOCKDOWN |
| 95 | depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS |
| 96 | #ChromeOS's payload seems to handle finalization on its on. |
| 97 | bool "Lock down chipset in coreboot" |
| 98 | default y |
| 99 | help |
| 100 | Some registers within host bridge on particular chipsets should be |
| 101 | locked down on each normal boot path (done by either coreboot or payload) |
| 102 | and S3 resume (always done by coreboot). Select this to let coreboot |
| 103 | to do this on normal boot path. |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 104 | |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 105 | config TCO_SPACE_NOT_YET_SPLIT |
| 106 | bool |
| 107 | |
Elyes HAOUAS | 551a759 | 2019-05-01 16:56:36 +0200 | [diff] [blame] | 108 | config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG |
| 109 | bool |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame] | 110 | depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 111 | |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 112 | config FIXED_RCBA_MMIO_BASE |
| 113 | hex |
| 114 | default 0xfed1c000 |
| 115 | |
Angel Pons | b70ff52 | 2021-01-28 14:27:46 +0100 | [diff] [blame] | 116 | config RCBA_LENGTH |
| 117 | hex |
| 118 | default 0x4000 |
| 119 | |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 120 | config FIXED_SMBUS_IO_BASE |
| 121 | hex |
| 122 | depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 123 | default 0x400 |