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review.coreboot.org / coreboot / 31402178c56108e752b95c34562b6e3554a2c1d8 / . / src / southbridge / intel / common / Kconfig.common
blob: c621399785c297aff4a0ba57f5c8acd5ce586bfe [file] [log] [blame]
Martin Roth5bdac842024-02-16 10:45:54 -0700[diff] [blame]1## SPDX-License-Identifier: GPL-2.0-only
2
Patrick Rudolph45022ae2018-10-01 19:17:11 +0200[diff] [blame]3config SOUTHBRIDGE_INTEL_COMMON_RESET
Arthur Heymans23a6c792019-10-13 22:36:04 +0200[diff] [blame]4 def_bool n
Patrick Rudolph45022ae2018-10-01 19:17:11 +0200[diff] [blame]5 select HAVE_CF9_RESET
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]6
Arthur Heymans074730c2019-06-04 14:05:53 +0200[diff] [blame]7config SOUTHBRIDGE_INTEL_COMMON_RTC
8 def_bool n
Arthur Heymans074730c2019-06-04 14:05:53 +0200[diff] [blame]9
Patrick Rudolph1ae592b2019-03-24 14:41:45 +0100[diff] [blame]10config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
11 def_bool n
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]12 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
13
14config SOUTHBRIDGE_INTEL_COMMON_PMBASE
15 def_bool n
Patrick Rudolph1ae592b2019-03-24 14:41:45 +0100[diff] [blame]16
Patrick Rudolph59de6c92015-12-26 08:33:16 +0100[diff] [blame]17config SOUTHBRIDGE_INTEL_COMMON_GPIO
18 def_bool n
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]19
Angel Pons20a609f2021-02-06 23:22:33 +0100[diff] [blame]20config SOUTHBRIDGE_INTEL_COMMON_ME
21 def_bool n
22
Angel Ponseef43432021-01-12 22:25:28 +0100[diff] [blame]23config SOUTHBRIDGE_INTEL_COMMON_HPET
24 def_bool n
25
Angel Pons90e9f542020-06-01 19:31:53 +0200[diff] [blame]26config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
27 def_bool n
28
Arthur Heymans16fe7902017-04-12 17:01:31 +0200[diff] [blame]29config SOUTHBRIDGE_INTEL_COMMON_SMBUS
30 def_bool n
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]31 select HAVE_DEBUG_SMBUS
32
Arthur Heymansbddef0d2017-09-25 12:21:07 +0200[diff] [blame]33config SOUTHBRIDGE_INTEL_COMMON_SPI
34 def_bool n
35 select SPI_FLASH
Arthur Heymans4c804252018-12-03 01:28:18 +0100[diff] [blame]36 select BOOT_DEVICE_SUPPORTS_WRITES
Arthur Heymansbddef0d2017-09-25 12:21:07 +0200[diff] [blame]37
Arthur Heymans47a66032019-10-25 23:43:14 +0200[diff] [blame]38config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7
39 def_bool n
40 select SOUTHBRIDGE_INTEL_COMMON_SPI
41
42config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
43 def_bool n
44 select SOUTHBRIDGE_INTEL_COMMON_SPI
45
46config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
47 def_bool n
48 select SOUTHBRIDGE_INTEL_COMMON_SPI
49
Tobias Diedrich9d8be5a2017-12-13 23:25:32 +0100[diff] [blame]50config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
51 def_bool n
52
53config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
54 def_bool n
55 select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
56
Bill XIEd533b162017-08-22 16:26:22 +0800[diff] [blame]57config HAVE_INTEL_CHIPSET_LOCKDOWN
58 def_bool n
59
Arthur Heymansa0508172018-01-25 11:30:22 +0100[diff] [blame]60config SOUTHBRIDGE_INTEL_COMMON_SMM
61 def_bool n
Nico Huber9faae2b2018-11-14 00:00:35 +0100[diff] [blame]62 select HAVE_POWER_STATE_AFTER_FAILURE
63 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Kyösti Mälkki86471532023-04-21 21:43:24 +0300[diff] [blame]64 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
Arthur Heymansa0508172018-01-25 11:30:22 +0100[diff] [blame]65
Tristan Corrick63626b12018-11-30 22:53:50 +1300[diff] [blame]66config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
67 bool
68
Arthur Heymans3457df12019-11-16 10:04:41 +0100[diff] [blame]69config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
70 def_bool n
71 select HAVE_USBDEBUG
72
Stefan Tauneref8b9572018-09-06 00:34:28 +0200[diff] [blame]73config INTEL_DESCRIPTOR_MODE_CAPABLE
74 def_bool n
75 help
76 This config simply states that the platform is *capable* of running in
77 descriptor mode (when the descriptor in flash is valid).
78
Angel Ponsa52016c2018-09-11 13:49:45 +0200[diff] [blame]79config INTEL_DESCRIPTOR_MODE_REQUIRED
80 def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE
81 help
82 This config states descriptor mode is *required* for the platform to
83 function properly, or to function at all.
84
Mathew Kingd8b150f2019-08-09 10:55:37 -0600[diff] [blame]85config VALIDATE_INTEL_DESCRIPTOR
86 depends on INTEL_DESCRIPTOR_MODE_CAPABLE
87 bool "Validate Intel firmware descriptor"
88 default n
89 help
90 This config enables validating the Intel firmware descriptor against the
91 fmap layout. If the firmware descriptor layout does not match the fmap
92 then the bootimage cannot be built.
93
Bill XIEd533b162017-08-22 16:26:22 +0800[diff] [blame]94config INTEL_CHIPSET_LOCKDOWN
95 depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
96 #ChromeOS's payload seems to handle finalization on its on.
97 bool "Lock down chipset in coreboot"
98 default y
99 help
100 Some registers within host bridge on particular chipsets should be
101 locked down on each normal boot path (done by either coreboot or payload)
102 and S3 resume (always done by coreboot). Select this to let coreboot
103 to do this on normal boot path.
Tristan Corrick63626b12018-11-30 22:53:50 +1300[diff] [blame]104
Kyösti Mälkkie8a3af12022-11-19 18:39:22 +0200[diff] [blame]105config TCO_SPACE_NOT_YET_SPLIT
106 bool
107
Elyes HAOUAS551a7592019-05-01 16:56:36 +0200[diff] [blame]108config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
109 bool
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]110 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
Angel Ponsb21bffa2020-07-03 01:02:28 +0200[diff] [blame]111
Angel Pons6e732d32021-01-28 13:56:18 +0100[diff] [blame]112config FIXED_RCBA_MMIO_BASE
113 hex
114 default 0xfed1c000
115
Angel Ponsb70ff522021-01-28 14:27:46 +0100[diff] [blame]116config RCBA_LENGTH
117 hex
118 default 0x4000
119
Angel Ponsb21bffa2020-07-03 01:02:28 +0200[diff] [blame]120config FIXED_SMBUS_IO_BASE
121 hex
122 depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
123 default 0x400