Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
Felix Held | 390a280 | 2021-10-21 03:13:42 +0200 | [diff] [blame] | 3 | #include <arch/ioapic.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pnp.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
| 9 | #include <device/pci_def.h> |
| 10 | #include <pc80/mc146818rtc.h> |
| 11 | #include <pc80/isa-dma.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 12 | #include <pc80/i8254.h> |
| 13 | #include <pc80/i8259.h> |
Raul E Rangel | 0f3bc81 | 2021-02-10 16:36:33 -0700 | [diff] [blame] | 14 | #include <amdblocks/acpi.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 15 | #include <amdblocks/acpimmio.h> |
Furquan Shaikh | 511aa44 | 2020-05-04 23:42:46 -0700 | [diff] [blame] | 16 | #include <amdblocks/espi.h> |
Felix Held | 390a280 | 2021-10-21 03:13:42 +0200 | [diff] [blame] | 17 | #include <amdblocks/ioapic.h> |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 18 | #include <amdblocks/iomap.h> |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 19 | #include <amdblocks/lpc.h> |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 20 | #include <soc/iomap.h> |
Raul E Rangel | 466edb5 | 2021-02-09 11:24:13 -0700 | [diff] [blame] | 21 | #include <soc/lpc.h> |
| 22 | #include <soc/southbridge.h> |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 23 | |
Marshall Dawson | 8d9b878 | 2020-06-29 17:56:02 -0600 | [diff] [blame] | 24 | static void setup_serirq(void) |
| 25 | { |
| 26 | u8 byte; |
| 27 | |
| 28 | /* Set up SERIRQ, enable continuous mode */ |
Raul E Rangel | a91eb90 | 2021-02-24 16:26:34 -0700 | [diff] [blame] | 29 | byte = PM_SERIRQ_NUM_BITS_21; |
| 30 | if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) |
| 31 | byte |= PM_SERIRQ_ENABLE; |
Marshall Dawson | 8d9b878 | 2020-06-29 17:56:02 -0600 | [diff] [blame] | 32 | if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) |
| 33 | byte |= PM_SERIRQ_MODE; |
| 34 | |
| 35 | pm_write8(PM_SERIRQ_CONF, byte); |
| 36 | } |
| 37 | |
Felix Held | 390a280 | 2021-10-21 03:13:42 +0200 | [diff] [blame] | 38 | static void fch_ioapic_init(void) |
| 39 | { |
| 40 | fch_enable_ioapic_decode(); |
| 41 | setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID); |
| 42 | } |
| 43 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 44 | static void lpc_init(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 45 | { |
| 46 | u8 byte; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 47 | |
| 48 | /* Initialize isa dma */ |
| 49 | isa_dma_init(); |
| 50 | |
| 51 | /* Enable DMA transaction on the LPC bus */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 52 | byte = pci_read_config8(dev, LPC_PCI_CONTROL); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 53 | byte |= LEGACY_DMA_EN; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 54 | pci_write_config8(dev, LPC_PCI_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 55 | |
| 56 | /* Disable the timeout mechanism on LPC */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 57 | byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 58 | byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 59 | pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 60 | |
| 61 | /* Disable LPC MSI Capability */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 62 | byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 63 | /* BIT 1 is not defined in public datasheet. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 64 | byte &= ~(1 << 1); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 65 | |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 66 | pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 67 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 68 | /* |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 69 | * Enable hand-instance of the pulse generator and SPI prefetch from |
| 70 | * host (earlier is recommended for boot speed). |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 71 | */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 72 | byte = pci_read_config8(dev, LPC_HOST_CONTROL); |
Richard Spiegel | ee09878 | 2018-07-30 12:05:22 -0700 | [diff] [blame] | 73 | byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 74 | pci_write_config8(dev, LPC_HOST_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 75 | |
| 76 | cmos_check_update_date(); |
| 77 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 78 | /* |
| 79 | * Initialize the real time clock. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 80 | * The 0 argument tells cmos_init not to |
| 81 | * update CMOS unless it is invalid. |
| 82 | * 1 tells cmos_init to always initialize the CMOS. |
| 83 | */ |
Aaron Durbin | 9fde0d7 | 2017-09-15 11:01:17 -0600 | [diff] [blame] | 84 | cmos_init(0); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 85 | |
| 86 | /* Initialize i8259 pic */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 87 | setup_i8259(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 88 | |
| 89 | /* Initialize i8254 timers */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 90 | setup_i8254(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 91 | |
Raul E Rangel | a91eb90 | 2021-02-24 16:26:34 -0700 | [diff] [blame] | 92 | setup_serirq(); |
Felix Held | 390a280 | 2021-10-21 03:13:42 +0200 | [diff] [blame] | 93 | |
| 94 | fch_ioapic_init(); |
| 95 | fch_configure_hpet(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 96 | } |
| 97 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 98 | static void lpc_read_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 99 | { |
| 100 | struct resource *res; |
| 101 | |
| 102 | /* Get the normal pci resources of this device */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 103 | pci_dev_read_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 104 | |
| 105 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 106 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 107 | res->base = 0; |
| 108 | res->size = 0x1000; |
| 109 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 110 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 111 | |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 112 | /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 113 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 114 | res->base = FLASH_BELOW_4GB_MAPPING_REGION_BASE; |
| 115 | res->size = FLASH_BELOW_4GB_MAPPING_REGION_SIZE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 116 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 117 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 118 | |
| 119 | /* Add a memory resource for the SPI BAR. */ |
Kyösti Mälkki | 8b89424 | 2022-05-26 15:42:59 +0300 | [diff] [blame] | 120 | mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 121 | |
| 122 | res = new_resource(dev, 3); /* IOAPIC */ |
| 123 | res->base = IO_APIC_ADDR; |
| 124 | res->size = 0x00001000; |
| 125 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 126 | |
| 127 | compact_resources(dev); |
| 128 | } |
| 129 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 130 | static void lpc_set_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 131 | { |
| 132 | struct resource *res; |
| 133 | u32 spi_enable_bits; |
| 134 | |
| 135 | /* Special case. The SpiRomEnable and other enables should STAY set. */ |
| 136 | res = find_resource(dev, 2); |
Felix Held | 697fa74 | 2022-03-03 20:54:38 +0100 | [diff] [blame] | 137 | spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER); |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 138 | spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; |
Felix Held | 697fa74 | 2022-03-03 20:54:38 +0100 | [diff] [blame] | 139 | pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER, |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 140 | res->base | spi_enable_bits); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 141 | |
| 142 | pci_dev_set_resources(dev); |
| 143 | } |
| 144 | |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 145 | static void configure_child_lpc_windows(struct device *dev, struct device *child) |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 146 | { |
| 147 | struct resource *res; |
| 148 | u32 base, end; |
| 149 | u32 rsize = 0, set = 0, set_x = 0; |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 150 | int wideio_index; |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 151 | u32 reg, reg_x; |
| 152 | |
| 153 | reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); |
| 154 | reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 155 | |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 156 | /* |
| 157 | * Be a bit relaxed, tolerate that LPC region might be bigger than |
| 158 | * resource we try to fit, do it like this for all regions < 16 bytes. |
| 159 | * If there is a resource > 16 bytes it must be 512 bytes to be able |
| 160 | * to allocate the fresh LPC window. |
| 161 | * |
| 162 | * AGESA and early initialization can set a wide IO port. This code |
| 163 | * will verify if required region was previously set and will avoid |
| 164 | * setting a new wide IO resource if one is already set. |
| 165 | */ |
| 166 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 167 | for (res = child->resource_list; res; res = res->next) { |
| 168 | if (!(res->flags & IORESOURCE_IO)) |
| 169 | continue; |
| 170 | base = res->base; |
| 171 | end = resource_end(res); |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 172 | printk(BIOS_DEBUG, |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 173 | "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", |
| 174 | dev_path(child), base, end); |
| 175 | /* find a resource size */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 176 | switch (base) { |
| 177 | case 0x60: /* KB */ |
| 178 | case 0x64: /* MS */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 179 | set |= DECODE_ENABLE_KBC_PORT; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 180 | rsize = 1; |
| 181 | break; |
| 182 | case 0x3f8: /* COM1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 183 | set |= DECODE_ENABLE_SERIAL_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 184 | rsize = 8; |
| 185 | break; |
| 186 | case 0x2f8: /* COM2 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 187 | set |= DECODE_ENABLE_SERIAL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 188 | rsize = 8; |
| 189 | break; |
| 190 | case 0x378: /* Parallel 1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 191 | set |= DECODE_ENABLE_PARALLEL_PORT0; |
| 192 | /* enable 0x778 for ECP mode */ |
| 193 | set |= DECODE_ENABLE_PARALLEL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 194 | rsize = 8; |
| 195 | break; |
| 196 | case 0x3f0: /* FD0 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 197 | set |= DECODE_ENABLE_FDC_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 198 | rsize = 8; |
| 199 | break; |
| 200 | case 0x220: /* 0x220 - 0x227 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 201 | set |= DECODE_ENABLE_SERIAL_PORT2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 202 | rsize = 8; |
| 203 | break; |
| 204 | case 0x228: /* 0x228 - 0x22f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 205 | set |= DECODE_ENABLE_SERIAL_PORT3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 206 | rsize = 8; |
| 207 | break; |
| 208 | case 0x238: /* 0x238 - 0x23f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 209 | set |= DECODE_ENABLE_SERIAL_PORT4; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 210 | rsize = 8; |
| 211 | break; |
| 212 | case 0x300: /* 0x300 - 0x301 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 213 | set |= DECODE_ENABLE_MIDI_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 214 | rsize = 2; |
| 215 | break; |
| 216 | case 0x400: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 217 | set_x |= DECODE_IO_PORT_ENABLE0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 218 | rsize = 0x40; |
| 219 | break; |
| 220 | case 0x480: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 221 | set_x |= DECODE_IO_PORT_ENABLE1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 222 | rsize = 0x40; |
| 223 | break; |
| 224 | case 0x500: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 225 | set_x |= DECODE_IO_PORT_ENABLE2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 226 | rsize = 0x40; |
| 227 | break; |
| 228 | case 0x580: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 229 | set_x |= DECODE_IO_PORT_ENABLE3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 230 | rsize = 0x40; |
| 231 | break; |
| 232 | case 0x4700: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 233 | set_x |= DECODE_IO_PORT_ENABLE5; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 234 | rsize = 0xc; |
| 235 | break; |
| 236 | case 0xfd60: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 237 | set_x |= DECODE_IO_PORT_ENABLE6; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 238 | rsize = 16; |
| 239 | break; |
| 240 | default: |
| 241 | rsize = 0; |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 242 | wideio_index = lpc_find_wideio_range(base, res->size); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 243 | if (wideio_index != WIDEIO_RANGE_ERROR) { |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 244 | rsize = lpc_wideio_size(wideio_index); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 245 | printk(BIOS_DEBUG, "Covered by wideIO"); |
| 246 | printk(BIOS_DEBUG, " %d\n", wideio_index); |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 247 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 248 | } |
| 249 | /* check if region found and matches the enable */ |
| 250 | if (res->size <= rsize) { |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 251 | reg |= set; |
| 252 | reg_x |= set_x; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 253 | /* check if we can fit resource in variable range */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 254 | } else { |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 255 | wideio_index = lpc_set_wideio_range(base, res->size); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 256 | if (wideio_index != WIDEIO_RANGE_ERROR) { |
| 257 | /* preserve wide IO related bits. */ |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 258 | reg_x = pci_read_config32(dev, |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 259 | LPC_IO_OR_MEM_DECODE_ENABLE); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 260 | printk(BIOS_DEBUG, |
| 261 | "Range assigned to wide IO %d\n", |
| 262 | wideio_index); |
| 263 | } else { |
| 264 | printk(BIOS_ERR, |
| 265 | "cannot fit LPC decode region:"); |
| 266 | printk(BIOS_ERR, |
| 267 | "%s, base = 0x%08x, end = 0x%08x\n", |
| 268 | dev_path(child), base, end); |
| 269 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 270 | } |
| 271 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 272 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 273 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); |
| 274 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 275 | } |
| 276 | |
Furquan Shaikh | 511aa44 | 2020-05-04 23:42:46 -0700 | [diff] [blame] | 277 | static void configure_child_espi_windows(struct device *child) |
| 278 | { |
| 279 | struct resource *res; |
| 280 | |
| 281 | for (res = child->resource_list; res; res = res->next) { |
| 282 | if (res->flags & IORESOURCE_IO) |
| 283 | espi_open_io_window(res->base, res->size); |
| 284 | else if (res->flags & IORESOURCE_MEM) |
| 285 | espi_open_mmio_window(res->base, res->size); |
| 286 | } |
| 287 | } |
| 288 | |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 289 | static void lpc_enable_children_resources(struct device *dev) |
| 290 | { |
| 291 | struct bus *link; |
| 292 | struct device *child; |
| 293 | |
| 294 | for (link = dev->link_list; link; link = link->next) { |
| 295 | for (child = link->children; child; child = child->sibling) { |
| 296 | if (!child->enabled) |
| 297 | continue; |
| 298 | if (child->path.type != DEVICE_PATH_PNP) |
| 299 | continue; |
Furquan Shaikh | 511aa44 | 2020-05-04 23:42:46 -0700 | [diff] [blame] | 300 | if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) |
| 301 | configure_child_espi_windows(child); |
| 302 | else |
| 303 | configure_child_lpc_windows(dev, child); |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 304 | } |
| 305 | } |
| 306 | } |
| 307 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 308 | static void lpc_enable_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 309 | { |
| 310 | pci_dev_enable_resources(dev); |
Furquan Shaikh | 1e279a5 | 2020-05-04 21:22:22 -0700 | [diff] [blame] | 311 | lpc_enable_children_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 312 | } |
| 313 | |
Felix Held | 3e29ca9 | 2021-02-16 23:52:58 +0100 | [diff] [blame] | 314 | #if CONFIG(HAVE_ACPI_TABLES) |
| 315 | static const char *lpc_acpi_name(const struct device *dev) |
| 316 | { |
| 317 | return "LPCB"; |
| 318 | } |
| 319 | #endif |
| 320 | |
Arthur Heymans | c6f029c | 2022-10-05 21:48:07 +0200 | [diff] [blame] | 321 | struct device_operations amd_lpc_ops = { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 322 | .read_resources = lpc_read_resources, |
| 323 | .set_resources = lpc_set_resources, |
| 324 | .enable_resources = lpc_enable_resources, |
Zheng Bao | bdd5031 | 2021-01-26 18:27:46 +0800 | [diff] [blame] | 325 | #if CONFIG(HAVE_ACPI_TABLES) |
Felix Held | 3e29ca9 | 2021-02-16 23:52:58 +0100 | [diff] [blame] | 326 | .acpi_name = lpc_acpi_name, |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 327 | .write_acpi_tables = southbridge_write_acpi_tables, |
Zheng Bao | bdd5031 | 2021-01-26 18:27:46 +0800 | [diff] [blame] | 328 | #endif |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 329 | .init = lpc_init, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 330 | .scan_bus = scan_static_bus, |
Furquan Shaikh | 40454b7 | 2020-05-04 20:52:08 -0700 | [diff] [blame] | 331 | .ops_pci = &pci_dev_ops_pci, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 332 | }; |