Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 4 | * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 17 | #include <cbmem.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pnp.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <pc80/isa-dma.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 27 | #include <arch/ioapic.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 28 | #include <pc80/i8254.h> |
| 29 | #include <pc80/i8259.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 30 | #include <amdblocks/acpimmio.h> |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 31 | #include <amdblocks/lpc.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 32 | #include <soc/acpi.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 33 | #include <soc/southbridge.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 34 | #include <soc/nvs.h> |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 35 | #include <soc/iomap.h> |
| 36 | |
| 37 | /* Most systems should have already enabled the bridge */ |
| 38 | void __weak soc_late_lpc_bridge_enable(void) { } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 39 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 40 | static void lpc_init(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 41 | { |
| 42 | u8 byte; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 43 | |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 44 | soc_late_lpc_bridge_enable(); |
| 45 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 46 | /* Initialize isa dma */ |
| 47 | isa_dma_init(); |
| 48 | |
| 49 | /* Enable DMA transaction on the LPC bus */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 50 | byte = pci_read_config8(dev, LPC_PCI_CONTROL); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 51 | byte |= LEGACY_DMA_EN; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 52 | pci_write_config8(dev, LPC_PCI_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 53 | |
| 54 | /* Disable the timeout mechanism on LPC */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 55 | byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 56 | byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 57 | pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 58 | |
| 59 | /* Disable LPC MSI Capability */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 60 | byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 61 | /* BIT 1 is not defined in public datasheet. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 62 | byte &= ~(1 << 1); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * Keep the old way. i.e., when bus master/DMA cycle is going |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 66 | * on on LPC, it holds PCI grant, so no LPC slave cycle can |
| 67 | * interrupt and visit LPC. |
| 68 | */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 69 | byte &= ~LPC_NOHOG; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 70 | pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 71 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 72 | /* |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 73 | * Enable hand-instance of the pulse generator and SPI prefetch from |
| 74 | * host (earlier is recommended for boot speed). |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 75 | */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 76 | byte = pci_read_config8(dev, LPC_HOST_CONTROL); |
Richard Spiegel | ee09878 | 2018-07-30 12:05:22 -0700 | [diff] [blame] | 77 | byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 78 | pci_write_config8(dev, LPC_HOST_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 79 | |
| 80 | cmos_check_update_date(); |
| 81 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 82 | /* |
| 83 | * Initialize the real time clock. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 84 | * The 0 argument tells cmos_init not to |
| 85 | * update CMOS unless it is invalid. |
| 86 | * 1 tells cmos_init to always initialize the CMOS. |
| 87 | */ |
Aaron Durbin | 9fde0d7 | 2017-09-15 11:01:17 -0600 | [diff] [blame] | 88 | cmos_init(0); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 89 | |
| 90 | /* Initialize i8259 pic */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 91 | setup_i8259(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 92 | |
| 93 | /* Initialize i8254 timers */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 94 | setup_i8254(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 95 | |
| 96 | /* Set up SERIRQ, enable continuous mode */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 97 | byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 98 | if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 99 | byte |= PM_SERIRQ_MODE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 100 | |
| 101 | pm_write8(PM_SERIRQ_CONF, byte); |
| 102 | } |
| 103 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 104 | static void lpc_read_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 105 | { |
| 106 | struct resource *res; |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 107 | global_nvs_t *gnvs; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 108 | |
| 109 | /* Get the normal pci resources of this device */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 110 | pci_dev_read_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | |
| 112 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 113 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 114 | res->base = 0; |
| 115 | res->size = 0x1000; |
| 116 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 117 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 118 | |
| 119 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 120 | res->base = FLASH_BASE_ADDR; |
| 121 | res->size = CONFIG_ROM_SIZE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 122 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 123 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 124 | |
| 125 | /* Add a memory resource for the SPI BAR. */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 126 | fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, |
| 127 | IORESOURCE_SUBTRACTIVE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 128 | |
| 129 | res = new_resource(dev, 3); /* IOAPIC */ |
| 130 | res->base = IO_APIC_ADDR; |
| 131 | res->size = 0x00001000; |
| 132 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 133 | |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 134 | /* I2C devices (all 4 devices) */ |
| 135 | res = new_resource(dev, 4); |
| 136 | res->base = I2C_BASE_ADDRESS; |
| 137 | res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT; |
| 138 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 139 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 140 | compact_resources(dev); |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 141 | |
| 142 | /* Allocate ACPI NVS in CBMEM */ |
| 143 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 145 | } |
| 146 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 147 | static void lpc_set_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 148 | { |
| 149 | struct resource *res; |
| 150 | u32 spi_enable_bits; |
| 151 | |
| 152 | /* Special case. The SpiRomEnable and other enables should STAY set. */ |
| 153 | res = find_resource(dev, 2); |
| 154 | spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 155 | spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 156 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, |
| 157 | res->base | spi_enable_bits); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 158 | |
| 159 | pci_dev_set_resources(dev); |
| 160 | } |
| 161 | |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 162 | static void set_child_resource(struct device *dev, struct device *child, |
| 163 | u32 *reg, u32 *reg_x) |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 164 | { |
| 165 | struct resource *res; |
| 166 | u32 base, end; |
| 167 | u32 rsize = 0, set = 0, set_x = 0; |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 168 | int wideio_index; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 169 | |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 170 | /* |
| 171 | * Be a bit relaxed, tolerate that LPC region might be bigger than |
| 172 | * resource we try to fit, do it like this for all regions < 16 bytes. |
| 173 | * If there is a resource > 16 bytes it must be 512 bytes to be able |
| 174 | * to allocate the fresh LPC window. |
| 175 | * |
| 176 | * AGESA and early initialization can set a wide IO port. This code |
| 177 | * will verify if required region was previously set and will avoid |
| 178 | * setting a new wide IO resource if one is already set. |
| 179 | */ |
| 180 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 181 | for (res = child->resource_list; res; res = res->next) { |
| 182 | if (!(res->flags & IORESOURCE_IO)) |
| 183 | continue; |
| 184 | base = res->base; |
| 185 | end = resource_end(res); |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 186 | printk(BIOS_DEBUG, |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 187 | "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", |
| 188 | dev_path(child), base, end); |
| 189 | /* find a resource size */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 190 | switch (base) { |
| 191 | case 0x60: /* KB */ |
| 192 | case 0x64: /* MS */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 193 | set |= DECODE_ENABLE_KBC_PORT; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 194 | rsize = 1; |
| 195 | break; |
| 196 | case 0x3f8: /* COM1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 197 | set |= DECODE_ENABLE_SERIAL_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 198 | rsize = 8; |
| 199 | break; |
| 200 | case 0x2f8: /* COM2 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 201 | set |= DECODE_ENABLE_SERIAL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 202 | rsize = 8; |
| 203 | break; |
| 204 | case 0x378: /* Parallel 1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 205 | set |= DECODE_ENABLE_PARALLEL_PORT0; |
| 206 | /* enable 0x778 for ECP mode */ |
| 207 | set |= DECODE_ENABLE_PARALLEL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 208 | rsize = 8; |
| 209 | break; |
| 210 | case 0x3f0: /* FD0 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 211 | set |= DECODE_ENABLE_FDC_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 212 | rsize = 8; |
| 213 | break; |
| 214 | case 0x220: /* 0x220 - 0x227 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 215 | set |= DECODE_ENABLE_SERIAL_PORT2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 216 | rsize = 8; |
| 217 | break; |
| 218 | case 0x228: /* 0x228 - 0x22f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 219 | set |= DECODE_ENABLE_SERIAL_PORT3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 220 | rsize = 8; |
| 221 | break; |
| 222 | case 0x238: /* 0x238 - 0x23f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 223 | set |= DECODE_ENABLE_SERIAL_PORT4; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 224 | rsize = 8; |
| 225 | break; |
| 226 | case 0x300: /* 0x300 - 0x301 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 227 | set |= DECODE_ENABLE_MIDI_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 228 | rsize = 2; |
| 229 | break; |
| 230 | case 0x400: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 231 | set_x |= DECODE_IO_PORT_ENABLE0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 232 | rsize = 0x40; |
| 233 | break; |
| 234 | case 0x480: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 235 | set_x |= DECODE_IO_PORT_ENABLE1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 236 | rsize = 0x40; |
| 237 | break; |
| 238 | case 0x500: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 239 | set_x |= DECODE_IO_PORT_ENABLE2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 240 | rsize = 0x40; |
| 241 | break; |
| 242 | case 0x580: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 243 | set_x |= DECODE_IO_PORT_ENABLE3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 244 | rsize = 0x40; |
| 245 | break; |
| 246 | case 0x4700: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 247 | set_x |= DECODE_IO_PORT_ENABLE5; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 248 | rsize = 0xc; |
| 249 | break; |
| 250 | case 0xfd60: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 251 | set_x |= DECODE_IO_PORT_ENABLE6; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 252 | rsize = 16; |
| 253 | break; |
| 254 | default: |
| 255 | rsize = 0; |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 256 | wideio_index = lpc_find_wideio_range(base, res->size); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 257 | if (wideio_index != WIDEIO_RANGE_ERROR) { |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 258 | rsize = lpc_wideio_size(wideio_index); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 259 | printk(BIOS_DEBUG, "Covered by wideIO"); |
| 260 | printk(BIOS_DEBUG, " %d\n", wideio_index); |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 261 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 262 | } |
| 263 | /* check if region found and matches the enable */ |
| 264 | if (res->size <= rsize) { |
| 265 | *reg |= set; |
| 266 | *reg_x |= set_x; |
| 267 | /* check if we can fit resource in variable range */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 268 | } else { |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame^] | 269 | wideio_index = lpc_set_wideio_range(base, res->size); |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 270 | if (wideio_index != WIDEIO_RANGE_ERROR) { |
| 271 | /* preserve wide IO related bits. */ |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 272 | *reg_x = pci_read_config32(dev, |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 273 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 274 | |
| 275 | printk(BIOS_DEBUG, |
| 276 | "Range assigned to wide IO %d\n", |
| 277 | wideio_index); |
| 278 | } else { |
| 279 | printk(BIOS_ERR, |
| 280 | "cannot fit LPC decode region:"); |
| 281 | printk(BIOS_ERR, |
| 282 | "%s, base = 0x%08x, end = 0x%08x\n", |
| 283 | dev_path(child), base, end); |
| 284 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 285 | } |
| 286 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 287 | } |
| 288 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 289 | /** |
| 290 | * @brief Enable resources for children devices |
| 291 | * |
| 292 | * @param dev the device whose children's resources are to be enabled |
| 293 | * |
| 294 | */ |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 295 | static void lpc_enable_childrens_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 296 | { |
| 297 | struct bus *link; |
| 298 | u32 reg, reg_x; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 299 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 300 | reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); |
| 301 | reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 302 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 303 | for (link = dev->link_list; link; link = link->next) { |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 304 | struct device *child; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 305 | for (child = link->children; child; |
| 306 | child = child->sibling) { |
| 307 | if (child->enabled |
Marshall Dawson | 1bc04e3 | 2019-05-02 18:56:54 -0600 | [diff] [blame] | 308 | && (child->path.type == DEVICE_PATH_PNP)) |
| 309 | set_child_resource(dev, child, ®, ®_x); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 310 | } |
| 311 | } |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 312 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); |
| 313 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 314 | } |
| 315 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 316 | static void lpc_enable_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 317 | { |
| 318 | pci_dev_enable_resources(dev); |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 319 | lpc_enable_childrens_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 320 | } |
| 321 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 322 | static struct pci_operations lops_pci = { |
| 323 | .set_subsystem = pci_dev_set_subsystem, |
| 324 | }; |
| 325 | |
| 326 | static struct device_operations lpc_ops = { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 327 | .read_resources = lpc_read_resources, |
| 328 | .set_resources = lpc_set_resources, |
| 329 | .enable_resources = lpc_enable_resources, |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 330 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 331 | .write_acpi_tables = southbridge_write_acpi_tables, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 332 | .init = lpc_init, |
| 333 | .scan_bus = scan_lpc_bus, |
| 334 | .ops_pci = &lops_pci, |
| 335 | }; |
| 336 | |
| 337 | static const unsigned short pci_device_ids[] = { |
| 338 | PCI_DEVICE_ID_AMD_SB900_LPC, |
| 339 | PCI_DEVICE_ID_AMD_CZ_LPC, |
| 340 | 0 |
| 341 | }; |
| 342 | static const struct pci_driver lpc_driver __pci_driver = { |
| 343 | .ops = &lpc_ops, |
| 344 | .vendor = PCI_VENDOR_ID_AMD, |
| 345 | .devices = pci_device_ids, |
| 346 | }; |