soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to
clarify that this isn't the address the SPI flash gets mapped, but the
address of the SPI controller MMIO region. This also aligns the register
name with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index ee8f7e4..99f84fa 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -124,9 +124,9 @@
/* Special case. The SpiRomEnable and other enables should STAY set. */
res = find_resource(dev, 2);
- spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+ spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER);
spi_enable_bits &= SPI_BASE_ALIGNMENT - 1;
- pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER,
+ pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER,
res->base | spi_enable_bits);
pci_dev_set_resources(dev);