soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device
Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.
TEST=On Mandolin both IOAPICs are still correctly detected by Linux.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 99f84fa..60c85b9 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/ioapic.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -15,6 +16,7 @@
#include <amdblocks/acpi.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/espi.h>
+#include <amdblocks/ioapic.h>
#include <amdblocks/lpc.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -34,6 +36,12 @@
pm_write8(PM_SERIRQ_CONF, byte);
}
+static void fch_ioapic_init(void)
+{
+ fch_enable_ioapic_decode();
+ setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
+}
+
static void lpc_init(struct device *dev)
{
u8 byte;
@@ -83,6 +91,9 @@
setup_i8254();
setup_serirq();
+
+ fch_ioapic_init();
+ fch_configure_hpet();
}
static void lpc_read_resources(struct device *dev)