Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 17 | #include <cbmem.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pnp.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <pc80/isa-dma.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <arch/ioapic.h> |
| 29 | #include <arch/acpi.h> |
| 30 | #include <pc80/i8254.h> |
| 31 | #include <pc80/i8259.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 32 | #include <soc/acpi.h> |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 34 | #include <soc/southbridge.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 35 | #include <soc/nvs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 36 | |
| 37 | static void lpc_init(device_t dev) |
| 38 | { |
| 39 | u8 byte; |
| 40 | u32 dword; |
| 41 | device_t sm_dev; |
| 42 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 43 | /* |
| 44 | * Enable the LPC Controller |
| 45 | * SMBus register 0x64 is not defined in public datasheet. |
| 46 | */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 47 | sm_dev = dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 48 | dword = pci_read_config32(sm_dev, 0x64); |
| 49 | dword |= 1 << 20; |
| 50 | pci_write_config32(sm_dev, 0x64, dword); |
| 51 | |
| 52 | /* Initialize isa dma */ |
| 53 | isa_dma_init(); |
| 54 | |
| 55 | /* Enable DMA transaction on the LPC bus */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 56 | byte = pci_read_config8(dev, LPC_PCI_CONTROL); |
| 57 | byte |= LEGACY_DMA_EN; |
| 58 | pci_write_config8(dev, LPC_PCI_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 59 | |
| 60 | /* Disable the timeout mechanism on LPC */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 61 | byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 62 | byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; |
| 63 | pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 64 | |
| 65 | /* Disable LPC MSI Capability */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 66 | byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); |
| 67 | /* BIT 1 is not defined in public datasheet. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 68 | byte &= ~(1 << 1); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 69 | |
| 70 | /* |
| 71 | * Keep the old way. i.e., when bus master/DMA cycle is going |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 72 | * on on LPC, it holds PCI grant, so no LPC slave cycle can |
| 73 | * interrupt and visit LPC. |
| 74 | */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 75 | byte &= ~LPC_NOHOG; |
| 76 | pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 77 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 78 | /* |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 79 | * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 80 | * todo: verify against BKDG |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 81 | */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 82 | byte = pci_read_config8(dev, LPC_HOST_CONTROL); |
| 83 | byte |= SPI_FROM_HOST_PREFETCH_EN | 1 << 3; |
| 84 | pci_write_config8(dev, LPC_HOST_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 85 | |
| 86 | cmos_check_update_date(); |
| 87 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 88 | /* |
| 89 | * Initialize the real time clock. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 90 | * The 0 argument tells cmos_init not to |
| 91 | * update CMOS unless it is invalid. |
| 92 | * 1 tells cmos_init to always initialize the CMOS. |
| 93 | */ |
Aaron Durbin | 9fde0d7 | 2017-09-15 11:01:17 -0600 | [diff] [blame] | 94 | cmos_init(0); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 95 | |
| 96 | /* Initialize i8259 pic */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 97 | setup_i8259(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 98 | |
| 99 | /* Initialize i8254 timers */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 100 | setup_i8254(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 101 | |
| 102 | /* Set up SERIRQ, enable continuous mode */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 103 | byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 104 | if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 105 | byte |= PM_SERIRQ_MODE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 106 | |
| 107 | pm_write8(PM_SERIRQ_CONF, byte); |
| 108 | } |
| 109 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 110 | static void lpc_read_resources(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | { |
| 112 | struct resource *res; |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 113 | global_nvs_t *gnvs; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 114 | |
| 115 | /* Get the normal pci resources of this device */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 116 | pci_dev_read_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 117 | |
| 118 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 119 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 120 | res->base = 0; |
| 121 | res->size = 0x1000; |
| 122 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 123 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 124 | |
| 125 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 126 | res->base = FLASH_BASE_ADDR; |
| 127 | res->size = CONFIG_ROM_SIZE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 128 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 129 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 130 | |
| 131 | /* Add a memory resource for the SPI BAR. */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 132 | fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, |
| 133 | IORESOURCE_SUBTRACTIVE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 134 | |
| 135 | res = new_resource(dev, 3); /* IOAPIC */ |
| 136 | res->base = IO_APIC_ADDR; |
| 137 | res->size = 0x00001000; |
| 138 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 139 | |
| 140 | compact_resources(dev); |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 141 | |
| 142 | /* Allocate ACPI NVS in CBMEM */ |
| 143 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 144 | } |
| 145 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 146 | static void lpc_set_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 147 | { |
| 148 | struct resource *res; |
| 149 | u32 spi_enable_bits; |
| 150 | |
| 151 | /* Special case. The SpiRomEnable and other enables should STAY set. */ |
| 152 | res = find_resource(dev, 2); |
| 153 | spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 154 | spi_enable_bits &= SPI_PRESERVE_BITS; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 155 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, |
| 156 | res->base | spi_enable_bits); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 157 | |
| 158 | pci_dev_set_resources(dev); |
| 159 | } |
| 160 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 161 | static void set_lpc_resource(device_t child, |
| 162 | int *variable_num, |
| 163 | u16 *reg_var, |
| 164 | u32 *reg, |
| 165 | u32 *reg_x, |
| 166 | u16 reg_size, |
| 167 | u8 *wiosize) |
| 168 | { |
| 169 | struct resource *res; |
| 170 | u32 base, end; |
| 171 | u32 rsize = 0, set = 0, set_x = 0; |
| 172 | u16 var_num; |
| 173 | |
| 174 | var_num = *variable_num; |
| 175 | for (res = child->resource_list; res; res = res->next) { |
| 176 | if (!(res->flags & IORESOURCE_IO)) |
| 177 | continue; |
| 178 | base = res->base; |
| 179 | end = resource_end(res); |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 180 | printk(BIOS_DEBUG, |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 181 | "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", |
| 182 | dev_path(child), base, end); |
| 183 | /* find a resource size */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 184 | switch (base) { |
| 185 | case 0x60: /* KB */ |
| 186 | case 0x64: /* MS */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 187 | set |= DECODE_ENABLE_KBC_PORT; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 188 | rsize = 1; |
| 189 | break; |
| 190 | case 0x3f8: /* COM1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 191 | set |= DECODE_ENABLE_SERIAL_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 192 | rsize = 8; |
| 193 | break; |
| 194 | case 0x2f8: /* COM2 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 195 | set |= DECODE_ENABLE_SERIAL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 196 | rsize = 8; |
| 197 | break; |
| 198 | case 0x378: /* Parallel 1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 199 | set |= DECODE_ENABLE_PARALLEL_PORT0; |
| 200 | /* enable 0x778 for ECP mode */ |
| 201 | set |= DECODE_ENABLE_PARALLEL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 202 | rsize = 8; |
| 203 | break; |
| 204 | case 0x3f0: /* FD0 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 205 | set |= DECODE_ENABLE_FDC_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 206 | rsize = 8; |
| 207 | break; |
| 208 | case 0x220: /* 0x220 - 0x227 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 209 | set |= DECODE_ENABLE_SERIAL_PORT2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 210 | rsize = 8; |
| 211 | break; |
| 212 | case 0x228: /* 0x228 - 0x22f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 213 | set |= DECODE_ENABLE_SERIAL_PORT3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 214 | rsize = 8; |
| 215 | break; |
| 216 | case 0x238: /* 0x238 - 0x23f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 217 | set |= DECODE_ENABLE_SERIAL_PORT4; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 218 | rsize = 8; |
| 219 | break; |
| 220 | case 0x300: /* 0x300 - 0x301 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 221 | set |= DECODE_ENABLE_MIDI_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 222 | rsize = 2; |
| 223 | break; |
| 224 | case 0x400: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 225 | set_x |= DECODE_IO_PORT_ENABLE0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 226 | rsize = 0x40; |
| 227 | break; |
| 228 | case 0x480: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 229 | set_x |= DECODE_IO_PORT_ENABLE1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 230 | rsize = 0x40; |
| 231 | break; |
| 232 | case 0x500: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 233 | set_x |= DECODE_IO_PORT_ENABLE2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 234 | rsize = 0x40; |
| 235 | break; |
| 236 | case 0x580: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 237 | set_x |= DECODE_IO_PORT_ENABLE3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 238 | rsize = 0x40; |
| 239 | break; |
| 240 | case 0x4700: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 241 | set_x |= DECODE_IO_PORT_ENABLE5; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 242 | rsize = 0xc; |
| 243 | break; |
| 244 | case 0xfd60: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 245 | set_x |= DECODE_IO_PORT_ENABLE6; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 246 | rsize = 16; |
| 247 | break; |
| 248 | default: |
| 249 | rsize = 0; |
| 250 | /* try AGESA allocated region in region 0 */ |
| 251 | if ((var_num > 0) && ((base >= reg_var[0]) && |
| 252 | ((base + res->size) <= (reg_var[0] + reg_size)))) |
| 253 | rsize = reg_size; |
| 254 | } |
| 255 | /* check if region found and matches the enable */ |
| 256 | if (res->size <= rsize) { |
| 257 | *reg |= set; |
| 258 | *reg_x |= set_x; |
| 259 | /* check if we can fit resource in variable range */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 260 | } else if ((var_num < 3) && |
| 261 | ((res->size <= 16) || (res->size == 512))) { |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 262 | /* use variable ranges if pre-defined do not match */ |
| 263 | switch (var_num) { |
| 264 | case 0: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 265 | *reg_x |= LPC_WIDEIO0_ENABLE; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 266 | if (res->size <= 16) |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 267 | *wiosize |= LPC_ALT_WIDEIO0_ENABLE; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 268 | break; |
| 269 | case 1: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 270 | *reg_x |= LPC_WIDEIO1_ENABLE; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 271 | if (res->size <= 16) |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 272 | *wiosize |= LPC_ALT_WIDEIO1_ENABLE; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 273 | break; |
| 274 | case 2: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 275 | *reg_x |= LPC_WIDEIO2_ENABLE; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 276 | if (res->size <= 16) |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 277 | *wiosize |= LPC_ALT_WIDEIO2_ENABLE; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 278 | break; |
| 279 | } |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 280 | reg_var[var_num++] = base & 0xffff; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 281 | } else { |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 282 | printk(BIOS_ERR, |
| 283 | "cannot fit LPC decode region:"); |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 284 | printk(BIOS_ERR, "%s, base = 0x%08x, end = 0x%08x\n", |
| 285 | dev_path(child), base, end); |
| 286 | } |
| 287 | } |
| 288 | *variable_num = var_num; |
| 289 | } |
| 290 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 291 | /** |
| 292 | * @brief Enable resources for children devices |
| 293 | * |
| 294 | * @param dev the device whose children's resources are to be enabled |
| 295 | * |
| 296 | */ |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 297 | static void lpc_enable_childrens_resources(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 298 | { |
| 299 | struct bus *link; |
| 300 | u32 reg, reg_x; |
| 301 | int var_num = 0; |
| 302 | u16 reg_var[3]; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 303 | u16 reg_size[1] = {512}; |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 304 | u8 wiosize = pci_read_config8(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 305 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 306 | /* |
| 307 | * Be a bit relaxed, tolerate that LPC region might be bigger than |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 308 | * resource we try to fit, do it like this for all regions < 16 bytes. |
| 309 | * If there is a resource > 16 bytes it must be 512 bytes to be able |
| 310 | * to allocate the fresh LPC window. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 311 | * |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 312 | * AGESA likes to enable already one LPC region in wide port base |
| 313 | * 0x64-0x65, using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size |
| 314 | * The code tries to check if resource can fit into this region. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 315 | */ |
| 316 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 317 | reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); |
| 318 | reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 319 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 320 | /* check if ranges are free and don't use them if already taken */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 321 | if (reg_x & LPC_WIDEIO0_ENABLE) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 322 | var_num = 1; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 323 | /* just in case check if someone did not manually set other ranges */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 324 | if (reg_x & LPC_WIDEIO1_ENABLE) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 325 | var_num = 2; |
| 326 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 327 | if (reg_x & LPC_WIDEIO2_ENABLE) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 328 | var_num = 3; |
| 329 | |
| 330 | /* check AGESA region size */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 331 | if (wiosize & LPC_ALT_WIDEIO0_ENABLE) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 332 | reg_size[0] = 16; |
| 333 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 334 | reg_var[2] = pci_read_config16(dev, LPC_WIDEIO2_GENERIC_PORT); |
| 335 | reg_var[1] = pci_read_config16(dev, LPC_WIDEIO1_GENERIC_PORT); |
| 336 | reg_var[0] = pci_read_config16(dev, LPC_WIDEIO_GENERIC_PORT); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 337 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 338 | /* todo: clean up the code style here */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 339 | for (link = dev->link_list; link; link = link->next) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 340 | device_t child; |
| 341 | for (child = link->children; child; |
| 342 | child = child->sibling) { |
| 343 | if (child->enabled |
| 344 | && (child->path.type == DEVICE_PATH_PNP)) { |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 345 | set_lpc_resource(child, |
| 346 | &var_num, |
| 347 | reg_var, |
| 348 | ®, |
| 349 | ®_x, |
| 350 | reg_size[0], |
| 351 | &wiosize); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 352 | } |
| 353 | } |
| 354 | } |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 355 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); |
| 356 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 357 | /* Set WideIO for as many IOs found (fall through is on purpose) */ |
| 358 | switch (var_num) { |
| 359 | case 3: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 360 | pci_write_config16(dev, LPC_WIDEIO2_GENERIC_PORT, reg_var[2]); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 361 | /* fall through */ |
| 362 | case 2: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 363 | pci_write_config16(dev, LPC_WIDEIO1_GENERIC_PORT, reg_var[1]); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 364 | /* fall through */ |
| 365 | case 1: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 366 | pci_write_config16(dev, LPC_WIDEIO_GENERIC_PORT, reg_var[0]); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 367 | break; |
| 368 | } |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame^] | 369 | pci_write_config8(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, wiosize); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 370 | } |
| 371 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 372 | static void lpc_enable_resources(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 373 | { |
| 374 | pci_dev_enable_resources(dev); |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 375 | lpc_enable_childrens_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 376 | } |
| 377 | |
| 378 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 379 | { |
| 380 | /* Just a dummy */ |
| 381 | return current; |
| 382 | } |
| 383 | |
| 384 | static struct pci_operations lops_pci = { |
| 385 | .set_subsystem = pci_dev_set_subsystem, |
| 386 | }; |
| 387 | |
| 388 | static struct device_operations lpc_ops = { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 389 | .read_resources = lpc_read_resources, |
| 390 | .set_resources = lpc_set_resources, |
| 391 | .enable_resources = lpc_enable_resources, |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 392 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 393 | .write_acpi_tables = southbridge_write_acpi_tables, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 394 | .init = lpc_init, |
| 395 | .scan_bus = scan_lpc_bus, |
| 396 | .ops_pci = &lops_pci, |
| 397 | }; |
| 398 | |
| 399 | static const unsigned short pci_device_ids[] = { |
| 400 | PCI_DEVICE_ID_AMD_SB900_LPC, |
| 401 | PCI_DEVICE_ID_AMD_CZ_LPC, |
| 402 | 0 |
| 403 | }; |
| 404 | static const struct pci_driver lpc_driver __pci_driver = { |
| 405 | .ops = &lpc_ops, |
| 406 | .vendor = PCI_VENDOR_ID_AMD, |
| 407 | .devices = pci_device_ids, |
| 408 | }; |