Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 4 | * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 17 | #include <cbmem.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pnp.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <pc80/isa-dma.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <arch/ioapic.h> |
| 29 | #include <arch/acpi.h> |
| 30 | #include <pc80/i8254.h> |
| 31 | #include <pc80/i8259.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 32 | #include <soc/acpi.h> |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 34 | #include <soc/southbridge.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 35 | #include <soc/nvs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 36 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 37 | static void lpc_init(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 38 | { |
| 39 | u8 byte; |
| 40 | u32 dword; |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 41 | struct device *sm_dev; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 42 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 43 | /* |
| 44 | * Enable the LPC Controller |
| 45 | * SMBus register 0x64 is not defined in public datasheet. |
| 46 | */ |
Chris Ching | 6a35fab | 2017-10-19 11:45:30 -0600 | [diff] [blame] | 47 | sm_dev = dev_find_slot(0, SMBUS_DEVFN); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 48 | dword = pci_read_config32(sm_dev, 0x64); |
| 49 | dword |= 1 << 20; |
| 50 | pci_write_config32(sm_dev, 0x64, dword); |
| 51 | |
| 52 | /* Initialize isa dma */ |
| 53 | isa_dma_init(); |
| 54 | |
| 55 | /* Enable DMA transaction on the LPC bus */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 56 | byte = pci_read_config8(dev, LPC_PCI_CONTROL); |
| 57 | byte |= LEGACY_DMA_EN; |
| 58 | pci_write_config8(dev, LPC_PCI_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 59 | |
| 60 | /* Disable the timeout mechanism on LPC */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 61 | byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 62 | byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; |
| 63 | pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 64 | |
| 65 | /* Disable LPC MSI Capability */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 66 | byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); |
| 67 | /* BIT 1 is not defined in public datasheet. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 68 | byte &= ~(1 << 1); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * Keep the old way. i.e., when bus master/DMA cycle is going |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 72 | * on on LPC, it holds PCI grant, so no LPC slave cycle can |
| 73 | * interrupt and visit LPC. |
| 74 | */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 75 | byte &= ~LPC_NOHOG; |
| 76 | pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 77 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 78 | /* |
Richard Spiegel | ee09878 | 2018-07-30 12:05:22 -0700 | [diff] [blame^] | 79 | * Enable hand-instance of the pulse generator and SPI |
| 80 | * controller prefetch of flash. |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 81 | */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 82 | byte = pci_read_config8(dev, LPC_HOST_CONTROL); |
Richard Spiegel | ee09878 | 2018-07-30 12:05:22 -0700 | [diff] [blame^] | 83 | byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 84 | pci_write_config8(dev, LPC_HOST_CONTROL, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 85 | |
| 86 | cmos_check_update_date(); |
| 87 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 88 | /* |
| 89 | * Initialize the real time clock. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 90 | * The 0 argument tells cmos_init not to |
| 91 | * update CMOS unless it is invalid. |
| 92 | * 1 tells cmos_init to always initialize the CMOS. |
| 93 | */ |
Aaron Durbin | 9fde0d7 | 2017-09-15 11:01:17 -0600 | [diff] [blame] | 94 | cmos_init(0); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 95 | |
| 96 | /* Initialize i8259 pic */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 97 | setup_i8259(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 98 | |
| 99 | /* Initialize i8254 timers */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 100 | setup_i8254(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 101 | |
| 102 | /* Set up SERIRQ, enable continuous mode */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 103 | byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 104 | if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 105 | byte |= PM_SERIRQ_MODE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 106 | |
| 107 | pm_write8(PM_SERIRQ_CONF, byte); |
| 108 | } |
| 109 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 110 | static void lpc_read_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | { |
| 112 | struct resource *res; |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 113 | global_nvs_t *gnvs; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 114 | |
| 115 | /* Get the normal pci resources of this device */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 116 | pci_dev_read_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 117 | |
| 118 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 119 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 120 | res->base = 0; |
| 121 | res->size = 0x1000; |
| 122 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 123 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 124 | |
| 125 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 126 | res->base = FLASH_BASE_ADDR; |
| 127 | res->size = CONFIG_ROM_SIZE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 128 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 129 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 130 | |
| 131 | /* Add a memory resource for the SPI BAR. */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 132 | fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, |
| 133 | IORESOURCE_SUBTRACTIVE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 134 | |
| 135 | res = new_resource(dev, 3); /* IOAPIC */ |
| 136 | res->base = IO_APIC_ADDR; |
| 137 | res->size = 0x00001000; |
| 138 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 139 | |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 140 | /* I2C devices (all 4 devices) */ |
| 141 | res = new_resource(dev, 4); |
| 142 | res->base = I2C_BASE_ADDRESS; |
| 143 | res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT; |
| 144 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 145 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 146 | compact_resources(dev); |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 147 | |
| 148 | /* Allocate ACPI NVS in CBMEM */ |
| 149 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 150 | } |
| 151 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 152 | static void lpc_set_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 153 | { |
| 154 | struct resource *res; |
| 155 | u32 spi_enable_bits; |
| 156 | |
| 157 | /* Special case. The SpiRomEnable and other enables should STAY set. */ |
| 158 | res = find_resource(dev, 2); |
| 159 | spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 160 | spi_enable_bits &= SPI_PRESERVE_BITS; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 161 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, |
| 162 | res->base | spi_enable_bits); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 163 | |
| 164 | pci_dev_set_resources(dev); |
| 165 | } |
| 166 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 167 | static void set_child_resource(struct device *child, |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 168 | u32 *reg, |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 169 | u32 *reg_x) |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 170 | { |
| 171 | struct resource *res; |
| 172 | u32 base, end; |
| 173 | u32 rsize = 0, set = 0, set_x = 0; |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 174 | int wideio_index; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 175 | |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 176 | /* |
| 177 | * Be a bit relaxed, tolerate that LPC region might be bigger than |
| 178 | * resource we try to fit, do it like this for all regions < 16 bytes. |
| 179 | * If there is a resource > 16 bytes it must be 512 bytes to be able |
| 180 | * to allocate the fresh LPC window. |
| 181 | * |
| 182 | * AGESA and early initialization can set a wide IO port. This code |
| 183 | * will verify if required region was previously set and will avoid |
| 184 | * setting a new wide IO resource if one is already set. |
| 185 | */ |
| 186 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 187 | for (res = child->resource_list; res; res = res->next) { |
| 188 | if (!(res->flags & IORESOURCE_IO)) |
| 189 | continue; |
| 190 | base = res->base; |
| 191 | end = resource_end(res); |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 192 | printk(BIOS_DEBUG, |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 193 | "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", |
| 194 | dev_path(child), base, end); |
| 195 | /* find a resource size */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 196 | switch (base) { |
| 197 | case 0x60: /* KB */ |
| 198 | case 0x64: /* MS */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 199 | set |= DECODE_ENABLE_KBC_PORT; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 200 | rsize = 1; |
| 201 | break; |
| 202 | case 0x3f8: /* COM1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 203 | set |= DECODE_ENABLE_SERIAL_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 204 | rsize = 8; |
| 205 | break; |
| 206 | case 0x2f8: /* COM2 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 207 | set |= DECODE_ENABLE_SERIAL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 208 | rsize = 8; |
| 209 | break; |
| 210 | case 0x378: /* Parallel 1 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 211 | set |= DECODE_ENABLE_PARALLEL_PORT0; |
| 212 | /* enable 0x778 for ECP mode */ |
| 213 | set |= DECODE_ENABLE_PARALLEL_PORT1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 214 | rsize = 8; |
| 215 | break; |
| 216 | case 0x3f0: /* FD0 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 217 | set |= DECODE_ENABLE_FDC_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 218 | rsize = 8; |
| 219 | break; |
| 220 | case 0x220: /* 0x220 - 0x227 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 221 | set |= DECODE_ENABLE_SERIAL_PORT2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 222 | rsize = 8; |
| 223 | break; |
| 224 | case 0x228: /* 0x228 - 0x22f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 225 | set |= DECODE_ENABLE_SERIAL_PORT3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 226 | rsize = 8; |
| 227 | break; |
| 228 | case 0x238: /* 0x238 - 0x23f */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 229 | set |= DECODE_ENABLE_SERIAL_PORT4; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 230 | rsize = 8; |
| 231 | break; |
| 232 | case 0x300: /* 0x300 - 0x301 */ |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 233 | set |= DECODE_ENABLE_MIDI_PORT0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 234 | rsize = 2; |
| 235 | break; |
| 236 | case 0x400: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 237 | set_x |= DECODE_IO_PORT_ENABLE0; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 238 | rsize = 0x40; |
| 239 | break; |
| 240 | case 0x480: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 241 | set_x |= DECODE_IO_PORT_ENABLE1; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 242 | rsize = 0x40; |
| 243 | break; |
| 244 | case 0x500: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 245 | set_x |= DECODE_IO_PORT_ENABLE2; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 246 | rsize = 0x40; |
| 247 | break; |
| 248 | case 0x580: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 249 | set_x |= DECODE_IO_PORT_ENABLE3; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 250 | rsize = 0x40; |
| 251 | break; |
| 252 | case 0x4700: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 253 | set_x |= DECODE_IO_PORT_ENABLE5; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 254 | rsize = 0xc; |
| 255 | break; |
| 256 | case 0xfd60: |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 257 | set_x |= DECODE_IO_PORT_ENABLE6; |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 258 | rsize = 16; |
| 259 | break; |
| 260 | default: |
| 261 | rsize = 0; |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 262 | wideio_index = sb_find_wideio_range(base, res->size); |
| 263 | if (wideio_index != WIDEIO_RANGE_ERROR) { |
| 264 | rsize = sb_wideio_size(wideio_index); |
| 265 | printk(BIOS_DEBUG, "Covered by wideIO"); |
| 266 | printk(BIOS_DEBUG, " %d\n", wideio_index); |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 267 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 268 | } |
| 269 | /* check if region found and matches the enable */ |
| 270 | if (res->size <= rsize) { |
| 271 | *reg |= set; |
| 272 | *reg_x |= set_x; |
| 273 | /* check if we can fit resource in variable range */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 274 | } else { |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 275 | wideio_index = sb_set_wideio_range(base, res->size); |
| 276 | if (wideio_index != WIDEIO_RANGE_ERROR) { |
| 277 | /* preserve wide IO related bits. */ |
| 278 | *reg_x = pci_read_config32(SOC_LPC_DEV, |
| 279 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 280 | |
| 281 | printk(BIOS_DEBUG, |
| 282 | "Range assigned to wide IO %d\n", |
| 283 | wideio_index); |
| 284 | } else { |
| 285 | printk(BIOS_ERR, |
| 286 | "cannot fit LPC decode region:"); |
| 287 | printk(BIOS_ERR, |
| 288 | "%s, base = 0x%08x, end = 0x%08x\n", |
| 289 | dev_path(child), base, end); |
| 290 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 291 | } |
| 292 | } |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 295 | /** |
| 296 | * @brief Enable resources for children devices |
| 297 | * |
| 298 | * @param dev the device whose children's resources are to be enabled |
| 299 | * |
| 300 | */ |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 301 | static void lpc_enable_childrens_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 302 | { |
| 303 | struct bus *link; |
| 304 | u32 reg, reg_x; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 305 | |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 306 | reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); |
| 307 | reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 308 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 309 | for (link = dev->link_list; link; link = link->next) { |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 310 | struct device *child; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 311 | for (child = link->children; child; |
| 312 | child = child->sibling) { |
| 313 | if (child->enabled |
| 314 | && (child->path.type == DEVICE_PATH_PNP)) { |
Richard Spiegel | 7a39e02 | 2017-11-09 10:54:04 -0700 | [diff] [blame] | 315 | set_child_resource(child, |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame] | 316 | ®, |
Richard Spiegel | b5f9645 | 2017-11-22 15:28:25 -0700 | [diff] [blame] | 317 | ®_x); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 318 | } |
| 319 | } |
| 320 | } |
Richard Spiegel | c5ecd3e | 2017-09-29 10:05:35 -0700 | [diff] [blame] | 321 | pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); |
| 322 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 323 | } |
| 324 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 325 | static void lpc_enable_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 326 | { |
| 327 | pci_dev_enable_resources(dev); |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 328 | lpc_enable_childrens_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 332 | { |
| 333 | /* Just a dummy */ |
| 334 | return current; |
| 335 | } |
| 336 | |
| 337 | static struct pci_operations lops_pci = { |
| 338 | .set_subsystem = pci_dev_set_subsystem, |
| 339 | }; |
| 340 | |
| 341 | static struct device_operations lpc_ops = { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 342 | .read_resources = lpc_read_resources, |
| 343 | .set_resources = lpc_set_resources, |
| 344 | .enable_resources = lpc_enable_resources, |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 345 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 346 | .write_acpi_tables = southbridge_write_acpi_tables, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 347 | .init = lpc_init, |
| 348 | .scan_bus = scan_lpc_bus, |
| 349 | .ops_pci = &lops_pci, |
| 350 | }; |
| 351 | |
| 352 | static const unsigned short pci_device_ids[] = { |
| 353 | PCI_DEVICE_ID_AMD_SB900_LPC, |
| 354 | PCI_DEVICE_ID_AMD_CZ_LPC, |
| 355 | 0 |
| 356 | }; |
| 357 | static const struct pci_driver lpc_driver __pci_driver = { |
| 358 | .ops = &lpc_ops, |
| 359 | .vendor = PCI_VENDOR_ID_AMD, |
| 360 | .devices = pci_device_ids, |
| 361 | }; |