commit 257db58bdb06994e6082afff047e1a3d2ad8fe9a
author Marc Jones <marc.jones@scarletltd.com> Sun Jun 18 17:33:30 2017 -0600
committer Martin Roth <martinroth@google.com> Mon Jul 31 17:29:35 2017 +0000
tree d620d4ec0fa210c2b49a4bf076e6e3a3bb73cb9f
parent 583806a79d36a2aff5cb6069150ebe173130b00e

soc/amd/stoneyridge: Add GNVS

Add ACPI asl for global non-volatile storage (GNVS).

Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/stoneyridge/lpc.c

diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index d45ef0a..fae5c55 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -28,8 +29,10 @@
 #include <arch/acpi.h>
 #include <pc80/i8254.h>
 #include <pc80/i8259.h>
+#include <soc/acpi.h>
 #include <soc/pci_devs.h>
 #include <soc/hudson.h>
+#include <soc/nvs.h>
 #include <vboot/vbnv.h>
 
 static void lpc_init(device_t dev)
@@ -105,6 +108,7 @@
 static void hudson_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
+	global_nvs_t *gnvs;
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev);
@@ -132,6 +136,9 @@
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	compact_resources(dev);
+
+	/* Allocate ACPI NVS in CBMEM */
+	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
 }
 
 static void hudson_lpc_set_resources(struct device *dev)
@@ -355,9 +362,8 @@
 	.read_resources = hudson_lpc_read_resources,
 	.set_resources = hudson_lpc_set_resources,
 	.enable_resources = hudson_lpc_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-	.write_acpi_tables = acpi_write_hpet,
-#endif
+	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.write_acpi_tables = southbridge_write_acpi_tables,
 	.init = lpc_init,
 	.scan_bus = scan_lpc_bus,
 	.ops_pci = &lops_pci,