Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 17 | #include <cbmem.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pnp.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <pc80/isa-dma.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <arch/ioapic.h> |
| 29 | #include <arch/acpi.h> |
| 30 | #include <pc80/i8254.h> |
| 31 | #include <pc80/i8259.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 32 | #include <soc/acpi.h> |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 34 | #include <soc/southbridge.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 35 | #include <soc/nvs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 36 | |
| 37 | static void lpc_init(device_t dev) |
| 38 | { |
| 39 | u8 byte; |
| 40 | u32 dword; |
| 41 | device_t sm_dev; |
| 42 | |
| 43 | /* Enable the LPC Controller */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 44 | sm_dev = dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 45 | dword = pci_read_config32(sm_dev, 0x64); |
| 46 | dword |= 1 << 20; |
| 47 | pci_write_config32(sm_dev, 0x64, dword); |
| 48 | |
| 49 | /* Initialize isa dma */ |
| 50 | isa_dma_init(); |
| 51 | |
| 52 | /* Enable DMA transaction on the LPC bus */ |
| 53 | byte = pci_read_config8(dev, 0x40); |
| 54 | byte |= (1 << 2); |
| 55 | pci_write_config8(dev, 0x40, byte); |
| 56 | |
| 57 | /* Disable the timeout mechanism on LPC */ |
| 58 | byte = pci_read_config8(dev, 0x48); |
| 59 | byte &= ~(1 << 7); |
| 60 | pci_write_config8(dev, 0x48, byte); |
| 61 | |
| 62 | /* Disable LPC MSI Capability */ |
| 63 | byte = pci_read_config8(dev, 0x78); |
| 64 | byte &= ~(1 << 1); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 65 | /* Keep the old way. i.e., when bus master/DMA cycle is going |
| 66 | * on on LPC, it holds PCI grant, so no LPC slave cycle can |
| 67 | * interrupt and visit LPC. |
| 68 | */ |
| 69 | byte &= ~(1 << 0); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 70 | pci_write_config8(dev, 0x78, byte); |
| 71 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 72 | /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads |
| 73 | * code from SPI ROM |
| 74 | * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. |
| 75 | * todo: verify both these against BKDG |
| 76 | */ |
| 77 | byte = pci_read_config8(dev, 0xbb); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 78 | byte |= 1 << 0 | 1 << 3; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 79 | pci_write_config8(dev, 0xbb, byte); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 80 | |
| 81 | cmos_check_update_date(); |
| 82 | |
| 83 | /* Initialize the real time clock. |
| 84 | * The 0 argument tells cmos_init not to |
| 85 | * update CMOS unless it is invalid. |
| 86 | * 1 tells cmos_init to always initialize the CMOS. |
| 87 | */ |
Aaron Durbin | 9fde0d7 | 2017-09-15 11:01:17 -0600 | [diff] [blame] | 88 | cmos_init(0); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 89 | |
| 90 | /* Initialize i8259 pic */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 91 | setup_i8259(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 92 | |
| 93 | /* Initialize i8254 timers */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 94 | setup_i8254(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 95 | |
| 96 | /* Set up SERIRQ, enable continuous mode */ |
| 97 | byte = (BIT(4) | BIT(7)); |
| 98 | if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) |
| 99 | byte |= BIT(6); |
| 100 | |
| 101 | pm_write8(PM_SERIRQ_CONF, byte); |
| 102 | } |
| 103 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 104 | static void lpc_read_resources(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 105 | { |
| 106 | struct resource *res; |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 107 | global_nvs_t *gnvs; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 108 | |
| 109 | /* Get the normal pci resources of this device */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 110 | pci_dev_read_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | |
| 112 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 113 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 114 | res->base = 0; |
| 115 | res->size = 0x1000; |
| 116 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 117 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 118 | |
| 119 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
| 120 | res->base = 0xff800000; |
| 121 | res->size = 0x00800000; /* 8 MB for flash */ |
| 122 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 123 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 124 | |
| 125 | /* Add a memory resource for the SPI BAR. */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 126 | fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, |
| 127 | IORESOURCE_SUBTRACTIVE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 128 | |
| 129 | res = new_resource(dev, 3); /* IOAPIC */ |
| 130 | res->base = IO_APIC_ADDR; |
| 131 | res->size = 0x00001000; |
| 132 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 133 | |
| 134 | compact_resources(dev); |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 135 | |
| 136 | /* Allocate ACPI NVS in CBMEM */ |
| 137 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 138 | } |
| 139 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 140 | static void lpc_set_resources(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 141 | { |
| 142 | struct resource *res; |
| 143 | u32 spi_enable_bits; |
| 144 | |
| 145 | /* Special case. The SpiRomEnable and other enables should STAY set. */ |
| 146 | res = find_resource(dev, 2); |
| 147 | spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 148 | spi_enable_bits &= 0xf; |
| 149 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, |
| 150 | res->base | spi_enable_bits); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 151 | |
| 152 | pci_dev_set_resources(dev); |
| 153 | } |
| 154 | |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame^] | 155 | static void set_lpc_resource(device_t child, |
| 156 | int *variable_num, |
| 157 | u16 *reg_var, |
| 158 | u32 *reg, |
| 159 | u32 *reg_x, |
| 160 | u16 reg_size, |
| 161 | u8 *wiosize) |
| 162 | { |
| 163 | struct resource *res; |
| 164 | u32 base, end; |
| 165 | u32 rsize = 0, set = 0, set_x = 0; |
| 166 | u16 var_num; |
| 167 | |
| 168 | var_num = *variable_num; |
| 169 | for (res = child->resource_list; res; res = res->next) { |
| 170 | if (!(res->flags & IORESOURCE_IO)) |
| 171 | continue; |
| 172 | base = res->base; |
| 173 | end = resource_end(res); |
| 174 | /* find a resource size */ |
| 175 | printk(BIOS_DEBUG, |
| 176 | "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", |
| 177 | dev_path(child), base, end); |
| 178 | switch (base) { |
| 179 | case 0x60: /* KB */ |
| 180 | case 0x64: /* MS */ |
| 181 | set |= (1 << 29); |
| 182 | rsize = 1; |
| 183 | break; |
| 184 | case 0x3f8: /* COM1 */ |
| 185 | set |= (1 << 6); |
| 186 | rsize = 8; |
| 187 | break; |
| 188 | case 0x2f8: /* COM2 */ |
| 189 | set |= (1 << 7); |
| 190 | rsize = 8; |
| 191 | break; |
| 192 | case 0x378: /* Parallel 1 */ |
| 193 | set |= (1 << 0); |
| 194 | set |= (1 << 1); /* + 0x778 for ECP */ |
| 195 | rsize = 8; |
| 196 | break; |
| 197 | case 0x3f0: /* FD0 */ |
| 198 | set |= (1 << 26); |
| 199 | rsize = 8; |
| 200 | break; |
| 201 | case 0x220: /* 0x220 - 0x227 */ |
| 202 | set |= (1 << 8); |
| 203 | rsize = 8; |
| 204 | break; |
| 205 | case 0x228: /* 0x228 - 0x22f */ |
| 206 | set |= (1 << 9); |
| 207 | rsize = 8; |
| 208 | break; |
| 209 | case 0x238: /* 0x238 - 0x23f */ |
| 210 | set |= (1 << 10); |
| 211 | rsize = 8; |
| 212 | break; |
| 213 | case 0x300: /* 0x300 - 0x301 */ |
| 214 | set |= (1 << 18); |
| 215 | rsize = 2; |
| 216 | break; |
| 217 | case 0x400: |
| 218 | set_x |= (1 << 16); |
| 219 | rsize = 0x40; |
| 220 | break; |
| 221 | case 0x480: |
| 222 | set_x |= (1 << 17); |
| 223 | rsize = 0x40; |
| 224 | break; |
| 225 | case 0x500: |
| 226 | set_x |= (1 << 18); |
| 227 | rsize = 0x40; |
| 228 | break; |
| 229 | case 0x580: |
| 230 | set_x |= (1 << 19); |
| 231 | rsize = 0x40; |
| 232 | break; |
| 233 | case 0x4700: |
| 234 | set_x |= (1 << 22); |
| 235 | rsize = 0xc; |
| 236 | break; |
| 237 | case 0xfd60: |
| 238 | set_x |= (1 << 23); |
| 239 | rsize = 16; |
| 240 | break; |
| 241 | default: |
| 242 | rsize = 0; |
| 243 | /* try AGESA allocated region in region 0 */ |
| 244 | if ((var_num > 0) && ((base >= reg_var[0]) && |
| 245 | ((base + res->size) <= (reg_var[0] + reg_size)))) |
| 246 | rsize = reg_size; |
| 247 | } |
| 248 | /* check if region found and matches the enable */ |
| 249 | if (res->size <= rsize) { |
| 250 | *reg |= set; |
| 251 | *reg_x |= set_x; |
| 252 | /* check if we can fit resource in variable range */ |
| 253 | } else if ((var_num < 3) && ((res->size <= 16) || |
| 254 | (res->size == 512))) { |
| 255 | /* use variable ranges if pre-defined do not match */ |
| 256 | switch (var_num) { |
| 257 | case 0: |
| 258 | *reg_x |= (1 << 2); |
| 259 | if (res->size <= 16) |
| 260 | *wiosize |= (1 << 0); |
| 261 | break; |
| 262 | case 1: |
| 263 | *reg_x |= (1 << 24); |
| 264 | if (res->size <= 16) |
| 265 | *wiosize |= (1 << 2); |
| 266 | break; |
| 267 | case 2: |
| 268 | *reg_x |= (1 << 25); |
| 269 | if (res->size <= 16) |
| 270 | *wiosize |= (1 << 3); |
| 271 | break; |
| 272 | } |
| 273 | reg_var[var_num++] = |
| 274 | base & 0xffff; |
| 275 | } else { |
| 276 | printk(BIOS_ERR, "cannot fit LPC decode region:"); |
| 277 | printk(BIOS_ERR, "%s, base = 0x%08x, end = 0x%08x\n", |
| 278 | dev_path(child), base, end); |
| 279 | } |
| 280 | } |
| 281 | *variable_num = var_num; |
| 282 | } |
| 283 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 284 | /** |
| 285 | * @brief Enable resources for children devices |
| 286 | * |
| 287 | * @param dev the device whose children's resources are to be enabled |
| 288 | * |
| 289 | */ |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 290 | static void lpc_enable_childrens_resources(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 291 | { |
| 292 | struct bus *link; |
| 293 | u32 reg, reg_x; |
| 294 | int var_num = 0; |
| 295 | u16 reg_var[3]; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 296 | u16 reg_size[1] = {512}; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 297 | u8 wiosize = pci_read_config8(dev, 0x74); |
| 298 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 299 | /* Be a bit relaxed, tolerate that LPC region might be bigger than |
| 300 | * resource we try to fit, do it like this for all regions < 16 bytes. |
| 301 | * If there is a resource > 16 bytes it must be 512 bytes to be able |
| 302 | * to allocate the fresh LPC window. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 303 | * |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 304 | * AGESA likes to enable already one LPC region in wide port base |
| 305 | * 0x64-0x65, using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size |
| 306 | * The code tries to check if resource can fit into this region. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 307 | */ |
| 308 | |
| 309 | reg = pci_read_config32(dev, 0x44); |
| 310 | reg_x = pci_read_config32(dev, 0x48); |
| 311 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 312 | /* check if ranges are free and don't use them if already taken */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 313 | if (reg_x & (1 << 2)) |
| 314 | var_num = 1; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 315 | /* just in case check if someone did not manually set other ranges */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 316 | if (reg_x & (1 << 24)) |
| 317 | var_num = 2; |
| 318 | |
| 319 | if (reg_x & (1 << 25)) |
| 320 | var_num = 3; |
| 321 | |
| 322 | /* check AGESA region size */ |
| 323 | if (wiosize & (1 << 0)) |
| 324 | reg_size[0] = 16; |
| 325 | |
| 326 | reg_var[2] = pci_read_config16(dev, 0x90); |
| 327 | reg_var[1] = pci_read_config16(dev, 0x66); |
| 328 | reg_var[0] = pci_read_config16(dev, 0x64); |
| 329 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 330 | /* todo: clean up the code style here */ |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame^] | 331 | for (link = dev->link_list; link; link = link->next) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 332 | device_t child; |
| 333 | for (child = link->children; child; |
| 334 | child = child->sibling) { |
| 335 | if (child->enabled |
| 336 | && (child->path.type == DEVICE_PATH_PNP)) { |
Richard Spiegel | aa18385 | 2017-10-05 18:53:31 -0700 | [diff] [blame^] | 337 | set_lpc_resource(child, |
| 338 | &var_num, |
| 339 | reg_var, |
| 340 | ®, |
| 341 | ®_x, |
| 342 | reg_size[0], |
| 343 | &wiosize); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 344 | } |
| 345 | } |
| 346 | } |
| 347 | pci_write_config32(dev, 0x44, reg); |
| 348 | pci_write_config32(dev, 0x48, reg_x); |
| 349 | /* Set WideIO for as many IOs found (fall through is on purpose) */ |
| 350 | switch (var_num) { |
| 351 | case 3: |
| 352 | pci_write_config16(dev, 0x90, reg_var[2]); |
| 353 | /* fall through */ |
| 354 | case 2: |
| 355 | pci_write_config16(dev, 0x66, reg_var[1]); |
| 356 | /* fall through */ |
| 357 | case 1: |
| 358 | pci_write_config16(dev, 0x64, reg_var[0]); |
| 359 | break; |
| 360 | } |
| 361 | pci_write_config8(dev, 0x74, wiosize); |
| 362 | } |
| 363 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 364 | static void lpc_enable_resources(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 365 | { |
| 366 | pci_dev_enable_resources(dev); |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 367 | lpc_enable_childrens_resources(dev); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 371 | { |
| 372 | /* Just a dummy */ |
| 373 | return current; |
| 374 | } |
| 375 | |
| 376 | static struct pci_operations lops_pci = { |
| 377 | .set_subsystem = pci_dev_set_subsystem, |
| 378 | }; |
| 379 | |
| 380 | static struct device_operations lpc_ops = { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 381 | .read_resources = lpc_read_resources, |
| 382 | .set_resources = lpc_set_resources, |
| 383 | .enable_resources = lpc_enable_resources, |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 384 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 385 | .write_acpi_tables = southbridge_write_acpi_tables, |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 386 | .init = lpc_init, |
| 387 | .scan_bus = scan_lpc_bus, |
| 388 | .ops_pci = &lops_pci, |
| 389 | }; |
| 390 | |
| 391 | static const unsigned short pci_device_ids[] = { |
| 392 | PCI_DEVICE_ID_AMD_SB900_LPC, |
| 393 | PCI_DEVICE_ID_AMD_CZ_LPC, |
| 394 | 0 |
| 395 | }; |
| 396 | static const struct pci_driver lpc_driver __pci_driver = { |
| 397 | .ops = &lpc_ops, |
| 398 | .vendor = PCI_VENDOR_ID_AMD, |
| 399 | .devices = pci_device_ids, |
| 400 | }; |