Blame - src/southbridge/amd/pi/hudson/Kconfig - coreboot

blob: 026c5fb2d5389af29a83060a14b42650fcbc24f7 [file] [log] [blame]

Elyes HAOUAS	8741510	2020-05-07 11:49:08 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
				3	config SOUTHBRIDGE_AMD_PI_AVALON
				4	bool
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	5
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	6	config SOUTHBRIDGE_AMD_PI_KERN
				7	bool
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	8
Felix Held	70d1c72	2021-04-09 22:22:09 +0200	[diff] [blame]	9	if SOUTHBRIDGE_AMD_PI_AVALON \|\| SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	10
Elyes HAOUAS	00b5f53	2021-02-01 09:45:08 +0100	[diff] [blame]	11	config SOUTHBRIDGE_SPECIFIC_OPTIONS
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	12	def_bool y
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	13	select HAVE_USBDEBUG_OPTIONS
				14	select HAVE_CF9_RESET
				15	select HAVE_CF9_RESET_PREPARE
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	16	select SOC_AMD_COMMON
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	17	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Felix Held	3136424	2021-07-23 19:18:02 +0200	[diff] [blame]	18	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
Kyösti Mälkki	b8cb142	2020-06-23 21:36:14 +0300	[diff] [blame]	19	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Felix Held	4b02769	2021-08-03 20:09:54 +0200	[diff] [blame]	20	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
Felix Held	21cdf0d	2020-11-23 16:24:29 +0100	[diff] [blame]	21	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	22
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	23	config EHCI_BAR
				24	hex
				25	default 0xfef00000
				26
				27	config HUDSON_XHCI_ENABLE
				28	bool "Enable Hudson XHCI Controller"
				29	default y
				30	help
				31	The XHCI controller must be enabled and the XHCI firmware
				32	must be added in order to have USB 3.0 support configured
				33	by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer	45e6c82	2018-12-11 17:53:07 +0100	[diff] [blame]	34	controller if the XHCI firmware is available but the
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	35	XHCI controller is not enabled by coreboot.
				36
				37	config HUDSON_XHCI_FWM
				38	bool "Add xhci firmware"
				39	default y
				40	help
				41	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
				42
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	43	config HUDSON_IMC_ENABLE
				44	bool
				45	default n
				46
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	47	config HUDSON_IMC_FWM
				48	bool "Add IMC firmware"
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	49	depends on HUDSON_IMC_ENABLE
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	50	default y
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	51	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	52	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
				53
				54	config HUDSON_GEC_FWM
				55	bool
				56	default n
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	57	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	58	Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
				59	Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
				60
				61	config HUDSON_PSP
				62	bool
Martin Roth	c681a82	2020-11-16 17:19:17 -0700	[diff] [blame]	63	default y if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	64
Zheng Bao	c5e28ab	2020-10-28 11:38:09 +0800	[diff] [blame]	65	config AMDFW_CONFIG_FILE
				66	string "AMD PSP Firmware config file"
				67	default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01
				68
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	69	config HUDSON_XHCI_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	70	string "XHCI firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	71	default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	72	default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	73	depends on HUDSON_XHCI_FWM
				74
				75	config HUDSON_IMC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	76	string "IMC firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	77	default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	78	default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	79	depends on HUDSON_IMC_FWM
				80
				81	config HUDSON_GEC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	82	string "GEC firmware path and filename"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	83	depends on HUDSON_GEC_FWM
				84
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	85	config AMD_PUBKEY_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	86	depends on HUDSON_PSP
				87	string "AMD public Key"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	88	default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	89
				90	config HUDSON_SATA_MODE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	91	int "SATA Mode"
Piotr Kleinschmidt	cb03065	2019-10-08 16:16:44 +0200	[diff] [blame]	92	default 2
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	93	range 0 6
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	94	help
				95	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
				96	The default is NATIVE.
				97	0: NATIVE mode does not require a ROM.
				98	1: RAID mode must have the two ROM files.
				99	2: AHCI may work with or without AHCI ROM. It depends on the payload support.
				100	For example, seabios does not require the AHCI ROM.
				101	3: LEGACY IDE
				102	4: IDE to AHCI
				103	5: AHCI7804: ROM Required, and AMD driver required in the OS.
				104	6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
				105
				106	comment "NATIVE"
				107	depends on HUDSON_SATA_MODE = 0
				108
				109	comment "RAID"
				110	depends on HUDSON_SATA_MODE = 1
				111
				112	comment "AHCI"
				113	depends on HUDSON_SATA_MODE = 2
				114
				115	comment "LEGACY IDE"
				116	depends on HUDSON_SATA_MODE = 3
				117
				118	comment "IDE to AHCI"
				119	depends on HUDSON_SATA_MODE = 4
				120
				121	comment "AHCI7804"
				122	depends on HUDSON_SATA_MODE = 5
				123
				124	comment "IDE to AHCI7804"
				125	depends on HUDSON_SATA_MODE = 6
				126
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	127	if HUDSON_SATA_MODE = 1
				128
				129	config RAID_ROM_ID
				130	string "RAID device PCI IDs"
				131	default "1022,7802"
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	132	help
				133	1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	134
				135	config RAID_ROM_FILE
				136	string "RAID ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	137	default "src/southbridge/amd/pi/hudson/raid.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	138
				139	config RAID_MISC_ROM_FILE
				140	string "RAID Misc ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	141	default "src/southbridge/amd/pi/hudson/misc.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	142
				143	config RAID_MISC_ROM_POSITION
				144	hex "RAID Misc ROM Position"
				145	default 0xFFF00000
				146	help
				147	The RAID ROM requires that the MISC ROM is located between the range
				148	0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
				149	The CONFIG_ROM_SIZE must be larger than 0x100000.
				150
				151	endif
				152
				153	config HUDSON_LEGACY_FREE
				154	bool "System is legacy free"
				155	help
				156	Select y if there is no keyboard controller in the system.
				157	This sets variables in AGESA and ACPI.
				158
Marshall Dawson	c6be0d8	2017-01-07 18:17:32 -0500	[diff] [blame]	159	config AMDFW_OUTSIDE_CBFS
				160	def_bool n
				161	help
				162	The AMDFW (PSP) is typically locatable in cbfs. Select this
				163	option to manually attach the generated amdfw.rom at an
				164	offset of 0x20000 from the bottom of the coreboot ROM image.
				165
Marc Jones	3eec9dd	2017-04-09 18:00:40 -0600	[diff] [blame]	166	config SERIRQ_CONTINUOUS_MODE
				167	bool
				168	default n
				169	help
				170	Set this option to y for serial IRQ in continuous mode.
				171	Otherwise it is in quiet mode.
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	172
				173	config HUDSON_ACPI_IO_BASE
				174	hex
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	175	default 0x800
				176	help
				177	Base address for the ACPI registers.
				178	This value must match the hardcoded value of AGESA.
				179
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	180	endif