Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Elyes HAOUAS | 24230f6 | 2020-07-27 07:56:14 +0200 | [diff] [blame] | 2 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 3 | #include <stdint.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Kyösti Mälkki | 9f0a2be | 2014-06-30 07:34:36 +0300 | [diff] [blame] | 5 | #include <console/console.h> |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 6 | #include <spi_flash.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 7 | #include <spi-generic.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 8 | #include <device/device.h> |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ops.h> |
Elyes HAOUAS | 24230f6 | 2020-07-27 07:56:14 +0200 | [diff] [blame] | 11 | #include <stddef.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 12 | |
Alexandru Gagniuc | 01e0adf | 2014-03-29 17:07:26 -0500 | [diff] [blame] | 13 | #include <Proc/Fch/FchPlatform.h> |
Martin Roth | 3316cf2 | 2012-12-05 16:22:54 -0700 | [diff] [blame] | 14 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 15 | #define SPI_REG_OPCODE 0x0 |
| 16 | #define SPI_REG_CNTRL01 0x1 |
| 17 | #define SPI_REG_CNTRL02 0x2 |
| 18 | #define CNTRL02_FIFO_RESET (1 << 4) |
| 19 | #define CNTRL02_EXEC_OPCODE (1 << 0) |
| 20 | #define SPI_REG_CNTRL03 0x3 |
| 21 | #define CNTRL03_SPIBUSY (1 << 7) |
| 22 | #define SPI_REG_FIFO 0xc |
| 23 | #define SPI_REG_CNTRL11 0xd |
| 24 | #define CNTRL11_FIFOPTR_MASK 0x07 |
| 25 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 26 | #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 27 | #define AMD_SB_SPI_TX_LEN 64 |
Kyösti Mälkki | 2fa8cc3 | 2014-07-15 02:30:49 +0300 | [diff] [blame] | 28 | #else |
| 29 | #define AMD_SB_SPI_TX_LEN 8 |
| 30 | #endif |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 31 | |
Stefan Reinauer | fce128c | 2015-07-21 12:52:34 -0700 | [diff] [blame] | 32 | static uintptr_t spibar; |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 33 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 34 | static inline uint8_t spi_read(uint8_t reg) |
| 35 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 36 | return read8((void *)(spibar + reg)); |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | static inline void spi_write(uint8_t reg, uint8_t val) |
| 40 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 41 | write8((void *)(spibar + reg), val); |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 42 | } |
| 43 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 44 | static void reset_internal_fifo_pointer(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 45 | { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 46 | uint8_t reg8; |
| 47 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 48 | do { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 49 | reg8 = spi_read(SPI_REG_CNTRL02); |
| 50 | reg8 |= CNTRL02_FIFO_RESET; |
| 51 | spi_write(SPI_REG_CNTRL02, reg8); |
| 52 | } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 53 | } |
| 54 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 55 | static void execute_command(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 56 | { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 57 | uint8_t reg8; |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 58 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 59 | reg8 = spi_read(SPI_REG_CNTRL02); |
| 60 | reg8 |= CNTRL02_EXEC_OPCODE; |
| 61 | spi_write(SPI_REG_CNTRL02, reg8); |
| 62 | |
| 63 | while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && |
| 64 | (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 65 | } |
| 66 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 67 | void spi_init(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 68 | { |
Elyes HAOUAS | a93e754 | 2018-05-19 14:30:47 +0200 | [diff] [blame] | 69 | struct device *dev; |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 70 | |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 71 | dev = pcidev_on_root(0x14, 3); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 72 | spibar = pci_read_config32(dev, 0xA0) & ~0x1F; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 73 | } |
| 74 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 75 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 76 | size_t bytesout, void *din, size_t bytesin) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 77 | { |
Paul Menzel | dee0f88 | 2018-11-10 11:24:38 +0100 | [diff] [blame] | 78 | /* First byte is cmd which can not be sent through FIFO. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 79 | u8 cmd = *(u8 *)dout++; |
| 80 | u8 readoffby1; |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 81 | size_t count; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 82 | |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 83 | bytesout--; |
Kyösti Mälkki | 9f0a2be | 2014-06-30 07:34:36 +0300 | [diff] [blame] | 84 | |
| 85 | /* |
| 86 | * Check if this is a write command attempting to transfer more bytes |
| 87 | * than the controller can handle. Iterations for writes are not |
| 88 | * supported here because each SPI write command needs to be preceded |
| 89 | * and followed by other SPI commands, and this sequence is controlled |
| 90 | * by the SPI chip driver. |
| 91 | */ |
| 92 | if (bytesout > AMD_SB_SPI_TX_LEN) { |
| 93 | printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" |
| 94 | " spi_crop_chunk()?\n"); |
| 95 | return -1; |
| 96 | } |
| 97 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 98 | readoffby1 = bytesout ? 0 : 1; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 99 | |
Arthur Heymans | bbf5de5 | 2022-03-23 22:41:05 +0100 | [diff] [blame] | 100 | if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) { |
| 101 | spi_write(0x1E, 5); |
| 102 | spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ |
| 103 | spi_write(0x1E, 6); |
| 104 | spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ |
| 105 | } else { |
| 106 | u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; |
| 107 | spi_write(SPI_REG_CNTRL01, readwrite); |
| 108 | } |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 109 | spi_write(SPI_REG_OPCODE, cmd); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 110 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 111 | reset_internal_fifo_pointer(); |
| 112 | for (count = 0; count < bytesout; count++, dout++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 113 | spi_write(SPI_REG_FIFO, *(uint8_t *)dout); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 114 | } |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 115 | |
| 116 | reset_internal_fifo_pointer(); |
| 117 | execute_command(); |
| 118 | |
| 119 | reset_internal_fifo_pointer(); |
| 120 | /* Skip the bytes we sent. */ |
| 121 | for (count = 0; count < bytesout; count++) { |
Paul Menzel | 9eb4d0a | 2018-11-10 11:27:02 +0100 | [diff] [blame] | 122 | spi_read(SPI_REG_FIFO); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 123 | } |
| 124 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 125 | for (count = 0; count < bytesin; count++, din++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 126 | *(uint8_t *)din = spi_read(SPI_REG_FIFO); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | return 0; |
| 130 | } |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 131 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 132 | int chipset_volatile_group_begin(const struct spi_flash *flash) |
| 133 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 134 | if (!CONFIG(HUDSON_IMC_FWM)) |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 135 | return 0; |
| 136 | |
| 137 | ImcSleep(NULL); |
| 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | int chipset_volatile_group_end(const struct spi_flash *flash) |
| 142 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 143 | if (!CONFIG(HUDSON_IMC_FWM)) |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 144 | return 0; |
| 145 | |
| 146 | ImcWakeup(NULL); |
| 147 | return 0; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 148 | } |
| 149 | |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 150 | static int xfer_vectors(const struct spi_slave *slave, |
| 151 | struct spi_op vectors[], size_t count) |
| 152 | { |
| 153 | return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); |
| 154 | } |
| 155 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 156 | static const struct spi_ctrlr spi_ctrlr = { |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 157 | .xfer_vector = xfer_vectors, |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 158 | .max_xfer_size = AMD_SB_SPI_TX_LEN, |
Aaron Durbin | 1fcc9f3 | 2018-01-29 11:30:17 -0700 | [diff] [blame] | 159 | .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 160 | }; |
| 161 | |
Furquan Shaikh | 12eca76 | 2017-05-18 14:58:49 -0700 | [diff] [blame] | 162 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 163 | { |
| 164 | .ctrlr = &spi_ctrlr, |
| 165 | .bus_start = 0, |
| 166 | .bus_end = 0, |
| 167 | }, |
| 168 | }; |
| 169 | |
| 170 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |