zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 18 | */ |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 19 | #include <stdint.h> |
| 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 22 | #include <arch/io.h> |
Kyösti Mälkki | 9f0a2be | 2014-06-30 07:34:36 +0300 | [diff] [blame] | 23 | #include <console/console.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 24 | #include <spi-generic.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 25 | #include <device/device.h> |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ops.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 28 | |
Dave Frodin | 9b800ae | 2014-06-11 13:15:56 -0600 | [diff] [blame] | 29 | #if IS_ENABLED (CONFIG_HUDSON_IMC_FWM) |
Alexandru Gagniuc | 01e0adf | 2014-03-29 17:07:26 -0500 | [diff] [blame] | 30 | #include <Proc/Fch/FchPlatform.h> |
Martin Roth | 3316cf2 | 2012-12-05 16:22:54 -0700 | [diff] [blame] | 31 | |
| 32 | static int bus_claimed = 0; |
| 33 | #endif |
| 34 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 35 | #define SPI_REG_OPCODE 0x0 |
| 36 | #define SPI_REG_CNTRL01 0x1 |
| 37 | #define SPI_REG_CNTRL02 0x2 |
| 38 | #define CNTRL02_FIFO_RESET (1 << 4) |
| 39 | #define CNTRL02_EXEC_OPCODE (1 << 0) |
| 40 | #define SPI_REG_CNTRL03 0x3 |
| 41 | #define CNTRL03_SPIBUSY (1 << 7) |
| 42 | #define SPI_REG_FIFO 0xc |
| 43 | #define SPI_REG_CNTRL11 0xd |
| 44 | #define CNTRL11_FIFOPTR_MASK 0x07 |
| 45 | |
Kyösti Mälkki | 2fa8cc3 | 2014-07-15 02:30:49 +0300 | [diff] [blame] | 46 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 47 | #define AMD_SB_SPI_TX_LEN 64 |
Kyösti Mälkki | 2fa8cc3 | 2014-07-15 02:30:49 +0300 | [diff] [blame] | 48 | #else |
| 49 | #define AMD_SB_SPI_TX_LEN 8 |
| 50 | #endif |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 51 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 52 | static u32 spibar; |
| 53 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 54 | static inline uint8_t spi_read(uint8_t reg) |
| 55 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 56 | return read8((void *)(spibar + reg)); |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | static inline void spi_write(uint8_t reg, uint8_t val) |
| 60 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 61 | write8((void *)(spibar + reg), val); |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 62 | } |
| 63 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 64 | static void reset_internal_fifo_pointer(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 65 | { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 66 | uint8_t reg8; |
| 67 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 68 | do { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 69 | reg8 = spi_read(SPI_REG_CNTRL02); |
| 70 | reg8 |= CNTRL02_FIFO_RESET; |
| 71 | spi_write(SPI_REG_CNTRL02, reg8); |
| 72 | } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 73 | } |
| 74 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 75 | static void execute_command(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 76 | { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 77 | uint8_t reg8; |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 78 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 79 | reg8 = spi_read(SPI_REG_CNTRL02); |
| 80 | reg8 |= CNTRL02_EXEC_OPCODE; |
| 81 | spi_write(SPI_REG_CNTRL02, reg8); |
| 82 | |
| 83 | while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && |
| 84 | (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 85 | } |
| 86 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 87 | void spi_init(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 88 | { |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 89 | device_t dev; |
| 90 | |
| 91 | dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); |
| 92 | spibar = pci_read_config32(dev, 0xA0) & ~0x1F; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 93 | } |
| 94 | |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 95 | unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) |
| 96 | { |
| 97 | return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len); |
| 98 | } |
| 99 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 100 | int spi_xfer(struct spi_slave *slave, const void *dout, |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 101 | unsigned int bytesout, void *din, unsigned int bytesin) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 102 | { |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 103 | /* First byte is cmd which can not being sent through FIFO. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 104 | u8 cmd = *(u8 *)dout++; |
| 105 | u8 readoffby1; |
| 106 | u8 count; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 107 | |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 108 | bytesout--; |
Kyösti Mälkki | 9f0a2be | 2014-06-30 07:34:36 +0300 | [diff] [blame] | 109 | |
| 110 | /* |
| 111 | * Check if this is a write command attempting to transfer more bytes |
| 112 | * than the controller can handle. Iterations for writes are not |
| 113 | * supported here because each SPI write command needs to be preceded |
| 114 | * and followed by other SPI commands, and this sequence is controlled |
| 115 | * by the SPI chip driver. |
| 116 | */ |
| 117 | if (bytesout > AMD_SB_SPI_TX_LEN) { |
| 118 | printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" |
| 119 | " spi_crop_chunk()?\n"); |
| 120 | return -1; |
| 121 | } |
| 122 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 123 | readoffby1 = bytesout ? 0 : 1; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 124 | |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame] | 125 | #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 126 | spi_write(0x1E, 5); |
| 127 | spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ |
| 128 | spi_write(0x1E, 6); |
| 129 | spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame] | 130 | #else |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 131 | u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 132 | spi_write(SPI_REG_CNTRL01, readwrite); |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame] | 133 | #endif |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 134 | spi_write(SPI_REG_OPCODE, cmd); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 135 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 136 | reset_internal_fifo_pointer(); |
| 137 | for (count = 0; count < bytesout; count++, dout++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 138 | spi_write(SPI_REG_FIFO, *(uint8_t *)dout); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 139 | } |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 140 | |
| 141 | reset_internal_fifo_pointer(); |
| 142 | execute_command(); |
| 143 | |
| 144 | reset_internal_fifo_pointer(); |
| 145 | /* Skip the bytes we sent. */ |
| 146 | for (count = 0; count < bytesout; count++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 147 | cmd = spi_read(SPI_REG_FIFO); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | reset_internal_fifo_pointer(); |
| 151 | for (count = 0; count < bytesin; count++, din++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 152 | *(uint8_t *)din = spi_read(SPI_REG_FIFO); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | int spi_claim_bus(struct spi_slave *slave) |
| 158 | { |
Dave Frodin | 9b800ae | 2014-06-11 13:15:56 -0600 | [diff] [blame] | 159 | #if IS_ENABLED (CONFIG_HUDSON_IMC_FWM) |
Martin Roth | 3316cf2 | 2012-12-05 16:22:54 -0700 | [diff] [blame] | 160 | |
| 161 | if (slave->rw == SPI_WRITE_FLAG) { |
| 162 | bus_claimed++; |
| 163 | if (bus_claimed == 1) |
| 164 | ImcSleep(NULL); |
| 165 | } |
| 166 | #endif |
| 167 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 168 | return 0; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 169 | } |
| 170 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 171 | void spi_release_bus(struct spi_slave *slave) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 172 | { |
Dave Frodin | 9b800ae | 2014-06-11 13:15:56 -0600 | [diff] [blame] | 173 | #if IS_ENABLED (CONFIG_HUDSON_IMC_FWM) |
Martin Roth | 3316cf2 | 2012-12-05 16:22:54 -0700 | [diff] [blame] | 174 | |
| 175 | if (slave->rw == SPI_WRITE_FLAG) { |
| 176 | bus_claimed--; |
| 177 | if (bus_claimed <= 0) { |
| 178 | bus_claimed = 0; |
| 179 | ImcWakeup(NULL); |
| 180 | } |
| 181 | } |
| 182 | #endif |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 183 | } |
| 184 | |
Gabe Black | 1e18735 | 2014-03-27 20:37:03 -0700 | [diff] [blame] | 185 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 186 | { |
| 187 | struct spi_slave *slave = malloc(sizeof(*slave)); |
| 188 | |
| 189 | if (!slave) { |
| 190 | return NULL; |
| 191 | } |
| 192 | |
| 193 | memset(slave, 0, sizeof(*slave)); |
| 194 | |
| 195 | return slave; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 196 | } |