AMD SPI: Optimise for longer writes
Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.
Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index f050a63..2aeb2c0 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -20,6 +20,7 @@
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>
+#include <console/console.h>
#include <spi-generic.h>
#include <device/device.h>
#include <device/pci.h>
@@ -101,6 +102,20 @@
u8 count;
bytesout--;
+
+ /*
+ * Check if this is a write command attempting to transfer more bytes
+ * than the controller can handle. Iterations for writes are not
+ * supported here because each SPI write command needs to be preceded
+ * and followed by other SPI commands, and this sequence is controlled
+ * by the SPI chip driver.
+ */
+ if (bytesout > AMD_SB_SPI_TX_LEN) {
+ printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use"
+ " spi_crop_chunk()?\n");
+ return -1;
+ }
+
readoffby1 = bytesout ? 0 : 1;
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE