commit cd49cce7b70e80b4acc49b56bb2bb94370b4d867
author Julius Werner <jwerner@chromium.org> Tue Mar 05 16:53:33 2019 -0800
committer Patrick Georgi <pgeorgi@google.com> Fri Mar 08 08:33:24 2019 +0000
tree 8e89136e2da7cf54453ba8c112eda94415b56242
parent b3a8cc54dbaf833c590a56f912209a5632b71f49

coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/southbridge/amd/agesa/hudson/spi.c

diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index a1c0755..76c5877 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -36,7 +36,7 @@
 #define SPI_REG_CNTRL11		0xd
  #define CNTRL11_FIFOPTR_MASK	0x07
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
+#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
 #define AMD_SB_SPI_TX_LEN	64
 #else
 #define AMD_SB_SPI_TX_LEN	8
@@ -110,7 +110,7 @@
 
 	readoffby1 = bytesout ? 0 : 1;
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
+#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
 	spi_write(0x1E, 5);
 	spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
 	spi_write(0x1E, 6);
@@ -144,7 +144,7 @@
 
 int chipset_volatile_group_begin(const struct spi_flash *flash)
 {
-	if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
+	if (!CONFIG(HUDSON_IMC_FWM))
 		return 0;
 
 	ImcSleep(NULL);
@@ -153,7 +153,7 @@
 
 int chipset_volatile_group_end(const struct spi_flash *flash)
 {
-	if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
+	if (!CONFIG(HUDSON_IMC_FWM))
 		return 0;
 
 	ImcWakeup(NULL);