zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 14 | */ |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 15 | #include <stdint.h> |
| 16 | #include <stdlib.h> |
| 17 | #include <string.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 18 | #include <arch/io.h> |
Kyösti Mälkki | 9f0a2be | 2014-06-30 07:34:36 +0300 | [diff] [blame] | 19 | #include <console/console.h> |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 20 | #include <spi_flash.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 21 | #include <spi-generic.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 22 | #include <device/device.h> |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ops.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 25 | |
Alexandru Gagniuc | 01e0adf | 2014-03-29 17:07:26 -0500 | [diff] [blame] | 26 | #include <Proc/Fch/FchPlatform.h> |
Martin Roth | 3316cf2 | 2012-12-05 16:22:54 -0700 | [diff] [blame] | 27 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 28 | #define SPI_REG_OPCODE 0x0 |
| 29 | #define SPI_REG_CNTRL01 0x1 |
| 30 | #define SPI_REG_CNTRL02 0x2 |
| 31 | #define CNTRL02_FIFO_RESET (1 << 4) |
| 32 | #define CNTRL02_EXEC_OPCODE (1 << 0) |
| 33 | #define SPI_REG_CNTRL03 0x3 |
| 34 | #define CNTRL03_SPIBUSY (1 << 7) |
| 35 | #define SPI_REG_FIFO 0xc |
| 36 | #define SPI_REG_CNTRL11 0xd |
| 37 | #define CNTRL11_FIFOPTR_MASK 0x07 |
| 38 | |
Kyösti Mälkki | 2fa8cc3 | 2014-07-15 02:30:49 +0300 | [diff] [blame] | 39 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 40 | #define AMD_SB_SPI_TX_LEN 64 |
Kyösti Mälkki | 2fa8cc3 | 2014-07-15 02:30:49 +0300 | [diff] [blame] | 41 | #else |
| 42 | #define AMD_SB_SPI_TX_LEN 8 |
| 43 | #endif |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 44 | |
Stefan Reinauer | fce128c | 2015-07-21 12:52:34 -0700 | [diff] [blame] | 45 | static uintptr_t spibar; |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 46 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 47 | static inline uint8_t spi_read(uint8_t reg) |
| 48 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 49 | return read8((void *)(spibar + reg)); |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 50 | } |
| 51 | |
| 52 | static inline void spi_write(uint8_t reg, uint8_t val) |
| 53 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 54 | write8((void *)(spibar + reg), val); |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 55 | } |
| 56 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 57 | static void reset_internal_fifo_pointer(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 58 | { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 59 | uint8_t reg8; |
| 60 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 61 | do { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 62 | reg8 = spi_read(SPI_REG_CNTRL02); |
| 63 | reg8 |= CNTRL02_FIFO_RESET; |
| 64 | spi_write(SPI_REG_CNTRL02, reg8); |
| 65 | } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 66 | } |
| 67 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 68 | static void execute_command(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 69 | { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 70 | uint8_t reg8; |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 71 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 72 | reg8 = spi_read(SPI_REG_CNTRL02); |
| 73 | reg8 |= CNTRL02_EXEC_OPCODE; |
| 74 | spi_write(SPI_REG_CNTRL02, reg8); |
| 75 | |
| 76 | while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && |
| 77 | (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 78 | } |
| 79 | |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 80 | void spi_init(void) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 81 | { |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 82 | device_t dev; |
| 83 | |
| 84 | dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); |
| 85 | spibar = pci_read_config32(dev, 0xA0) & ~0x1F; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 86 | } |
| 87 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 88 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 89 | size_t bytesout, void *din, size_t bytesin) |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 90 | { |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 91 | /* First byte is cmd which can not being sent through FIFO. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 92 | u8 cmd = *(u8 *)dout++; |
| 93 | u8 readoffby1; |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 94 | size_t count; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 95 | |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 96 | bytesout--; |
Kyösti Mälkki | 9f0a2be | 2014-06-30 07:34:36 +0300 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * Check if this is a write command attempting to transfer more bytes |
| 100 | * than the controller can handle. Iterations for writes are not |
| 101 | * supported here because each SPI write command needs to be preceded |
| 102 | * and followed by other SPI commands, and this sequence is controlled |
| 103 | * by the SPI chip driver. |
| 104 | */ |
| 105 | if (bytesout > AMD_SB_SPI_TX_LEN) { |
| 106 | printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" |
| 107 | " spi_crop_chunk()?\n"); |
| 108 | return -1; |
| 109 | } |
| 110 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 111 | readoffby1 = bytesout ? 0 : 1; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 112 | |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 113 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 114 | spi_write(0x1E, 5); |
| 115 | spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ |
| 116 | spi_write(0x1E, 6); |
| 117 | spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame] | 118 | #else |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 119 | u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 120 | spi_write(SPI_REG_CNTRL01, readwrite); |
Siyuan Wang | 9157145 | 2013-07-09 17:32:42 +0800 | [diff] [blame] | 121 | #endif |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 122 | spi_write(SPI_REG_OPCODE, cmd); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 123 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 124 | reset_internal_fifo_pointer(); |
| 125 | for (count = 0; count < bytesout; count++, dout++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 126 | spi_write(SPI_REG_FIFO, *(uint8_t *)dout); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 127 | } |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 128 | |
| 129 | reset_internal_fifo_pointer(); |
| 130 | execute_command(); |
| 131 | |
| 132 | reset_internal_fifo_pointer(); |
| 133 | /* Skip the bytes we sent. */ |
| 134 | for (count = 0; count < bytesout; count++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 135 | cmd = spi_read(SPI_REG_FIFO); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 136 | } |
| 137 | |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 138 | for (count = 0; count < bytesin; count++, din++) { |
Alexandru Gagniuc | 991e951 | 2014-04-19 22:21:27 -0500 | [diff] [blame] | 139 | *(uint8_t *)din = spi_read(SPI_REG_FIFO); |
Zheng Bao | 7bcffa5 | 2012-11-28 11:36:52 +0800 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | return 0; |
| 143 | } |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 144 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 145 | int chipset_volatile_group_begin(const struct spi_flash *flash) |
| 146 | { |
| 147 | if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) |
| 148 | return 0; |
| 149 | |
| 150 | ImcSleep(NULL); |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | int chipset_volatile_group_end(const struct spi_flash *flash) |
| 155 | { |
| 156 | if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) |
| 157 | return 0; |
| 158 | |
| 159 | ImcWakeup(NULL); |
| 160 | return 0; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 161 | } |
| 162 | |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame^] | 163 | static int xfer_vectors(const struct spi_slave *slave, |
| 164 | struct spi_op vectors[], size_t count) |
| 165 | { |
| 166 | return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); |
| 167 | } |
| 168 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 169 | static const struct spi_ctrlr spi_ctrlr = { |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame^] | 170 | .xfer_vector = xfer_vectors, |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 171 | .max_xfer_size = AMD_SB_SPI_TX_LEN, |
Aaron Durbin | 1fcc9f3 | 2018-01-29 11:30:17 -0700 | [diff] [blame] | 172 | .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 173 | }; |
| 174 | |
Furquan Shaikh | 12eca76 | 2017-05-18 14:58:49 -0700 | [diff] [blame] | 175 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 176 | { |
| 177 | .ctrlr = &spi_ctrlr, |
| 178 | .bus_start = 0, |
| 179 | .bus_end = 0, |
| 180 | }, |
| 181 | }; |
| 182 | |
| 183 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |