Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 7 | #include <acpi/acpi.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 8 | #include <bootstate.h> |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 9 | #include <console/console.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 13 | #include <pc80/mc146818rtc.h> |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 14 | #include <drivers/uart/uart8250reg.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 15 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 16 | #include <soc/iomap.h> |
| 17 | #include <soc/irq.h> |
| 18 | #include <soc/lpc.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 19 | #include <soc/pci_devs.h> |
Angel Pons | b5320b2 | 2020-07-07 18:27:30 +0200 | [diff] [blame] | 20 | #include <soc/pm.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 21 | #include <soc/ramstage.h> |
| 22 | #include <soc/spi.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 23 | #include "chip.h" |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 24 | #include <acpi/acpigen.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 25 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 26 | static void sc_add_mmio_resources(struct device *dev) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 27 | { |
Kyösti Mälkki | 5a55a45 | 2021-06-24 20:49:05 +0300 | [diff] [blame] | 28 | mmio_range(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 29 | mmio_range(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 30 | mmio_range(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 31 | mmio_range(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 32 | mmio_range(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 33 | mmio_range(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 34 | mmio_range(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 35 | mmio_range(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 39 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 40 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 41 | |
| 42 | static inline int io_range_in_default(int base, int size) |
| 43 | { |
| 44 | /* Does it start above the range? */ |
| 45 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 46 | return 0; |
| 47 | |
| 48 | /* Is it entirely contained? */ |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 49 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 50 | return 1; |
| 51 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 52 | /* This will return not in range for partial overlaps */ |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | /* |
| 57 | * Note: this function assumes there is no overlap with the default LPC device's |
| 58 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 59 | */ |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 60 | static void sc_add_io_resource(struct device *dev, int base, int size, int index) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 61 | { |
| 62 | struct resource *res; |
| 63 | |
| 64 | if (io_range_in_default(base, size)) |
| 65 | return; |
| 66 | |
| 67 | res = new_resource(dev, index); |
| 68 | res->base = base; |
| 69 | res->size = size; |
| 70 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 71 | } |
| 72 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 73 | static void sc_add_io_resources(struct device *dev) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 74 | { |
| 75 | struct resource *res; |
| 76 | |
| 77 | /* Add the default claimed IO range for the LPC device. */ |
| 78 | res = new_resource(dev, 0); |
| 79 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 80 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 81 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 82 | |
| 83 | /* GPIO */ |
Frans Hendriks | 802f43d | 2018-10-29 14:17:16 +0100 | [diff] [blame] | 84 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 85 | |
| 86 | /* ACPI */ |
Frans Hendriks | 802f43d | 2018-10-29 14:17:16 +0100 | [diff] [blame] | 87 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 88 | } |
| 89 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 90 | static void sc_read_resources(struct device *dev) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 91 | { |
| 92 | /* Get the normal PCI resources of this device. */ |
| 93 | pci_dev_read_resources(dev); |
| 94 | |
| 95 | /* Add non-standard MMIO resources. */ |
| 96 | sc_add_mmio_resources(dev); |
| 97 | |
| 98 | /* Add IO resources. */ |
| 99 | sc_add_io_resources(dev); |
| 100 | } |
| 101 | |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 102 | /* |
| 103 | * The UART hardware loses power while in suspend. Because of this the kernel |
| 104 | * can hang because it doesn't re-initialize serial ports it is using for |
| 105 | * consoles at resume time. The following function configures the UART |
| 106 | * if the hardware is enabled though it may not be the correct baud rate |
| 107 | * or configuration. This is definitely a hack, but it helps the kernel |
| 108 | * along. |
| 109 | */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 110 | static void com1_configure_resume(struct device *dev) |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 111 | { |
| 112 | const uint16_t port = 0x3f8; |
| 113 | |
Martin Roth | 99a3bba | 2014-12-07 14:57:26 -0700 | [diff] [blame] | 114 | /* Is the UART I/O port enabled? */ |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 115 | if (!(pci_read_config32(dev, UART_CONT) & 1)) |
| 116 | return; |
| 117 | |
| 118 | /* Disable interrupts */ |
| 119 | outb(0x0, port + UART8250_IER); |
| 120 | |
| 121 | /* Enable FIFOs */ |
| 122 | outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); |
| 123 | |
| 124 | /* assert DTR and RTS so the other end is happy */ |
| 125 | outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); |
| 126 | |
| 127 | /* DLAB on */ |
| 128 | outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); |
| 129 | |
| 130 | /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ |
| 131 | outb(1, port + UART8250_DLL); |
| 132 | outb(0, port + UART8250_DLM); |
| 133 | |
| 134 | /* Set to 3 for 8N1 */ |
| 135 | outb(3, port + UART8250_LCR); |
| 136 | } |
| 137 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 138 | static void sc_init(struct device *dev) |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 139 | { |
| 140 | int i; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 141 | u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); |
Alexander Couzens | 316170e | 2015-11-24 09:46:18 +0100 | [diff] [blame] | 142 | u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 143 | u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 144 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 145 | const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 146 | struct soc_intel_baytrail_config *config = config_of(dev); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 147 | |
| 148 | /* Set up the PIRQ PIC routing based on static config. */ |
| 149 | for (i = 0; i < NUM_PIRQS; i++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 150 | write8(pr_base + i, ir->pic[i]); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 151 | } |
| 152 | /* Set up the per device PIRQ routing base on static config. */ |
| 153 | for (i = 0; i < NUM_IR_DEVS; i++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 154 | write16(ir_base + i, ir->pcidev[i]); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 155 | } |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 156 | |
| 157 | /* Route SCI to IRQ9 */ |
| 158 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 159 | |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 160 | cmos_init(rtc_failure()); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 161 | |
| 162 | if (config->disable_slp_x_stretch_sus_fail) { |
| 163 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 164 | write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 165 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 166 | } else { |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 167 | write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 168 | } |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 169 | |
Kyösti Mälkki | 9e94dbf | 2015-01-08 20:03:18 +0200 | [diff] [blame] | 170 | if (acpi_is_wakeup_s3()) |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 171 | com1_configure_resume(dev); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 172 | } |
| 173 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 174 | /* |
| 175 | * Common code for the south cluster devices. |
| 176 | */ |
| 177 | |
Martin Roth | 99a3bba | 2014-12-07 14:57:26 -0700 | [diff] [blame] | 178 | /* Set bit in function disable register to hide this device. */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 179 | static void sc_disable_devfn(struct device *dev) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 180 | { |
Angel Pons | e80d17f | 2020-07-07 17:25:38 +0200 | [diff] [blame] | 181 | void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 182 | void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 183 | uint32_t mask = 0; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 184 | uint32_t mask2 = 0; |
| 185 | |
| 186 | switch (dev->path.pci.devfn) { |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 187 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 188 | mask |= MMC_DIS; |
| 189 | break; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 190 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 191 | mask |= SDIO_DIS; |
| 192 | break; |
| 193 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 194 | mask |= SD_DIS; |
| 195 | break; |
| 196 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 197 | mask |= SATA_DIS; |
| 198 | break; |
| 199 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 200 | mask |= XHCI_DIS; |
| 201 | /* Disable super speed PHY when XHCI is not available. */ |
| 202 | mask2 |= USH_SS_PHY_DIS; |
| 203 | break; |
| 204 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 205 | mask |= LPE_DIS; |
| 206 | break; |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 207 | case PCI_DEVFN(MMC45_DEV, MMC45_FUNC): |
| 208 | mask |= MMC45_DIS; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 209 | break; |
| 210 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 211 | mask |= SIO_DMA1_DIS; |
| 212 | break; |
| 213 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 214 | mask |= I2C1_DIS; |
| 215 | break; |
| 216 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 217 | mask |= I2C1_DIS; |
| 218 | break; |
| 219 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 220 | mask |= I2C3_DIS; |
| 221 | break; |
| 222 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 223 | mask |= I2C4_DIS; |
| 224 | break; |
| 225 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 226 | mask |= I2C5_DIS; |
| 227 | break; |
| 228 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 229 | mask |= I2C6_DIS; |
| 230 | break; |
| 231 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 232 | mask |= I2C7_DIS; |
| 233 | break; |
| 234 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 235 | mask |= TXE_DIS; |
| 236 | break; |
| 237 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 238 | mask |= HDA_DIS; |
| 239 | break; |
| 240 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 241 | mask |= PCIE_PORT1_DIS; |
| 242 | break; |
| 243 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 244 | mask |= PCIE_PORT2_DIS; |
| 245 | break; |
| 246 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 247 | mask |= PCIE_PORT3_DIS; |
| 248 | break; |
| 249 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 250 | mask |= PCIE_PORT4_DIS; |
| 251 | break; |
| 252 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 253 | mask |= EHCI_DIS; |
| 254 | break; |
| 255 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 256 | mask |= SIO_DMA2_DIS; |
| 257 | break; |
| 258 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 259 | mask |= PWM1_DIS; |
| 260 | break; |
| 261 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 262 | mask |= PWM2_DIS; |
| 263 | break; |
| 264 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 265 | mask |= HSUART1_DIS; |
| 266 | break; |
| 267 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 268 | mask |= HSUART2_DIS; |
| 269 | break; |
| 270 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 271 | mask |= SPI_DIS; |
| 272 | break; |
| 273 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 274 | mask2 |= SMBUS_DIS; |
| 275 | break; |
| 276 | } |
| 277 | |
| 278 | if (mask != 0) { |
| 279 | write32(func_dis, read32(func_dis) | mask); |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 280 | /* Ensure posted write hits */ |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 281 | read32(func_dis); |
| 282 | } |
| 283 | |
| 284 | if (mask2 != 0) { |
| 285 | write32(func_dis2, read32(func_dis2) | mask2); |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 286 | /* Ensure posted write hits */ |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 287 | read32(func_dis2); |
| 288 | } |
| 289 | } |
| 290 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 291 | static inline void set_d3hot_bits(struct device *dev, int offset) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 292 | { |
| 293 | uint32_t reg8; |
| 294 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 295 | reg8 = pci_read_config8(dev, offset + 4); |
| 296 | reg8 |= 0x3; |
| 297 | pci_write_config8(dev, offset + 4, reg8); |
| 298 | } |
| 299 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 300 | /* |
| 301 | * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into |
| 302 | * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio. |
| 303 | */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 304 | static void hda_work_around(struct device *dev) |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 305 | { |
Angel Pons | e80d17f | 2020-07-07 17:25:38 +0200 | [diff] [blame] | 306 | void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 307 | |
| 308 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 309 | pci_write_config8(dev, 0x43, 0xd7); |
| 310 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 311 | /* |
| 312 | * Need to set bit 0 of GCTL to take the device out of reset. |
| 313 | * However, that requires setting up the 64-bit BAR. |
| 314 | */ |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 315 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 316 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 317 | pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 318 | write32(gctl, read32(gctl) | 0x1); |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 319 | pci_write_config16(dev, PCI_COMMAND, 0); |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 320 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 321 | } |
| 322 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 323 | static int place_device_in_d3hot(struct device *dev) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 324 | { |
Martin Roth | 57e8909 | 2019-10-23 21:45:23 -0600 | [diff] [blame] | 325 | unsigned int offset; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 326 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 327 | /* |
| 328 | * Parts of the HDA block are used for LPE audio as well. |
| 329 | * Therefore assume the HDA will never be put into D3Hot. |
| 330 | */ |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 331 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 332 | hda_work_around(dev); |
| 333 | return 0; |
| 334 | } |
| 335 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 336 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 337 | |
| 338 | if (offset != 0) { |
| 339 | set_d3hot_bits(dev, offset); |
| 340 | return 0; |
| 341 | } |
| 342 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 343 | /* |
| 344 | * For some reason some of the devices don't have the capability pointer set correctly. |
| 345 | * Work around this by hard coding the offset. |
| 346 | */ |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 347 | switch (dev->path.pci.devfn) { |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 348 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 349 | offset = 0x80; |
| 350 | break; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 351 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 352 | offset = 0x80; |
| 353 | break; |
| 354 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 355 | offset = 0x80; |
| 356 | break; |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 357 | case PCI_DEVFN(MMC45_DEV, MMC45_FUNC): |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 358 | offset = 0x80; |
| 359 | break; |
| 360 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 361 | offset = 0x80; |
| 362 | break; |
| 363 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 364 | offset = 0x80; |
| 365 | break; |
| 366 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 367 | offset = 0x80; |
| 368 | break; |
| 369 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 370 | offset = 0x80; |
| 371 | break; |
| 372 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 373 | offset = 0x80; |
| 374 | break; |
| 375 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 376 | offset = 0x80; |
| 377 | break; |
| 378 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 379 | offset = 0x80; |
| 380 | break; |
| 381 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 382 | offset = 0x80; |
| 383 | break; |
| 384 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 385 | offset = 0x80; |
| 386 | break; |
| 387 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 388 | offset = 0x80; |
| 389 | break; |
| 390 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 391 | offset = 0x80; |
| 392 | break; |
| 393 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 394 | offset = 0x80; |
| 395 | break; |
| 396 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 397 | offset = 0x80; |
| 398 | break; |
| 399 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 400 | offset = 0x80; |
| 401 | break; |
| 402 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 403 | offset = 0x80; |
| 404 | break; |
| 405 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 406 | offset = 0x70; |
| 407 | break; |
| 408 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 409 | offset = 0x70; |
| 410 | break; |
| 411 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 412 | offset = 0x70; |
| 413 | break; |
| 414 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 415 | offset = 0x50; |
| 416 | break; |
| 417 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 418 | offset = 0x50; |
| 419 | break; |
| 420 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
Aaron Durbin | 1eae3ee | 2013-10-30 17:08:59 -0500 | [diff] [blame] | 421 | /* TXE cannot be placed in D3Hot. */ |
| 422 | return 0; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 423 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 424 | offset = 0xa0; |
| 425 | break; |
| 426 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 427 | offset = 0xa0; |
| 428 | break; |
| 429 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 430 | offset = 0xa0; |
| 431 | break; |
| 432 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 433 | offset = 0xa0; |
| 434 | break; |
| 435 | } |
| 436 | |
| 437 | if (offset != 0) { |
| 438 | set_d3hot_bits(dev, offset); |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | return -1; |
| 443 | } |
| 444 | |
| 445 | /* Common PCI device function disable. */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 446 | void southcluster_enable_dev(struct device *dev) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 447 | { |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 448 | uint16_t reg16; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 449 | |
| 450 | if (!dev->enabled) { |
| 451 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 452 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 453 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 454 | dev_path(dev), slot, func); |
| 455 | |
| 456 | /* Ensure memory, io, and bus master are all disabled */ |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 457 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 458 | reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 459 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 460 | |
| 461 | /* Place device in D3Hot */ |
| 462 | if (place_device_in_d3hot(dev) < 0) { |
| 463 | printk(BIOS_WARNING, |
| 464 | "Could not place %02x.%01x into D3Hot. " |
| 465 | "Keeping device visible.\n", slot, func); |
| 466 | return; |
| 467 | } |
| 468 | /* Disable this device if possible */ |
| 469 | sc_disable_devfn(dev); |
| 470 | } else { |
| 471 | /* Enable SERR */ |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 472 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 473 | } |
| 474 | } |
| 475 | |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 476 | static struct device_operations device_ops = { |
| 477 | .read_resources = sc_read_resources, |
| 478 | .set_resources = pci_dev_set_resources, |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 479 | .write_acpi_tables = acpi_write_hpet, |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 480 | .init = sc_init, |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 481 | .enable = southcluster_enable_dev, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 482 | .scan_bus = scan_static_bus, |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 483 | .ops_pci = &soc_pci_ops, |
| 484 | }; |
| 485 | |
| 486 | static const struct pci_driver southcluster __pci_driver = { |
| 487 | .ops = &device_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 488 | .vendor = PCI_VID_INTEL, |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 489 | .device = LPC_DEVID, |
| 490 | }; |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 491 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 492 | int __weak mainboard_get_spi_config(struct spi_config *cfg) |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 493 | { |
| 494 | return -1; |
| 495 | } |
| 496 | |
| 497 | static void finalize_chipset(void *unused) |
| 498 | { |
Angel Pons | e80d17f | 2020-07-07 17:25:38 +0200 | [diff] [blame] | 499 | void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); |
| 500 | void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); |
| 501 | void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 502 | void *etr = (void *)(PMC_BASE_ADDRESS + ETR); |
Angel Pons | c4d4b54 | 2020-07-07 19:00:07 +0200 | [diff] [blame] | 503 | uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 504 | struct spi_config cfg; |
| 505 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 506 | /* Set the lock enable on the BIOS control register */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 507 | write32(bcr, read32(bcr) | BCR_LE); |
| 508 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 509 | /* Set BIOS lock down bit controlling boot block size and swapping */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 510 | write32(gcs, read32(gcs) | BILD); |
| 511 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 512 | /* Lock sleep stretching policy and set SMI lock */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 513 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 514 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 515 | /* Set the CF9 lock */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 516 | write32(etr, read32(etr) | CF9LOCK); |
| 517 | |
| 518 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 519 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 520 | } else { |
| 521 | write16(spi + PREOP, cfg.preop); |
| 522 | write16(spi + OPTYPE, cfg.optype); |
| 523 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 524 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 525 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 526 | write32(spi + UVSCC, cfg.uvscc); |
| 527 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 528 | } |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 529 | } |
| 530 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 531 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); |
| 532 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); |