commit e80d17f602e841e826e0892e4e44c9e1a9810cc0
author Angel Pons <th3fanbus@gmail.com> Tue Jul 07 17:25:38 2020 +0200
committer Angel Pons <th3fanbus@gmail.com> Sat Jul 25 10:17:40 2020 +0000
tree 43bde154b250343252fc6655492250b875681d93
parent e4109ff54ff3268fe65739e8efe79b57e67d2e3c

soc/intel/baytrail: Retype some pointers

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/baytrail/southcluster.c

diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index a836d41..dcc48e9 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -198,8 +198,8 @@
 /* Set bit in function disable register to hide this device. */
 static void sc_disable_devfn(struct device *dev)
 {
-	u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
-	u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
+	void *func_dis  = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
+	void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
 	uint32_t mask = 0;
 	uint32_t mask2 = 0;
 
@@ -323,7 +323,7 @@
  */
 static void hda_work_around(struct device *dev)
 {
-	u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
+	void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
 
 	/* Need to set magic register 0x43 to 0xd7 in config space. */
 	pci_write_config8(dev, 0x43, 0xd7);
@@ -542,10 +542,10 @@
 
 static void finalize_chipset(void *unused)
 {
-	u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
-	u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS);
-	u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2);
-	u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR);
+	void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
+	void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS);
+	void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
+	void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
 	u8 *spi = (u8 *)SPI_BASE_ADDRESS;
 	struct spi_config cfg;