commit 802f43d67fc12c738325c860c5547e33141cff66
author Frans Hendriks <fhendriks@eltan.com> Mon Oct 29 14:17:16 2018 +0100
committer Felix Held <felix-coreboot@felixheld.de> Fri Nov 23 17:16:18 2018 +0000
tree 1599063a86ef92fb5e1c2b677ce76feb120e667a
parent 2f1ef98bdcea248671bf2b5ad1547c1dcfec2c64

src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines

The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.

BUG=N/A
TEST=Intel BayTrail CRB

Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Huang Jin <huang.jin@intel.com>

src/soc/intel/baytrail/southcluster.c

diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index c8e08dd..d5e3400 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2008-2009 coresystems GmbH
  * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -106,10 +107,10 @@
 	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	/* GPIO */
-	sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE);
+	sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE);
 
 	/* ACPI */
-	sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
+	sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
 }
 
 static void sc_read_resources(struct device *dev)