Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 7 | #include <option.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 8 | #include <pc80/isa-dma.h> |
| 9 | #include <pc80/i8259.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 11 | #include <arch/ioapic.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 12 | #include <acpi/acpi.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 13 | #include <cpu/x86/smm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 14 | #include <soc/iomap.h> |
| 15 | #include <soc/lpc.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 16 | #include <soc/pch.h> |
| 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/pm.h> |
| 19 | #include <soc/ramstage.h> |
| 20 | #include <soc/rcba.h> |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 21 | #include <soc/intel/broadwell/pch/chip.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 22 | #include <acpi/acpigen.h> |
Arthur Heymans | 2abbe46 | 2019-06-04 14:12:01 +0200 | [diff] [blame] | 23 | #include <southbridge/intel/common/rtc.h> |
Angel Pons | c423ce2 | 2021-04-19 16:13:31 +0200 | [diff] [blame] | 24 | #include <southbridge/intel/lynxpoint/iobp.h> |
Angel Pons | 733f03d | 2021-01-28 16:59:04 +0100 | [diff] [blame] | 25 | #include <southbridge/intel/lynxpoint/lp_gpio.h> |
Duncan Laurie | 35dc00f | 2015-01-18 14:06:42 -0800 | [diff] [blame] | 26 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 27 | static void pch_enable_ioapic(struct device *dev) |
| 28 | { |
| 29 | u32 reg32; |
| 30 | |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 31 | /* Assign unique bus/dev/fn for I/O APIC */ |
| 32 | pci_write_config16(dev, LPC_IBDF, |
| 33 | PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); |
| 34 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 35 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 36 | |
| 37 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 38 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 39 | |
| 40 | /* PCH-LP has 39 redirection entries */ |
| 41 | reg32 &= ~0x00ff0000; |
| 42 | reg32 |= 0x00270000; |
| 43 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 44 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * Select Boot Configuration register (0x03) and |
| 48 | * use Processor System Bus (0x01) to deliver interrupts. |
| 49 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 50 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 51 | } |
| 52 | |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 53 | static void enable_hpet(struct device *dev) |
| 54 | { |
| 55 | size_t i; |
| 56 | |
| 57 | /* Assign unique bus/dev/fn for each HPET */ |
| 58 | for (i = 0; i < 8; ++i) |
| 59 | pci_write_config16(dev, LPC_HnBDF(i), |
| 60 | PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); |
| 61 | } |
| 62 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 63 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 64 | * 0x00 - 0000 = Reserved |
| 65 | * 0x01 - 0001 = Reserved |
| 66 | * 0x02 - 0010 = Reserved |
| 67 | * 0x03 - 0011 = IRQ3 |
| 68 | * 0x04 - 0100 = IRQ4 |
| 69 | * 0x05 - 0101 = IRQ5 |
| 70 | * 0x06 - 0110 = IRQ6 |
| 71 | * 0x07 - 0111 = IRQ7 |
| 72 | * 0x08 - 1000 = Reserved |
| 73 | * 0x09 - 1001 = IRQ9 |
| 74 | * 0x0A - 1010 = IRQ10 |
| 75 | * 0x0B - 1011 = IRQ11 |
| 76 | * 0x0C - 1100 = IRQ12 |
| 77 | * 0x0D - 1101 = Reserved |
| 78 | * 0x0E - 1110 = IRQ14 |
| 79 | * 0x0F - 1111 = IRQ15 |
| 80 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 81 | * 0x80 - The PIRQ is not routed. |
| 82 | */ |
| 83 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 84 | static void pch_pirq_init(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 85 | { |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 86 | struct device *irq_dev; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 87 | |
Angel Pons | 4a6c0a3 | 2020-07-25 15:11:15 +0200 | [diff] [blame] | 88 | const uint8_t pirq = 0x80; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 89 | |
Angel Pons | 4a6c0a3 | 2020-07-25 15:11:15 +0200 | [diff] [blame] | 90 | pci_write_config8(dev, PIRQA_ROUT, pirq); |
| 91 | pci_write_config8(dev, PIRQB_ROUT, pirq); |
| 92 | pci_write_config8(dev, PIRQC_ROUT, pirq); |
| 93 | pci_write_config8(dev, PIRQD_ROUT, pirq); |
| 94 | |
| 95 | pci_write_config8(dev, PIRQE_ROUT, pirq); |
| 96 | pci_write_config8(dev, PIRQF_ROUT, pirq); |
| 97 | pci_write_config8(dev, PIRQG_ROUT, pirq); |
| 98 | pci_write_config8(dev, PIRQH_ROUT, pirq); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 99 | |
Elyes HAOUAS | 4a83f1c | 2016-08-25 21:07:59 +0200 | [diff] [blame] | 100 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 101 | u8 int_pin = 0, int_line = 0; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 102 | |
| 103 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 104 | continue; |
| 105 | |
| 106 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 107 | |
| 108 | switch (int_pin) { |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 109 | case 1: /* INTA# */ |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 110 | case 2: /* INTB# */ |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 111 | case 3: /* INTC# */ |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 112 | case 4: /* INTD# */ |
Angel Pons | 4a6c0a3 | 2020-07-25 15:11:15 +0200 | [diff] [blame] | 113 | int_line = pirq; |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 114 | break; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | if (!int_line) |
| 118 | continue; |
| 119 | |
| 120 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 121 | } |
| 122 | } |
| 123 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 124 | static void pch_power_options(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 125 | { |
| 126 | u16 reg16; |
| 127 | const char *state; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 128 | |
| 129 | /* Which state do we want to goto after g3 (power restored)? |
| 130 | * 0 == S0 Full On |
| 131 | * 1 == S5 Soft Off |
| 132 | * |
| 133 | * If the option is not existent (Laptops), use Kconfig setting. |
| 134 | */ |
Angel Pons | 88dcb31 | 2021-04-26 17:10:28 +0200 | [diff] [blame] | 135 | const unsigned int pwr_on = get_uint_option("power_on_after_fail", |
Angel Pons | 62719a3 | 2021-04-19 13:15:28 +0200 | [diff] [blame] | 136 | CONFIG_MAINBOARD_POWER_FAILURE_STATE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 137 | |
| 138 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 139 | reg16 &= 0xfffe; |
| 140 | switch (pwr_on) { |
| 141 | case MAINBOARD_POWER_OFF: |
| 142 | reg16 |= 1; |
| 143 | state = "off"; |
| 144 | break; |
| 145 | case MAINBOARD_POWER_ON: |
| 146 | reg16 &= ~1; |
| 147 | state = "on"; |
| 148 | break; |
| 149 | case MAINBOARD_POWER_KEEP: |
| 150 | reg16 &= ~1; |
| 151 | state = "state keep"; |
| 152 | break; |
| 153 | default: |
| 154 | state = "undefined"; |
| 155 | } |
Angel Pons | 6fb87c2 | 2020-10-30 20:40:48 +0100 | [diff] [blame] | 156 | |
| 157 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 158 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 159 | |
| 160 | reg16 &= ~(1 << 10); |
| 161 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 162 | |
| 163 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 164 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 165 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 166 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 167 | |
Angel Pons | 02414f8 | 2020-10-28 13:50:38 +0100 | [diff] [blame] | 168 | if (dev->chip_info) { |
| 169 | const struct soc_intel_broadwell_pch_config *config = dev->chip_info; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 170 | |
Angel Pons | 02414f8 | 2020-10-28 13:50:38 +0100 | [diff] [blame] | 171 | /* GPE setup based on device tree configuration */ |
| 172 | enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, |
| 173 | config->gpe0_en_3, config->gpe0_en_4); |
| 174 | |
| 175 | /* SMI setup based on device tree configuration */ |
| 176 | enable_alt_smi(config->alt_gp_smi_en); |
| 177 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 178 | } |
| 179 | |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 180 | static void pch_misc_init(struct device *dev) |
| 181 | { |
| 182 | u8 reg8; |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 183 | u32 reg32; |
| 184 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 185 | /* Prepare sleep mode */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 186 | reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 187 | reg32 &= ~SLP_TYP; |
| 188 | reg32 |= SCI_EN; |
| 189 | outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); |
| 190 | |
| 191 | /* Set up NMI on errors */ |
| 192 | reg8 = inb(0x61); |
| 193 | reg8 &= ~0xf0; /* Higher nibble must be 0 */ |
| 194 | reg8 |= (1 << 2); /* PCI SERR# disable for now */ |
| 195 | outb(reg8, 0x61); |
| 196 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 197 | /* Disable NMI sources */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 198 | reg8 = inb(0x70); |
| 199 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
| 200 | outb(reg8, 0x70); |
| 201 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 202 | /* Indicate DRAM init done for MRC */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 203 | pci_or_config8(dev, GEN_PMCON_2, 1 << 7); |
| 204 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 205 | /* Enable BIOS updates outside of SMM */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 206 | pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); |
| 207 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 208 | /* Clear status bits to prevent unexpected wake */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 209 | RCBA32_OR(0x3310, 0x2f); |
| 210 | |
| 211 | RCBA32_AND_OR(0x3f02, ~0xf, 0); |
| 212 | |
Kenji Chen | 074a028 | 2014-09-20 01:39:20 +0800 | [diff] [blame] | 213 | /* Enable PCIe Releaxed Order */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 214 | RCBA32_OR(0x2314, (1 << 31) | (1 << 7)), |
| 215 | RCBA32_OR(0x1114, (1 << 15) | (1 << 14)), |
| 216 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 217 | /* Setup SERIRQ, enable continuous mode */ |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 218 | reg8 = pci_read_config8(dev, SERIRQ_CNTL); |
| 219 | reg8 |= 1 << 7; |
| 220 | |
| 221 | if (CONFIG(SERIRQ_CONTINUOUS_MODE)) |
| 222 | reg8 |= 1 << 6; |
| 223 | |
| 224 | pci_write_config8(dev, SERIRQ_CNTL, reg8); |
| 225 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 226 | |
| 227 | /* Magic register settings for power management */ |
Angel Pons | 2436ac0 | 2020-10-13 20:03:49 +0200 | [diff] [blame] | 228 | static void pch_pm_init_magic(struct device *dev) |
| 229 | { |
| 230 | pci_write_config8(dev, 0xa9, 0x46); |
| 231 | |
| 232 | RCBA32_AND_OR(0x232c, ~1, 0); |
| 233 | |
| 234 | RCBA32_OR(0x1100, 0x0000c13f); |
| 235 | |
| 236 | RCBA32_AND_OR(0x2320, ~0x60, 0x10); |
| 237 | |
| 238 | RCBA32(0x3314) = 0x00012fff; |
| 239 | |
| 240 | RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400); |
| 241 | |
| 242 | RCBA32(0x3324) = 0x04000000; |
| 243 | RCBA32(0x3368) = 0x00041400; |
| 244 | RCBA32(0x3388) = 0x3f8ddbff; |
| 245 | RCBA32(0x33ac) = 0x00007001; |
| 246 | RCBA32(0x33b0) = 0x00181900; |
| 247 | RCBA32(0x33c0) = 0x00060A00; |
| 248 | RCBA32(0x33d0) = 0x06200840; |
| 249 | RCBA32(0x3a28) = 0x01010101; |
| 250 | RCBA32(0x3a2c) = 0x040c0404; |
| 251 | RCBA32(0x3a9c) = 0x9000000a; |
| 252 | RCBA32(0x2b1c) = 0x03808033; |
| 253 | RCBA32(0x2b34) = 0x80000009; |
| 254 | RCBA32(0x3348) = 0x022ddfff; |
| 255 | RCBA32(0x334c) = 0x00000001; |
| 256 | RCBA32(0x3358) = 0x0001c000; |
| 257 | RCBA32(0x3380) = 0x3f8ddbff; |
| 258 | RCBA32(0x3384) = 0x0001c7e1; |
| 259 | RCBA32(0x338c) = 0x0001c7e1; |
| 260 | RCBA32(0x3398) = 0x0001c000; |
| 261 | RCBA32(0x33a8) = 0x00181900; |
| 262 | RCBA32(0x33dc) = 0x00080000; |
| 263 | RCBA32(0x33e0) = 0x00000001; |
| 264 | RCBA32(0x3a20) = 0x0000040c; |
| 265 | RCBA32(0x3a24) = 0x01010101; |
| 266 | RCBA32(0x3a30) = 0x01010101; |
| 267 | |
| 268 | pci_update_config32(dev, 0xac, ~0x00200000, 0); |
| 269 | |
| 270 | RCBA32_OR(0x0410, 0x00000003); |
| 271 | RCBA32_OR(0x2618, 0x08000000); |
| 272 | RCBA32_OR(0x2300, 0x00000002); |
| 273 | RCBA32_OR(0x2600, 0x00000008); |
| 274 | |
| 275 | RCBA32(0x33b4) = 0x00007001; |
| 276 | RCBA32(0x3350) = 0x022ddfff; |
| 277 | RCBA32(0x3354) = 0x00000001; |
| 278 | |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 279 | /* Power Optimizer */ |
Angel Pons | 2436ac0 | 2020-10-13 20:03:49 +0200 | [diff] [blame] | 280 | RCBA32_OR(0x33d4, 0x08000000); |
| 281 | RCBA32_OR(0x33c8, 0x00000080); |
| 282 | |
| 283 | RCBA32(0x2b10) = 0x0000883c; |
| 284 | RCBA32(0x2b14) = 0x1e0a4616; |
| 285 | RCBA32(0x2b24) = 0x40000005; |
| 286 | RCBA32(0x2b20) = 0x0005db01; |
| 287 | RCBA32(0x3a80) = 0x05145005; |
| 288 | RCBA32(0x3a84) = 0x00001005; |
| 289 | |
| 290 | RCBA32_OR(0x33d4, 0x2fff2fb1); |
| 291 | RCBA32_OR(0x33c8, 0x00008000); |
| 292 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 293 | |
| 294 | static void pch_enable_mphy(void) |
| 295 | { |
| 296 | u32 gpio71_native = gpio_is_native(71); |
| 297 | u32 data_and = 0xffffffff; |
| 298 | u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); |
| 299 | |
| 300 | if (gpio71_native) { |
| 301 | data_or |= (1 << 0); |
| 302 | if (pch_is_wpt()) { |
| 303 | data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); |
| 304 | data_or |= (1 << 5) | (1 << 4); |
| 305 | |
| 306 | if (pch_is_wpt_ulx()) { |
| 307 | /* Check if SATA and USB3 MPHY are enabled */ |
| 308 | u32 strap19 = pch_read_soft_strap(19); |
| 309 | strap19 &= ((1 << 31) | (1 << 30)); |
| 310 | strap19 >>= 30; |
| 311 | if (strap19 == 3) { |
| 312 | data_or |= (1 << 3); |
| 313 | printk(BIOS_DEBUG, "Enable ULX MPHY PG " |
| 314 | "control in single domain\n"); |
| 315 | } else if (strap19 == 0) { |
| 316 | printk(BIOS_DEBUG, "Enable ULX MPHY PG " |
| 317 | "control in split domains\n"); |
| 318 | } else { |
| 319 | printk(BIOS_DEBUG, "Invalid PCH Soft " |
| 320 | "Strap 19 configuration\n"); |
| 321 | } |
| 322 | } else { |
| 323 | data_or |= (1 << 3); |
| 324 | } |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | pch_iobp_update(0xCF000000, data_and, data_or); |
| 329 | } |
| 330 | |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 331 | static void pch_init_deep_sx(struct device *dev) |
| 332 | { |
Angel Pons | 02414f8 | 2020-10-28 13:50:38 +0100 | [diff] [blame] | 333 | const struct soc_intel_broadwell_pch_config *config = dev->chip_info; |
| 334 | |
| 335 | if (!config) |
| 336 | return; |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 337 | |
| 338 | if (config->deep_sx_enable_ac) { |
| 339 | RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); |
| 340 | RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_AC); |
| 341 | } |
| 342 | |
| 343 | if (config->deep_sx_enable_dc) { |
| 344 | RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_DC); |
| 345 | RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_DC); |
| 346 | } |
| 347 | |
| 348 | if (config->deep_sx_enable_ac || config->deep_sx_enable_dc) |
| 349 | RCBA32_OR(DEEP_SX_CONFIG, |
| 350 | DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN); |
| 351 | } |
| 352 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 353 | /* Power Management init */ |
| 354 | static void pch_pm_init(struct device *dev) |
| 355 | { |
| 356 | printk(BIOS_DEBUG, "PCH PM init\n"); |
| 357 | |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 358 | pch_init_deep_sx(dev); |
| 359 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 360 | pch_enable_mphy(); |
| 361 | |
Angel Pons | 2436ac0 | 2020-10-13 20:03:49 +0200 | [diff] [blame] | 362 | pch_pm_init_magic(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 363 | |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 364 | if (pch_is_wpt()) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 365 | RCBA32_OR(0x33e0, (1 << 4) | (1 << 1)); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 366 | RCBA32_OR(0x2b1c, (1 << 22) | (1 << 14) | (1 << 13)); |
| 367 | RCBA32(0x33e4) = 0x16bf0002; |
| 368 | RCBA32_OR(0x33e4, 0x1); |
| 369 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 370 | |
| 371 | pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
| 372 | |
| 373 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 374 | if (RCBA32(FD) & PCH_DISABLE_ADSPD) |
| 375 | RCBA32_OR(0x2b1c, (1 << 29)); |
| 376 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 377 | } |
| 378 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 379 | static void pch_cg_init(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 380 | { |
| 381 | u32 reg32; |
| 382 | u16 reg16; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 383 | struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 384 | |
| 385 | /* DMI */ |
| 386 | RCBA32_OR(0x2234, 0xf); |
| 387 | |
| 388 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 389 | reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ |
| 390 | if (pch_is_wpt()) |
| 391 | reg16 &= ~(1 << 11); |
| 392 | else |
| 393 | reg16 |= (1 << 11); |
| 394 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12); |
| 395 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 396 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 397 | |
| 398 | /* |
| 399 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 400 | * RCBA + 0x2614[23:16] = 0x20 |
| 401 | * RCBA + 0x2614[30:28] = 0x0 |
| 402 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
| 403 | */ |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 404 | RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 405 | |
| 406 | /* Check for 0:2.0@0x08 >= 0x0b */ |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 407 | if (pch_is_wpt() || pci_read_config8(igd_dev, 0x8) >= 0x0b) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 408 | RCBA32_OR(0x2614, (1 << 26)); |
| 409 | |
| 410 | RCBA32_OR(0x900, 0x0000031f); |
| 411 | |
| 412 | reg32 = RCBA32(CG); |
| 413 | if (RCBA32(0x3454) & (1 << 4)) |
| 414 | reg32 &= ~(1 << 29); // LPC Dynamic |
| 415 | else |
| 416 | reg32 |= (1 << 29); // LPC Dynamic |
| 417 | reg32 |= (1 << 31); // LP LPC |
| 418 | reg32 |= (1 << 30); // LP BLA |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 419 | if (RCBA32(0x3454) & (1 << 4)) |
| 420 | reg32 &= ~(1 << 29); |
| 421 | else |
| 422 | reg32 |= (1 << 29); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 423 | reg32 |= (1 << 28); // GPIO Dynamic |
| 424 | reg32 |= (1 << 27); // HPET Dynamic |
| 425 | reg32 |= (1 << 26); // Generic Platform Event Clock |
| 426 | if (RCBA32(BUC) & PCH_DISABLE_GBE) |
| 427 | reg32 |= (1 << 23); // GbE Static |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 428 | if (RCBA32(FD) & PCH_DISABLE_HD_AUDIO) |
| 429 | reg32 |= (1 << 21); // HDA Static |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 430 | reg32 |= (1 << 22); // HDA Dynamic |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 431 | RCBA32(CG) = reg32; |
| 432 | |
| 433 | /* PCH-LP LPC */ |
| 434 | if (pch_is_wpt()) |
| 435 | RCBA32_AND_OR(0x3434, ~0x1f, 0x17); |
| 436 | else |
| 437 | RCBA32_OR(0x3434, 0x7); |
| 438 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 439 | /* SPI */ |
| 440 | RCBA32_OR(0x38c0, 0x3c07); |
| 441 | |
| 442 | pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); |
| 443 | } |
| 444 | |
| 445 | static void pch_set_acpi_mode(void) |
| 446 | { |
Kyösti Mälkki | ad882c3 | 2020-06-02 05:05:30 +0300 | [diff] [blame] | 447 | if (!acpi_is_wakeup_s3()) { |
Kyösti Mälkki | b658548 | 2020-06-01 15:11:14 +0300 | [diff] [blame] | 448 | apm_control(APM_CNT_ACPI_DISABLE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 449 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | static void lpc_init(struct device *dev) |
| 453 | { |
| 454 | /* Legacy initialization */ |
| 455 | isa_dma_init(); |
Arthur Heymans | 2abbe46 | 2019-06-04 14:12:01 +0200 | [diff] [blame] | 456 | sb_rtc_init(); |
Angel Pons | f2e2b96 | 2020-10-13 20:19:40 +0200 | [diff] [blame] | 457 | pch_misc_init(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 458 | |
| 459 | /* Interrupt configuration */ |
| 460 | pch_enable_ioapic(dev); |
| 461 | pch_pirq_init(dev); |
| 462 | setup_i8259(); |
| 463 | i8259_configure_irq_trigger(9, 1); |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 464 | enable_hpet(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 465 | |
| 466 | /* Initialize power management */ |
| 467 | pch_power_options(dev); |
| 468 | pch_pm_init(dev); |
| 469 | pch_cg_init(dev); |
| 470 | |
| 471 | pch_set_acpi_mode(); |
| 472 | } |
| 473 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 474 | static void pch_lpc_add_mmio_resources(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 475 | { |
| 476 | u32 reg; |
| 477 | struct resource *res; |
| 478 | const u32 default_decode_base = IO_APIC_ADDR; |
| 479 | |
| 480 | /* |
| 481 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 482 | * them reserved as that may upset the OS if this range is marked |
| 483 | * as reserved in the e820. |
| 484 | */ |
| 485 | res = new_resource(dev, OIC); |
| 486 | res->base = default_decode_base; |
| 487 | res->size = 0 - default_decode_base; |
| 488 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 489 | |
| 490 | /* RCBA */ |
Angel Pons | 64c6a74 | 2021-01-28 15:09:39 +0100 | [diff] [blame] | 491 | if (default_decode_base > CONFIG_FIXED_RCBA_MMIO_BASE) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 492 | res = new_resource(dev, RCBA); |
Angel Pons | 64c6a74 | 2021-01-28 15:09:39 +0100 | [diff] [blame] | 493 | res->base = CONFIG_FIXED_RCBA_MMIO_BASE; |
| 494 | res->size = CONFIG_RCBA_LENGTH; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 495 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 496 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 497 | } |
| 498 | |
| 499 | /* Check LPC Memory Decode register. */ |
| 500 | reg = pci_read_config32(dev, LGMR); |
| 501 | if (reg & 1) { |
| 502 | reg &= ~0xffff; |
| 503 | if (reg < default_decode_base) { |
| 504 | res = new_resource(dev, LGMR); |
| 505 | res->base = reg; |
| 506 | res->size = 16 * 1024; |
| 507 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 508 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 509 | } |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 514 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 515 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 516 | |
Julius Werner | 7c712bb | 2019-05-01 16:51:20 -0700 | [diff] [blame] | 517 | static inline int pch_io_range_in_default(int base, int size) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 518 | { |
| 519 | /* Does it start above the range? */ |
| 520 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 521 | return 0; |
| 522 | |
| 523 | /* Is it entirely contained? */ |
| 524 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 525 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 526 | return 1; |
| 527 | |
| 528 | /* This will return not in range for partial overlaps. */ |
| 529 | return 0; |
| 530 | } |
| 531 | |
| 532 | /* |
| 533 | * Note: this function assumes there is no overlap with the default LPC device's |
| 534 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 535 | */ |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 536 | static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, |
| 537 | int index) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 538 | { |
| 539 | struct resource *res; |
| 540 | |
| 541 | if (pch_io_range_in_default(base, size)) |
| 542 | return; |
| 543 | |
| 544 | res = new_resource(dev, index); |
| 545 | res->base = base; |
| 546 | res->size = size; |
| 547 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 548 | } |
| 549 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 550 | static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, |
| 551 | int index) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 552 | { |
| 553 | /* |
| 554 | * Check if the register is enabled. If so and the base exceeds the |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 555 | * device's default claim range add the resource. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 556 | */ |
| 557 | if (reg_value & 1) { |
| 558 | u16 base = reg_value & 0xfffc; |
| 559 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 560 | pch_lpc_add_io_resource(dev, base, size, index); |
| 561 | } |
| 562 | } |
| 563 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 564 | static void pch_lpc_add_io_resources(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 565 | { |
| 566 | struct resource *res; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 567 | |
| 568 | /* Add the default claimed IO range for the LPC device. */ |
| 569 | res = new_resource(dev, 0); |
| 570 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 571 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 572 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 573 | |
| 574 | /* GPIOBASE */ |
| 575 | pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, |
| 576 | GPIO_BASE_SIZE, GPIO_BASE); |
| 577 | |
| 578 | /* PMBASE */ |
| 579 | pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); |
| 580 | |
| 581 | /* LPC Generic IO Decode range. */ |
Angel Pons | 02414f8 | 2020-10-28 13:50:38 +0100 | [diff] [blame] | 582 | if (dev->chip_info) { |
| 583 | const struct soc_intel_broadwell_pch_config *config = dev->chip_info; |
| 584 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 585 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 586 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 587 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 588 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 589 | } |
| 590 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 591 | static void pch_lpc_read_resources(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 592 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 593 | /* Get the normal PCI resources of this device. */ |
| 594 | pci_dev_read_resources(dev); |
| 595 | |
| 596 | /* Add non-standard MMIO resources. */ |
| 597 | pch_lpc_add_mmio_resources(dev); |
| 598 | |
| 599 | /* Add IO resources. */ |
| 600 | pch_lpc_add_io_resources(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 601 | } |
| 602 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 603 | static unsigned long broadwell_write_acpi_tables(const struct device *device, |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 604 | unsigned long current, |
| 605 | struct acpi_rsdp *rsdp) |
| 606 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 607 | if (CONFIG(INTEL_PCH_UART_CONSOLE)) |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 608 | current = acpi_write_dbg2_pci_uart(rsdp, current, |
| 609 | (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ? |
| 610 | PCH_DEV_UART1 : PCH_DEV_UART0, |
| 611 | ACPI_ACCESS_SIZE_BYTE_ACCESS); |
| 612 | return acpi_write_hpet(device, current, rsdp); |
| 613 | } |
| 614 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 615 | static struct device_operations device_ops = { |
| 616 | .read_resources = &pch_lpc_read_resources, |
| 617 | .set_resources = &pci_dev_set_resources, |
| 618 | .enable_resources = &pci_dev_enable_resources, |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 619 | .write_acpi_tables = broadwell_write_acpi_tables, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 620 | .init = &lpc_init, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 621 | .scan_bus = &scan_static_bus, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 622 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 623 | }; |
| 624 | |
| 625 | static const unsigned short pci_device_ids[] = { |
| 626 | PCH_LPT_LP_SAMPLE, |
| 627 | PCH_LPT_LP_PREMIUM, |
| 628 | PCH_LPT_LP_MAINSTREAM, |
| 629 | PCH_LPT_LP_VALUE, |
| 630 | PCH_WPT_HSW_U_SAMPLE, |
| 631 | PCH_WPT_BDW_U_SAMPLE, |
| 632 | PCH_WPT_BDW_U_PREMIUM, |
| 633 | PCH_WPT_BDW_U_BASE, |
| 634 | PCH_WPT_BDW_Y_SAMPLE, |
| 635 | PCH_WPT_BDW_Y_PREMIUM, |
| 636 | PCH_WPT_BDW_Y_BASE, |
| 637 | PCH_WPT_BDW_H, |
| 638 | 0 |
| 639 | }; |
| 640 | |
| 641 | static const struct pci_driver pch_lpc __pci_driver = { |
| 642 | .ops = &device_ops, |
| 643 | .vendor = PCI_VENDOR_ID_INTEL, |
| 644 | .devices = pci_device_ids, |
| 645 | }; |