x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 394a9d7..53cc4b8 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -53,22 +53,22 @@
{
u32 reg32;
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control