Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <pc80/isa-dma.h> |
| 28 | #include <pc80/i8259.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <arch/ioapic.h> |
| 31 | #include <arch/acpi.h> |
| 32 | #include <cpu/cpu.h> |
| 33 | #include <cpu/x86/smm.h> |
| 34 | #include <cbmem.h> |
| 35 | #include <reg_script.h> |
| 36 | #include <string.h> |
| 37 | #include <broadwell/gpio.h> |
| 38 | #include <broadwell/iobp.h> |
| 39 | #include <broadwell/iomap.h> |
| 40 | #include <broadwell/lpc.h> |
| 41 | #include <broadwell/nvs.h> |
| 42 | #include <broadwell/pch.h> |
| 43 | #include <broadwell/pci_devs.h> |
| 44 | #include <broadwell/pm.h> |
| 45 | #include <broadwell/ramstage.h> |
| 46 | #include <broadwell/rcba.h> |
| 47 | #include <chip.h> |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 48 | #include <arch/acpi.h> |
| 49 | #include <arch/acpigen.h> |
| 50 | #include <cpu/cpu.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 51 | |
| 52 | static void pch_enable_ioapic(struct device *dev) |
| 53 | { |
| 54 | u32 reg32; |
| 55 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 56 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 57 | |
| 58 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 59 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 60 | |
| 61 | /* PCH-LP has 39 redirection entries */ |
| 62 | reg32 &= ~0x00ff0000; |
| 63 | reg32 |= 0x00270000; |
| 64 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 65 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 66 | |
| 67 | /* |
| 68 | * Select Boot Configuration register (0x03) and |
| 69 | * use Processor System Bus (0x01) to deliver interrupts. |
| 70 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame^] | 71 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 75 | * 0x00 - 0000 = Reserved |
| 76 | * 0x01 - 0001 = Reserved |
| 77 | * 0x02 - 0010 = Reserved |
| 78 | * 0x03 - 0011 = IRQ3 |
| 79 | * 0x04 - 0100 = IRQ4 |
| 80 | * 0x05 - 0101 = IRQ5 |
| 81 | * 0x06 - 0110 = IRQ6 |
| 82 | * 0x07 - 0111 = IRQ7 |
| 83 | * 0x08 - 1000 = Reserved |
| 84 | * 0x09 - 1001 = IRQ9 |
| 85 | * 0x0A - 1010 = IRQ10 |
| 86 | * 0x0B - 1011 = IRQ11 |
| 87 | * 0x0C - 1100 = IRQ12 |
| 88 | * 0x0D - 1101 = Reserved |
| 89 | * 0x0E - 1110 = IRQ14 |
| 90 | * 0x0F - 1111 = IRQ15 |
| 91 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 92 | * 0x80 - The PIRQ is not routed. |
| 93 | */ |
| 94 | |
| 95 | static void pch_pirq_init(device_t dev) |
| 96 | { |
| 97 | device_t irq_dev; |
| 98 | config_t *config = dev->chip_info; |
| 99 | |
| 100 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 101 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 102 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 103 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 104 | |
| 105 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 106 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 107 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 108 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 109 | |
| 110 | for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 111 | u8 int_pin=0, int_line=0; |
| 112 | |
| 113 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 114 | continue; |
| 115 | |
| 116 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 117 | |
| 118 | switch (int_pin) { |
| 119 | case 1: /* INTA# */ int_line = config->pirqa_routing; break; |
| 120 | case 2: /* INTB# */ int_line = config->pirqb_routing; break; |
| 121 | case 3: /* INTC# */ int_line = config->pirqc_routing; break; |
| 122 | case 4: /* INTD# */ int_line = config->pirqd_routing; break; |
| 123 | } |
| 124 | |
| 125 | if (!int_line) |
| 126 | continue; |
| 127 | |
| 128 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | static void pch_power_options(device_t dev) |
| 133 | { |
| 134 | u16 reg16; |
| 135 | const char *state; |
| 136 | /* Get the chip configuration */ |
| 137 | config_t *config = dev->chip_info; |
| 138 | int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 139 | |
| 140 | /* Which state do we want to goto after g3 (power restored)? |
| 141 | * 0 == S0 Full On |
| 142 | * 1 == S5 Soft Off |
| 143 | * |
| 144 | * If the option is not existent (Laptops), use Kconfig setting. |
| 145 | */ |
| 146 | get_option(&pwr_on, "power_on_after_fail"); |
| 147 | |
| 148 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 149 | reg16 &= 0xfffe; |
| 150 | switch (pwr_on) { |
| 151 | case MAINBOARD_POWER_OFF: |
| 152 | reg16 |= 1; |
| 153 | state = "off"; |
| 154 | break; |
| 155 | case MAINBOARD_POWER_ON: |
| 156 | reg16 &= ~1; |
| 157 | state = "on"; |
| 158 | break; |
| 159 | case MAINBOARD_POWER_KEEP: |
| 160 | reg16 &= ~1; |
| 161 | state = "state keep"; |
| 162 | break; |
| 163 | default: |
| 164 | state = "undefined"; |
| 165 | } |
| 166 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 167 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 168 | |
| 169 | /* GPE setup based on device tree configuration */ |
| 170 | enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, |
| 171 | config->gpe0_en_3, config->gpe0_en_4); |
| 172 | |
| 173 | /* SMI setup based on device tree configuration */ |
| 174 | enable_alt_smi(config->alt_gp_smi_en); |
| 175 | } |
| 176 | |
| 177 | static void pch_rtc_init(struct device *dev) |
| 178 | { |
| 179 | u8 reg8; |
| 180 | int rtc_failed; |
| 181 | |
| 182 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 183 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 184 | if (rtc_failed) { |
| 185 | reg8 &= ~RTC_BATTERY_DEAD; |
| 186 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 187 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 188 | } |
| 189 | |
| 190 | cmos_init(rtc_failed); |
| 191 | } |
| 192 | |
| 193 | static const struct reg_script pch_misc_init_script[] = { |
| 194 | /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ |
| 195 | REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), |
| 196 | (1 << 3)|(1 << 11)|(1 << 12)), |
| 197 | /* Prepare sleep mode */ |
| 198 | REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), |
| 199 | /* Setup NMI on errors, disable SERR */ |
| 200 | REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), |
| 201 | /* Disable NMI sources */ |
| 202 | REG_IO_OR8(0x70, (1 << 7)), |
| 203 | /* Indicate DRAM init done for MRC */ |
| 204 | REG_PCI_OR8(GEN_PMCON_2, (1 << 7)), |
| 205 | /* Enable BIOS updates outside of SMM */ |
| 206 | REG_PCI_RMW8(0xdc, ~(1 << 5), 0), |
| 207 | /* Clear status bits to prevent unexpected wake */ |
| 208 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x00000031), |
| 209 | REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), |
| 210 | /* Setup SERIRQ, enable continuous mode */ |
| 211 | REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), |
| 212 | #if !CONFIG_SERIRQ_CONTINUOUS_MODE |
| 213 | REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), |
| 214 | #endif |
| 215 | REG_SCRIPT_END |
| 216 | }; |
| 217 | |
| 218 | /* Magic register settings for power management */ |
| 219 | static const struct reg_script pch_pm_init_script[] = { |
| 220 | REG_PCI_WRITE8(0xa9, 0x46), |
| 221 | REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0), |
| 222 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f), |
| 223 | REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10), |
| 224 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff), |
| 225 | REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400), |
| 226 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000), |
| 227 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400), |
| 228 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff), |
| 229 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001), |
| 230 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900), |
| 231 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00), |
| 232 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840), |
| 233 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101), |
| 234 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404), |
| 235 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a), |
| 236 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033), |
| 237 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009), |
| 238 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff), |
| 239 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001), |
| 240 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000), |
| 241 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff), |
| 242 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1), |
| 243 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1), |
| 244 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000), |
| 245 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900), |
| 246 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000), |
| 247 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001), |
| 248 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c), |
| 249 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101), |
| 250 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101), |
| 251 | REG_PCI_RMW32(0xac, ~0x00200000, 0), |
| 252 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003), |
| 253 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000), |
| 254 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002), |
| 255 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008), |
| 256 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001), |
| 257 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff), |
| 258 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), |
| 259 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), |
| 260 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080), |
| 261 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), |
| 262 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), |
| 263 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), |
| 264 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01), |
| 265 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005), |
| 266 | REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005), |
| 267 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1), |
| 268 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000), |
| 269 | REG_SCRIPT_END |
| 270 | }; |
| 271 | |
| 272 | static void pch_enable_mphy(void) |
| 273 | { |
| 274 | u32 gpio71_native = gpio_is_native(71); |
| 275 | u32 data_and = 0xffffffff; |
| 276 | u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); |
| 277 | |
| 278 | if (gpio71_native) { |
| 279 | data_or |= (1 << 0); |
| 280 | if (pch_is_wpt()) { |
| 281 | data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); |
| 282 | data_or |= (1 << 5) | (1 << 4); |
| 283 | |
| 284 | if (pch_is_wpt_ulx()) { |
| 285 | /* Check if SATA and USB3 MPHY are enabled */ |
| 286 | u32 strap19 = pch_read_soft_strap(19); |
| 287 | strap19 &= ((1 << 31) | (1 << 30)); |
| 288 | strap19 >>= 30; |
| 289 | if (strap19 == 3) { |
| 290 | data_or |= (1 << 3); |
| 291 | printk(BIOS_DEBUG, "Enable ULX MPHY PG " |
| 292 | "control in single domain\n"); |
| 293 | } else if (strap19 == 0) { |
| 294 | printk(BIOS_DEBUG, "Enable ULX MPHY PG " |
| 295 | "control in split domains\n"); |
| 296 | } else { |
| 297 | printk(BIOS_DEBUG, "Invalid PCH Soft " |
| 298 | "Strap 19 configuration\n"); |
| 299 | } |
| 300 | } else { |
| 301 | data_or |= (1 << 3); |
| 302 | } |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | pch_iobp_update(0xCF000000, data_and, data_or); |
| 307 | } |
| 308 | |
| 309 | /* Power Management init */ |
| 310 | static void pch_pm_init(struct device *dev) |
| 311 | { |
| 312 | printk(BIOS_DEBUG, "PCH PM init\n"); |
| 313 | |
| 314 | pch_enable_mphy(); |
| 315 | |
| 316 | reg_script_run_on_dev(dev, pch_pm_init_script); |
| 317 | |
| 318 | if (pch_is_wpt()) |
| 319 | RCBA32_OR(0x33e0, (1 << 4) | (1 << 1)); |
| 320 | |
| 321 | pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
| 322 | |
| 323 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 324 | if (RCBA32(FD) & PCH_DISABLE_ADSPD) |
| 325 | RCBA32_OR(0x2b1c, (1 << 29)); |
| 326 | |
| 327 | /* Lock */ |
| 328 | RCBA32_OR(0x3a6c, 0x00000001); |
| 329 | } |
| 330 | |
| 331 | static void pch_cg_init(device_t dev) |
| 332 | { |
| 333 | u32 reg32; |
| 334 | u16 reg16; |
| 335 | |
| 336 | /* DMI */ |
| 337 | RCBA32_OR(0x2234, 0xf); |
| 338 | |
| 339 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 340 | reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ |
| 341 | if (pch_is_wpt()) |
| 342 | reg16 &= ~(1 << 11); |
| 343 | else |
| 344 | reg16 |= (1 << 11); |
| 345 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12); |
| 346 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 347 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 348 | |
| 349 | /* |
| 350 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 351 | * RCBA + 0x2614[23:16] = 0x20 |
| 352 | * RCBA + 0x2614[30:28] = 0x0 |
| 353 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
| 354 | */ |
| 355 | RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); |
| 356 | |
| 357 | /* Check for 0:2.0@0x08 >= 0x0b */ |
| 358 | if (pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b) |
| 359 | RCBA32_OR(0x2614, (1 << 26)); |
| 360 | |
| 361 | RCBA32_OR(0x900, 0x0000031f); |
| 362 | |
| 363 | reg32 = RCBA32(CG); |
| 364 | if (RCBA32(0x3454) & (1 << 4)) |
| 365 | reg32 &= ~(1 << 29); // LPC Dynamic |
| 366 | else |
| 367 | reg32 |= (1 << 29); // LPC Dynamic |
| 368 | reg32 |= (1 << 31); // LP LPC |
| 369 | reg32 |= (1 << 30); // LP BLA |
| 370 | reg32 |= (1 << 28); // GPIO Dynamic |
| 371 | reg32 |= (1 << 27); // HPET Dynamic |
| 372 | reg32 |= (1 << 26); // Generic Platform Event Clock |
| 373 | if (RCBA32(BUC) & PCH_DISABLE_GBE) |
| 374 | reg32 |= (1 << 23); // GbE Static |
| 375 | reg32 |= (1 << 22); // HDA Dynamic |
| 376 | reg32 |= (1 << 16); // PCI Dynamic |
| 377 | RCBA32(CG) = reg32; |
| 378 | |
| 379 | /* PCH-LP LPC */ |
| 380 | if (pch_is_wpt()) |
| 381 | RCBA32_AND_OR(0x3434, ~0x1f, 0x17); |
| 382 | else |
| 383 | RCBA32_OR(0x3434, 0x7); |
| 384 | |
| 385 | /* SATA */ |
| 386 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); |
| 387 | |
| 388 | /* SPI */ |
| 389 | RCBA32_OR(0x38c0, 0x3c07); |
| 390 | |
| 391 | pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); |
| 392 | } |
| 393 | |
| 394 | static void pch_set_acpi_mode(void) |
| 395 | { |
| 396 | #if CONFIG_HAVE_SMI_HANDLER |
| 397 | if (acpi_slp_type != 3) { |
| 398 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
| 399 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); |
| 400 | printk(BIOS_DEBUG, "done.\n"); |
| 401 | } |
| 402 | #endif /* CONFIG_HAVE_SMI_HANDLER */ |
| 403 | } |
| 404 | |
| 405 | static void lpc_init(struct device *dev) |
| 406 | { |
| 407 | /* Legacy initialization */ |
| 408 | isa_dma_init(); |
| 409 | pch_rtc_init(dev); |
| 410 | reg_script_run_on_dev(dev, pch_misc_init_script); |
| 411 | |
| 412 | /* Interrupt configuration */ |
| 413 | pch_enable_ioapic(dev); |
| 414 | pch_pirq_init(dev); |
| 415 | setup_i8259(); |
| 416 | i8259_configure_irq_trigger(9, 1); |
| 417 | |
| 418 | /* Initialize power management */ |
| 419 | pch_power_options(dev); |
| 420 | pch_pm_init(dev); |
| 421 | pch_cg_init(dev); |
| 422 | |
| 423 | pch_set_acpi_mode(); |
| 424 | } |
| 425 | |
| 426 | static void pch_lpc_add_mmio_resources(device_t dev) |
| 427 | { |
| 428 | u32 reg; |
| 429 | struct resource *res; |
| 430 | const u32 default_decode_base = IO_APIC_ADDR; |
| 431 | |
| 432 | /* |
| 433 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 434 | * them reserved as that may upset the OS if this range is marked |
| 435 | * as reserved in the e820. |
| 436 | */ |
| 437 | res = new_resource(dev, OIC); |
| 438 | res->base = default_decode_base; |
| 439 | res->size = 0 - default_decode_base; |
| 440 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 441 | |
| 442 | /* RCBA */ |
| 443 | if (RCBA_BASE_ADDRESS < default_decode_base) { |
| 444 | res = new_resource(dev, RCBA); |
| 445 | res->base = RCBA_BASE_ADDRESS; |
| 446 | res->size = 16 * 1024; |
| 447 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 448 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 449 | } |
| 450 | |
| 451 | /* Check LPC Memory Decode register. */ |
| 452 | reg = pci_read_config32(dev, LGMR); |
| 453 | if (reg & 1) { |
| 454 | reg &= ~0xffff; |
| 455 | if (reg < default_decode_base) { |
| 456 | res = new_resource(dev, LGMR); |
| 457 | res->base = reg; |
| 458 | res->size = 16 * 1024; |
| 459 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 460 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 461 | } |
| 462 | } |
| 463 | } |
| 464 | |
| 465 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 466 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 467 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 468 | |
| 469 | static inline int pch_io_range_in_default(u16 base, u16 size) |
| 470 | { |
| 471 | /* Does it start above the range? */ |
| 472 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 473 | return 0; |
| 474 | |
| 475 | /* Is it entirely contained? */ |
| 476 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 477 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 478 | return 1; |
| 479 | |
| 480 | /* This will return not in range for partial overlaps. */ |
| 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | /* |
| 485 | * Note: this function assumes there is no overlap with the default LPC device's |
| 486 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 487 | */ |
| 488 | static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) |
| 489 | { |
| 490 | struct resource *res; |
| 491 | |
| 492 | if (pch_io_range_in_default(base, size)) |
| 493 | return; |
| 494 | |
| 495 | res = new_resource(dev, index); |
| 496 | res->base = base; |
| 497 | res->size = size; |
| 498 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 499 | } |
| 500 | |
| 501 | static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) |
| 502 | { |
| 503 | /* |
| 504 | * Check if the register is enabled. If so and the base exceeds the |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 505 | * device's default claim range add the resource. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 506 | */ |
| 507 | if (reg_value & 1) { |
| 508 | u16 base = reg_value & 0xfffc; |
| 509 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 510 | pch_lpc_add_io_resource(dev, base, size, index); |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | static void pch_lpc_add_io_resources(device_t dev) |
| 515 | { |
| 516 | struct resource *res; |
| 517 | config_t *config = dev->chip_info; |
| 518 | |
| 519 | /* Add the default claimed IO range for the LPC device. */ |
| 520 | res = new_resource(dev, 0); |
| 521 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 522 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 523 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 524 | |
| 525 | /* GPIOBASE */ |
| 526 | pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, |
| 527 | GPIO_BASE_SIZE, GPIO_BASE); |
| 528 | |
| 529 | /* PMBASE */ |
| 530 | pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); |
| 531 | |
| 532 | /* LPC Generic IO Decode range. */ |
| 533 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 534 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 535 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 536 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 537 | } |
| 538 | |
| 539 | static void pch_lpc_read_resources(device_t dev) |
| 540 | { |
| 541 | global_nvs_t *gnvs; |
| 542 | |
| 543 | /* Get the normal PCI resources of this device. */ |
| 544 | pci_dev_read_resources(dev); |
| 545 | |
| 546 | /* Add non-standard MMIO resources. */ |
| 547 | pch_lpc_add_mmio_resources(dev); |
| 548 | |
| 549 | /* Add IO resources. */ |
| 550 | pch_lpc_add_io_resources(dev); |
| 551 | |
| 552 | /* Allocate ACPI NVS in CBMEM */ |
| 553 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
| 554 | if (acpi_slp_type != 3 && gnvs) |
| 555 | memset(gnvs, 0, sizeof(global_nvs_t)); |
| 556 | } |
| 557 | |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 558 | static void southcluster_inject_dsdt(void) |
| 559 | { |
| 560 | global_nvs_t *gnvs; |
| 561 | |
| 562 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 563 | if (!gnvs) { |
| 564 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); |
| 565 | if (gnvs) |
| 566 | memset(gnvs, 0, sizeof(*gnvs)); |
| 567 | } |
| 568 | |
| 569 | if (gnvs) { |
| 570 | memset(gnvs, 0, sizeof(*gnvs)); |
| 571 | acpi_create_gnvs(gnvs); |
| 572 | acpi_save_gnvs((unsigned long)gnvs); |
| 573 | /* And tell SMI about it */ |
| 574 | smm_setup_structures(gnvs, NULL, NULL); |
| 575 | |
| 576 | /* Add it to DSDT. */ |
| 577 | acpigen_write_scope("\\"); |
| 578 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 579 | acpigen_pop_len(); |
| 580 | } |
| 581 | } |
| 582 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 583 | static struct device_operations device_ops = { |
| 584 | .read_resources = &pch_lpc_read_resources, |
| 585 | .set_resources = &pci_dev_set_resources, |
| 586 | .enable_resources = &pci_dev_enable_resources, |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 587 | .acpi_inject_dsdt_generator = southcluster_inject_dsdt, |
| 588 | .write_acpi_tables = acpi_write_hpet, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 589 | .init = &lpc_init, |
| 590 | .scan_bus = &scan_static_bus, |
| 591 | .ops_pci = &broadwell_pci_ops, |
| 592 | }; |
| 593 | |
| 594 | static const unsigned short pci_device_ids[] = { |
| 595 | PCH_LPT_LP_SAMPLE, |
| 596 | PCH_LPT_LP_PREMIUM, |
| 597 | PCH_LPT_LP_MAINSTREAM, |
| 598 | PCH_LPT_LP_VALUE, |
| 599 | PCH_WPT_HSW_U_SAMPLE, |
| 600 | PCH_WPT_BDW_U_SAMPLE, |
| 601 | PCH_WPT_BDW_U_PREMIUM, |
| 602 | PCH_WPT_BDW_U_BASE, |
| 603 | PCH_WPT_BDW_Y_SAMPLE, |
| 604 | PCH_WPT_BDW_Y_PREMIUM, |
| 605 | PCH_WPT_BDW_Y_BASE, |
| 606 | PCH_WPT_BDW_H, |
| 607 | 0 |
| 608 | }; |
| 609 | |
| 610 | static const struct pci_driver pch_lpc __pci_driver = { |
| 611 | .ops = &device_ops, |
| 612 | .vendor = PCI_VENDOR_ID_INTEL, |
| 613 | .devices = pci_device_ids, |
| 614 | }; |