broadwell: add new intel SOC
broadwell: Import files from haswell/lynxpoint into soc/broadwell
Reviewed-on: https://chromium-review.googlesource.com/198425
(cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af)
broadwell: Unify and clean up license
Reviewed-on: https://chromium-review.googlesource.com/198426
(cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d)
broadwell: pch.h: split PM into new header
Reviewed-on: https://chromium-review.googlesource.com/198427
(cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373)
broadwell: pch.h: split RCBA into new header
Reviewed-on: https://chromium-review.googlesource.com/198428
(cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135)
broadwell: pch.h: split SATA into new header
Reviewed-on: https://chromium-review.googlesource.com/198429
(cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71)
broadwell: pch.h: split SPI into new header
Reviewed-on: https://chromium-review.googlesource.com/198550
(cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14)
broadwell: pch.h: split SerialIO into new header
Reviewed-on: https://chromium-review.googlesource.com/198551
(cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6)
broadwell: pch.h: split LPC into new header
Reviewed-on: https://chromium-review.googlesource.com/198552
(cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102)
broadwell: pch.h: split GPIO into new header and clean up
Reviewed-on: https://chromium-review.googlesource.com/198553
(cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5)
broadwell: pch.h: split USB into new headers
Reviewed-on: https://chromium-review.googlesource.com/198554
(cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068)
broadwell: Split IOBP into separate files
Reviewed-on: https://chromium-review.googlesource.com/198734
(cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600)
broadwell: smbus: Extract common code and split header
Reviewed-on: https://chromium-review.googlesource.com/198735
(cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d)
broadwell: Create iomap.h header with platform base addresses
Reviewed-on: https://chromium-review.googlesource.com/198736
(cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee)
broadwell: Add header for platform PCI devices
Reviewed-on: https://chromium-review.googlesource.com/198737
(cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500)
broadwell: Split SMM related defines/prototypes to new header
Reviewed-on: https://chromium-review.googlesource.com/198738
(cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4)
broadwell: cpu.h: Split MSR defines to separate header
Reviewed-on: https://chromium-review.googlesource.com/198739
(cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805)
broadwell: Create romstage header file
Reviewed-on: https://chromium-review.googlesource.com/198740
(cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21)
broadwell: Create ram stage header file
Reviewed-on: https://chromium-review.googlesource.com/198741
(cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621)
broadwell: Add reference code data interface
Reviewed-on: https://chromium-review.googlesource.com/198743
(cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95)
broadwell: Clean up ACPI NVS region
Reviewed-on: https://chromium-review.googlesource.com/198897
(cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14)
broadwell: Move CTDP ACPI methods to new file
Reviewed-on: https://chromium-review.googlesource.com/198898
(cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2)
broadwell: Split EHCI and XHCI ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/198899
(cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca)
broadwell: ACPI: Clean up SerialIO ACPI code
Reviewed-on: https://chromium-review.googlesource.com/198910
(cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35)
broadwell: ACPI: Remove special handling of LPT-LP chipset
Reviewed-on: https://chromium-review.googlesource.com/198911
(cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6)
broadwell: ACPI: Clean up use of base address defines
Reviewed-on: https://chromium-review.googlesource.com/198912
(cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75)
broadwell: ACPI: Clean up and fix formatting
Reviewed-on: https://chromium-review.googlesource.com/198913
(cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050)
broadwell: Add header for ACPI defines and prototypes
Reviewed-on: https://chromium-review.googlesource.com/198914
(cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9)
broadwell: Add reset_system function and header
Reviewed-on: https://chromium-review.googlesource.com/198915
(cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef)
broadwell: Move PCODE MMIO defines to systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198916
(cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f)
broadwell: Unify chip.h and add chip.c
Reviewed-on: https://chromium-review.googlesource.com/198917
(cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1)
broadwell: Rename HASWELL_BCLK to CPU_BCLK
Reviewed-on: https://chromium-review.googlesource.com/198918
(cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1)
broadwell: Clean up broadwell/cpu.h
Reviewed-on: https://chromium-review.googlesource.com/198919
(cherry picked from commit 17353803babc8ace279e105c012130678226144e)
broadwell: Clean up broadwell/systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198920
(cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae)
broadwell: Clean up broadwell/pch.h
Reviewed-on: https://chromium-review.googlesource.com/198921
(cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b)
broadwell: Clean up management engine driver
Reviewed-on: https://chromium-review.googlesource.com/198922
(cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72)
broadwell: Add common CPUID and PCI Device ID defines
Reviewed-on: https://chromium-review.googlesource.com/198923
(cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8)
broadwell: Clean up and expand report_platform
Reviewed-on: https://chromium-review.googlesource.com/198924
(cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022)
broadwell: Clean up the bootblock code
Reviewed-on: https://chromium-review.googlesource.com/198925
(cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c)
broadwell: Clean up ramstage device and driver operations
Reviewed-on: https://chromium-review.googlesource.com/199180
(cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569)
broadwell: Clean up XHCI and EHCI ramstage drivers
Reviewed-on: https://chromium-review.googlesource.com/199181
(cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d)
broadwell: Clean up gpio handling code
Reviewed-on: https://chromium-review.googlesource.com/199182
(cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20)
broadwell: Clean up the PCH generic code
Reviewed-on: https://chromium-review.googlesource.com/199183
(cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff)
broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c
Reviewed-on: https://chromium-review.googlesource.com/199184
(cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7)
broadwell: Clean up pmutil.c
Reviewed-on: https://chromium-review.googlesource.com/199185
(cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84)
broadwell: pmutil: Add new acpi_sci_irq() function
Reviewed-on: https://chromium-review.googlesource.com/199186
(cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5)
broadwell: Clean up HDA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199187
(cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d)
broadwell: Clean up cache_as_ram assembly
Reviewed-on: https://chromium-review.googlesource.com/199188
(cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d)
broadwell: romstage: Separate stack helper functions
Reviewed-on: https://chromium-review.googlesource.com/199189
(cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad)
broadwell: Add function to read WPSR from SPI
Reviewed-on: https://chromium-review.googlesource.com/199190
(cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a)
broadwell: Clean up SMBUS code in romstage and ramstage
Reviewed-on: https://chromium-review.googlesource.com/199191
(cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa)
broadwell: SPI: Clean up romstage and ramstage code
Reviewed-on: https://chromium-review.googlesource.com/199192
(cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf)
broadwell: Clean up PCIe root port ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199193
(cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e)
broadwell: Clean up minihd ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199194
(cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e)
broadwell: Update romstage main to follow baytrail format
Reviewed-on: https://chromium-review.googlesource.com/199361
(cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd)
broadwell: Add CPU set_max_freq function for romstage
Reviewed-on: https://chromium-review.googlesource.com/199362
(cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6)
broadwell: romstage: Add chipset_power_state implementation
Reviewed-on: https://chromium-review.googlesource.com/199363
(cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c)
broadwell: romstage: Convert systemagent init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199364
(cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2)
broadwell: romstage: Convert pch init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199365
(cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c)
broadwell: elog: Use chipset_power_state for events
Reviewed-on: https://chromium-review.googlesource.com/199366
(cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9)
broadwell: Clean up SATA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199367
(cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8)
broadwell: Update ramstage graphics driver to support broadwell
Reviewed-on: https://chromium-review.googlesource.com/199368
(cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281)
broadwell: Update raminit to follow baytrail layout
Reviewed-on: https://chromium-review.googlesource.com/199369
(cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523)
broadwell: Update and unify the finalize steps
Reviewed-on: https://chromium-review.googlesource.com/199390
(cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa)
broadwell: Clean up SMM code
Reviewed-on: https://chromium-review.googlesource.com/199391
(cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd)
broadwell: Clean up LPC ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199392
(cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e)
broadwell: Clean up systemagent ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199393
(cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3)
broadwell: Move C-state configuration information to acpi.c
Reviewed-on: https://chromium-review.googlesource.com/199394
(cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990)
broadwell: Clean up CPU ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199395
(cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969)
broadwell: Do not reserve SMM relocation region
Reviewed-on: https://chromium-review.googlesource.com/199402
(cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c)
broadwell: Add an early ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199403
(cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3)
broadwell: Support for second reference code binary
Reviewed-on: https://chromium-review.googlesource.com/199404
(cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2)
broadwell: Clean up serialio init code
Reviewed-on: https://chromium-review.googlesource.com/199405
(cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489)
broadwell: acpi: Add function to fill out FADT
Reviewed-on: https://chromium-review.googlesource.com/199406
(cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74)
broadwell: Update C-state table creation
Reviewed-on: https://chromium-review.googlesource.com/199407
(cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063)
broadwell: acpi: Clean up acpi table creation code
Reviewed-on: https://chromium-review.googlesource.com/199408
(cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146)
broadwell: acpi: Add ACPI table create helper functions
Reviewed-on: https://chromium-review.googlesource.com/199409
(cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c)
broadwell: Add soc/intel/broadwell Makefiles
Reviewed-on: https://chromium-review.googlesource.com/199410
(cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc)
broadwell: Add Kconfig for broadwell soc
Reviewed-on: https://chromium-review.googlesource.com/199411
(cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe)
Squashed 78 commits for broadwell that form a solid code base.
Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6964
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
new file mode 100644
index 0000000..4b21326
--- /dev/null
+++ b/src/soc/intel/broadwell/lpc.c
@@ -0,0 +1,584 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/smm.h>
+#include <cbmem.h>
+#include <reg_script.h>
+#include <string.h>
+#include <broadwell/gpio.h>
+#include <broadwell/iobp.h>
+#include <broadwell/iomap.h>
+#include <broadwell/lpc.h>
+#include <broadwell/nvs.h>
+#include <broadwell/pch.h>
+#include <broadwell/pci_devs.h>
+#include <broadwell/pm.h>
+#include <broadwell/ramstage.h>
+#include <broadwell/rcba.h>
+#include <chip.h>
+
+static void pch_enable_ioapic(struct device *dev)
+{
+ u32 reg32;
+
+ set_ioapic_id(IO_APIC_ADDR, 0x02);
+
+ /* affirm full set of redirection table entries ("write once") */
+ reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+
+ /* PCH-LP has 39 redirection entries */
+ reg32 &= ~0x00ff0000;
+ reg32 |= 0x00270000;
+
+ io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+
+ /*
+ * Select Boot Configuration register (0x03) and
+ * use Processor System Bus (0x01) to deliver interrupts.
+ */
+ io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+}
+
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
+static void pch_pirq_init(device_t dev)
+{
+ device_t irq_dev;
+ config_t *config = dev->chip_info;
+
+ pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+ pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+ pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+ pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+ pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+ pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+ pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+ for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin=0, int_line=0;
+
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
+
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+ switch (int_pin) {
+ case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+ case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+ case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+ case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ }
+
+ if (!int_line)
+ continue;
+
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
+}
+
+static void pch_power_options(device_t dev)
+{
+ u16 reg16;
+ const char *state;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+ int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+ /* Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use Kconfig setting.
+ */
+ get_option(&pwr_on, "power_on_after_fail");
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_3);
+ reg16 &= 0xfffe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg16 |= 1;
+ state = "off";
+ break;
+ case MAINBOARD_POWER_ON:
+ reg16 &= ~1;
+ state = "on";
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg16 &= ~1;
+ state = "state keep";
+ break;
+ default:
+ state = "undefined";
+ }
+ pci_write_config16(dev, GEN_PMCON_3, reg16);
+ printk(BIOS_INFO, "Set power %s after power failure.\n", state);
+
+ /* GPE setup based on device tree configuration */
+ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
+ config->gpe0_en_3, config->gpe0_en_4);
+
+ /* SMI setup based on device tree configuration */
+ enable_alt_smi(config->alt_gp_smi_en);
+}
+
+static void pch_rtc_init(struct device *dev)
+{
+ u8 reg8;
+ int rtc_failed;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ rtc_failed = reg8 & RTC_BATTERY_DEAD;
+ if (rtc_failed) {
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
+ }
+
+ cmos_init(rtc_failed);
+}
+
+static const struct reg_script pch_misc_init_script[] = {
+ /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */
+ REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)),
+ (1 << 3)|(1 << 11)|(1 << 12)),
+ /* Prepare sleep mode */
+ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
+ /* Setup NMI on errors, disable SERR */
+ REG_IO_RMW8(0x61, ~0xf0, (1 << 2)),
+ /* Disable NMI sources */
+ REG_IO_OR8(0x70, (1 << 7)),
+ /* Indicate DRAM init done for MRC */
+ REG_PCI_OR8(GEN_PMCON_2, (1 << 7)),
+ /* Enable BIOS updates outside of SMM */
+ REG_PCI_RMW8(0xdc, ~(1 << 5), 0),
+ /* Clear status bits to prevent unexpected wake */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x00000031),
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0),
+ /* Setup SERIRQ, enable continuous mode */
+ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
+#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+ REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
+#endif
+ REG_SCRIPT_END
+};
+
+/* Magic register settings for power management */
+static const struct reg_script pch_pm_init_script[] = {
+ REG_PCI_WRITE8(0xa9, 0x46),
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f),
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff),
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101),
+ REG_PCI_RMW32(0xac, ~0x00200000, 0),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005),
+ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
+ REG_SCRIPT_END
+};
+
+static void pch_enable_mphy(void)
+{
+ u32 gpio71_native = gpio_is_native(71);
+ u32 data_and = 0xffffffff;
+ u32 data_or = (1 << 14) | (1 << 13) | (1 << 12);
+
+ if (gpio71_native) {
+ data_or |= (1 << 0);
+ if (pch_is_wpt()) {
+ data_and &= ~((1 << 7) | (1 << 6) | (1 << 3));
+ data_or |= (1 << 5) | (1 << 4);
+
+ if (pch_is_wpt_ulx()) {
+ /* Check if SATA and USB3 MPHY are enabled */
+ u32 strap19 = pch_read_soft_strap(19);
+ strap19 &= ((1 << 31) | (1 << 30));
+ strap19 >>= 30;
+ if (strap19 == 3) {
+ data_or |= (1 << 3);
+ printk(BIOS_DEBUG, "Enable ULX MPHY PG "
+ "control in single domain\n");
+ } else if (strap19 == 0) {
+ printk(BIOS_DEBUG, "Enable ULX MPHY PG "
+ "control in split domains\n");
+ } else {
+ printk(BIOS_DEBUG, "Invalid PCH Soft "
+ "Strap 19 configuration\n");
+ }
+ } else {
+ data_or |= (1 << 3);
+ }
+ }
+ }
+
+ pch_iobp_update(0xCF000000, data_and, data_or);
+}
+
+/* Power Management init */
+static void pch_pm_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "PCH PM init\n");
+
+ pch_enable_mphy();
+
+ reg_script_run_on_dev(dev, pch_pm_init_script);
+
+ if (pch_is_wpt())
+ RCBA32_OR(0x33e0, (1 << 4) | (1 << 1));
+
+ pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
+
+ /* Set RCBA 0x2b1c[29]=1 if DSP disabled */
+ if (RCBA32(FD) & PCH_DISABLE_ADSPD)
+ RCBA32_OR(0x2b1c, (1 << 29));
+
+ /* Lock */
+ RCBA32_OR(0x3a6c, 0x00000001);
+}
+
+static void pch_cg_init(device_t dev)
+{
+ u32 reg32;
+ u16 reg16;
+
+ /* DMI */
+ RCBA32_OR(0x2234, 0xf);
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
+ if (pch_is_wpt())
+ reg16 &= ~(1 << 11);
+ else
+ reg16 |= (1 << 11);
+ reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12);
+ reg16 |= (1 << 2); // PCI CLKRUN# Enable
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ /*
+ * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
+ * RCBA + 0x2614[23:16] = 0x20
+ * RCBA + 0x2614[30:28] = 0x0
+ * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
+ */
+ RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500);
+
+ /* Check for 0:2.0@0x08 >= 0x0b */
+ if (pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b)
+ RCBA32_OR(0x2614, (1 << 26));
+
+ RCBA32_OR(0x900, 0x0000031f);
+
+ reg32 = RCBA32(CG);
+ if (RCBA32(0x3454) & (1 << 4))
+ reg32 &= ~(1 << 29); // LPC Dynamic
+ else
+ reg32 |= (1 << 29); // LPC Dynamic
+ reg32 |= (1 << 31); // LP LPC
+ reg32 |= (1 << 30); // LP BLA
+ reg32 |= (1 << 28); // GPIO Dynamic
+ reg32 |= (1 << 27); // HPET Dynamic
+ reg32 |= (1 << 26); // Generic Platform Event Clock
+ if (RCBA32(BUC) & PCH_DISABLE_GBE)
+ reg32 |= (1 << 23); // GbE Static
+ reg32 |= (1 << 22); // HDA Dynamic
+ reg32 |= (1 << 16); // PCI Dynamic
+ RCBA32(CG) = reg32;
+
+ /* PCH-LP LPC */
+ if (pch_is_wpt())
+ RCBA32_AND_OR(0x3434, ~0x1f, 0x17);
+ else
+ RCBA32_OR(0x3434, 0x7);
+
+ /* SATA */
+ RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000);
+
+ /* SPI */
+ RCBA32_OR(0x38c0, 0x3c07);
+
+ pch_iobp_update(0xCE00C000, ~1UL, 0x00000000);
+}
+
+static void pch_set_acpi_mode(void)
+{
+#if CONFIG_HAVE_SMI_HANDLER
+ if (acpi_slp_type != 3) {
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+ outb(APM_CNT_ACPI_DISABLE, APM_CNT);
+ printk(BIOS_DEBUG, "done.\n");
+ }
+#endif /* CONFIG_HAVE_SMI_HANDLER */
+}
+
+static void lpc_init(struct device *dev)
+{
+ /* Legacy initialization */
+ isa_dma_init();
+ pch_rtc_init(dev);
+ reg_script_run_on_dev(dev, pch_misc_init_script);
+
+ /* Interrupt configuration */
+ pch_enable_ioapic(dev);
+ pch_pirq_init(dev);
+ setup_i8259();
+ i8259_configure_irq_trigger(9, 1);
+
+ /* Initialize power management */
+ pch_power_options(dev);
+ pch_pm_init(dev);
+ pch_cg_init(dev);
+
+ pch_set_acpi_mode();
+}
+
+static void pch_lpc_add_mmio_resources(device_t dev)
+{
+ u32 reg;
+ struct resource *res;
+ const u32 default_decode_base = IO_APIC_ADDR;
+
+ /*
+ * Just report all resources from IO-APIC base to 4GiB. Don't mark
+ * them reserved as that may upset the OS if this range is marked
+ * as reserved in the e820.
+ */
+ res = new_resource(dev, OIC);
+ res->base = default_decode_base;
+ res->size = 0 - default_decode_base;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* RCBA */
+ if (RCBA_BASE_ADDRESS < default_decode_base) {
+ res = new_resource(dev, RCBA);
+ res->base = RCBA_BASE_ADDRESS;
+ res->size = 16 * 1024;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+ IORESOURCE_FIXED | IORESOURCE_RESERVE;
+ }
+
+ /* Check LPC Memory Decode register. */
+ reg = pci_read_config32(dev, LGMR);
+ if (reg & 1) {
+ reg &= ~0xffff;
+ if (reg < default_decode_base) {
+ res = new_resource(dev, LGMR);
+ res->base = reg;
+ res->size = 16 * 1024;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+ IORESOURCE_FIXED | IORESOURCE_RESERVE;
+ }
+ }
+}
+
+/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
+#define LPC_DEFAULT_IO_RANGE_LOWER 0
+#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
+
+static inline int pch_io_range_in_default(u16 base, u16 size)
+{
+ /* Does it start above the range? */
+ if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
+ return 0;
+
+ /* Is it entirely contained? */
+ if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
+ (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
+ return 1;
+
+ /* This will return not in range for partial overlaps. */
+ return 0;
+}
+
+/*
+ * Note: this function assumes there is no overlap with the default LPC device's
+ * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
+ */
+static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
+{
+ struct resource *res;
+
+ if (pch_io_range_in_default(base, size))
+ return;
+
+ res = new_resource(dev, index);
+ res->base = base;
+ res->size = size;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
+{
+ /*
+ * Check if the register is enabled. If so and the base exceeds the
+ * device's deafult claim range add the resoure.
+ */
+ if (reg_value & 1) {
+ u16 base = reg_value & 0xfffc;
+ u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1;
+ pch_lpc_add_io_resource(dev, base, size, index);
+ }
+}
+
+static void pch_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+ config_t *config = dev->chip_info;
+
+ /* Add the default claimed IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = LPC_DEFAULT_IO_RANGE_LOWER;
+ res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* GPIOBASE */
+ pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS,
+ GPIO_BASE_SIZE, GPIO_BASE);
+
+ /* PMBASE */
+ pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
+
+ /* LPC Generic IO Decode range. */
+ pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
+ pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
+ pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
+ pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
+}
+
+static void pch_lpc_read_resources(device_t dev)
+{
+ global_nvs_t *gnvs;
+
+ /* Get the normal PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add non-standard MMIO resources. */
+ pch_lpc_add_mmio_resources(dev);
+
+ /* Add IO resources. */
+ pch_lpc_add_io_resources(dev);
+
+ /* Allocate ACPI NVS in CBMEM */
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ if (acpi_slp_type != 3 && gnvs)
+ memset(gnvs, 0, sizeof(global_nvs_t));
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &pch_lpc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .init = &lpc_init,
+ .scan_bus = &scan_static_bus,
+ .ops_pci = &broadwell_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCH_LPT_LP_SAMPLE,
+ PCH_LPT_LP_PREMIUM,
+ PCH_LPT_LP_MAINSTREAM,
+ PCH_LPT_LP_VALUE,
+ PCH_WPT_HSW_U_SAMPLE,
+ PCH_WPT_BDW_U_SAMPLE,
+ PCH_WPT_BDW_U_PREMIUM,
+ PCH_WPT_BDW_U_BASE,
+ PCH_WPT_BDW_Y_SAMPLE,
+ PCH_WPT_BDW_Y_PREMIUM,
+ PCH_WPT_BDW_Y_BASE,
+ PCH_WPT_BDW_H,
+ 0
+};
+
+static const struct pci_driver pch_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};