Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 2 | |
Elyes Haouas | 171ad51 | 2023-08-04 07:42:33 +0200 | [diff] [blame] | 3 | config SOC_INTEL_COOPERLAKE_SP |
| 4 | bool |
| 5 | select XEON_SP_COMMON_BASE |
| 6 | select PLATFORM_USES_FSP2_2 |
| 7 | select CACHE_MRC_SETTINGS |
| 8 | select NO_FSP_TEMP_RAM_EXIT |
Arthur Heymans | ffa61b0 | 2021-09-07 14:16:50 +0200 | [diff] [blame] | 9 | select HAVE_INTEL_FSP_REPO |
Elyes Haouas | 171ad51 | 2023-08-04 07:42:33 +0200 | [diff] [blame] | 10 | help |
| 11 | Intel Cooper Lake-SP support |
| 12 | |
| 13 | if SOC_INTEL_COOPERLAKE_SP |
Arthur Heymans | 86d195b | 2020-12-11 09:46:03 +0100 | [diff] [blame] | 14 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 15 | config FSP_HEADER_PATH |
Arthur Heymans | ffa61b0 | 2021-09-07 14:16:50 +0200 | [diff] [blame] | 16 | default "3rdparty/fsp/CedarIslandFspBinPkg/Include" |
| 17 | |
| 18 | config FSP_FD_PATH |
| 19 | default "3rdparty/fsp/CedarIslandFspBinPkg/Fsp.fd" |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 20 | |
| 21 | config MAX_SOCKET |
| 22 | int |
| 23 | default 2 |
| 24 | |
| 25 | config MAX_CPUS |
| 26 | int |
Andrey Petrov | e37d1f7 | 2020-04-20 21:11:51 -0700 | [diff] [blame] | 27 | default 255 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 28 | |
| 29 | config PCR_BASE_ADDRESS |
| 30 | hex |
| 31 | default 0xfd000000 |
| 32 | help |
| 33 | This option allows you to select MMIO Base Address of sideband bus. |
| 34 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 35 | config DCACHE_RAM_BASE |
| 36 | hex |
Arthur Heymans | b38d6bb | 2020-10-28 18:24:56 +0100 | [diff] [blame] | 37 | default 0xfe800000 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 38 | |
| 39 | config DCACHE_RAM_SIZE |
| 40 | hex |
Arthur Heymans | b38d6bb | 2020-10-28 18:24:56 +0100 | [diff] [blame] | 41 | default 0x1fff00 |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 42 | help |
| 43 | The size of the cache-as-ram region required during bootblock |
Arthur Heymans | b38d6bb | 2020-10-28 18:24:56 +0100 | [diff] [blame] | 44 | and/or romstage. FSP-T reserves the upper 0x100 for |
| 45 | FspReservedBuffer. |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 46 | |
| 47 | config DCACHE_BSP_STACK_SIZE |
| 48 | hex |
Arthur Heymans | 7a5c369 | 2021-01-04 12:49:39 +0100 | [diff] [blame] | 49 | default 0x40000 |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 50 | help |
| 51 | The amount of anticipated stack usage in CAR by bootblock and |
| 52 | other stages. It needs to include FSP-M stack requirement and |
Arthur Heymans | b38d6bb | 2020-10-28 18:24:56 +0100 | [diff] [blame] | 53 | CB romstage stack requirement. The integration documentation |
Arthur Heymans | 7a5c369 | 2021-01-04 12:49:39 +0100 | [diff] [blame] | 54 | says this needs to be 256KiB. |
| 55 | |
| 56 | config FSP_M_RC_HEAP_SIZE |
| 57 | hex |
| 58 | default 0x130000 |
| 59 | help |
| 60 | On xeon_sp/cpx FSP-M has two separate heap managers, one regular |
| 61 | whose size and base are controllable via the StackBase and |
| 62 | StackSize UPDs and a 'rc' heap manager that is statically |
| 63 | allocated at 0xfe800000 (the CAR base) and consumes about 0x130000 |
| 64 | bytes of memory. |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 65 | |
| 66 | config CPU_MICROCODE_CBFS_LOC |
| 67 | hex |
| 68 | default 0xfff0fdc0 |
| 69 | |
| 70 | config CPU_MICROCODE_CBFS_LEN |
| 71 | hex |
| 72 | default 0x7C00 |
| 73 | |
Patrick Georgi | acbc491 | 2023-11-06 17:22:34 +0000 | [diff] [blame] | 74 | config HEAP_SIZE |
| 75 | hex |
| 76 | default 0x80000 |
| 77 | |
Jonathan Zhang | 4337a9a | 2020-07-31 17:35:25 -0700 | [diff] [blame] | 78 | config STACK_SIZE |
| 79 | hex |
| 80 | default 0x4000 |
| 81 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 82 | config FSP_TEMP_RAM_SIZE |
| 83 | hex |
| 84 | depends on FSP_USES_CB_STACK |
Arthur Heymans | b38d6bb | 2020-10-28 18:24:56 +0100 | [diff] [blame] | 85 | default 0x40000 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 86 | help |
| 87 | The amount of anticipated heap usage in CAR by FSP. |
| 88 | Refer to Platform FSP integration guide document to know |
Arthur Heymans | b38d6bb | 2020-10-28 18:24:56 +0100 | [diff] [blame] | 89 | the exact FSP requirement for Heap setup. The FSP integration |
| 90 | documentation says this needs to be at least 128KiB, but practice |
| 91 | show this needs to be 256KiB or more. |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 92 | |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 93 | config IED_REGION_SIZE |
| 94 | hex |
| 95 | default 0x400000 |
| 96 | |
Johnny Lin | c05aa26 | 2021-06-22 11:35:41 +0800 | [diff] [blame] | 97 | config IFD_CHIPSET |
| 98 | string |
| 99 | default "lbg" |
| 100 | |
Andrey Petrov | cf270f0 | 2020-04-30 13:36:38 -0700 | [diff] [blame] | 101 | config SOC_INTEL_COMMON_BLOCK_P2SB |
| 102 | def_bool y |
| 103 | |
Jingle Hsu | a41b12c | 2020-08-11 20:48:45 +0800 | [diff] [blame] | 104 | config CPU_BCLK_MHZ |
| 105 | int |
| 106 | default 100 |
| 107 | |
Jonathan Zhang | decf7dc | 2020-07-27 15:26:30 -0700 | [diff] [blame] | 108 | # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel |
| 109 | # Default value is set to one socket, full config. |
| 110 | config DIMM_MAX |
Jonathan Zhang | decf7dc | 2020-07-27 15:26:30 -0700 | [diff] [blame] | 111 | default 12 |
| 112 | |
| 113 | # DDR4 |
| 114 | config DIMM_SPD_SIZE |
Jonathan Zhang | decf7dc | 2020-07-27 15:26:30 -0700 | [diff] [blame] | 115 | default 512 |
| 116 | |
Christian Walter | 106def9 | 2022-06-29 18:23:51 +0200 | [diff] [blame] | 117 | config XEON_SP_HAVE_IIO_IOAPIC |
| 118 | bool |
| 119 | default y |
| 120 | |
Arthur Heymans | 9059a89 | 2020-10-23 11:08:41 +0200 | [diff] [blame] | 121 | if INTEL_TXT |
| 122 | |
| 123 | config INTEL_TXT_SINIT_SIZE |
| 124 | hex |
| 125 | default 0x50000 |
| 126 | help |
| 127 | According to document number 572782 this needs to be 256KiB |
| 128 | for the SINIT module and 64KiB for SINIT data. |
| 129 | |
| 130 | config INTEL_TXT_HEAP_SIZE |
| 131 | hex |
| 132 | default 0xf0000 |
| 133 | help |
| 134 | This must be 960KiB according to 572782. |
| 135 | |
| 136 | endif # INTEL_TXT |
| 137 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 138 | endif |