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Subrata Banik91e89c52019-11-01 18:30:01 +05301config SOC_INTEL_TIGERLAKE
2 bool
3 help
4 Intel Tigerlake support
5
Aamir Bohraa23e0c92020-03-25 15:31:12 +05306if SOC_INTEL_TIGERLAKE
Subrata Banik91e89c52019-11-01 18:30:01 +05307
8config CPU_SPECIFIC_OPTIONS
9 def_bool y
10 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Angel Ponsa32df262020-09-25 10:20:11 +020011 select ARCH_ALL_STAGES_X86_32
Subrata Banik91e89c52019-11-01 18:30:01 +053012 select BOOT_DEVICE_SUPPORTS_WRITES
Subrata Banik91e89c52019-11-01 18:30:01 +053013 select CACHE_MRC_SETTINGS
Alex Levinf3668fc2020-06-11 20:09:45 -070014 select CPU_INTEL_COMMON
Subrata Banik91e89c52019-11-01 18:30:01 +053015 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +020016 select CPU_SUPPORTS_PM_TIMER_EMULATION
Duncan Laurie2e9315c2020-10-27 10:29:16 -070017 select DRIVERS_USB_ACPI
Furquan Shaikhba75c4c2020-11-22 15:45:54 -080018 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
Karthikeyan Ramasubramanian6abee842020-06-16 23:29:28 -060019 select FSP_COMPRESS_FSP_S_LZ4
Subrata Banik91e89c52019-11-01 18:30:01 +053020 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053021 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Subrata Banik91e89c52019-11-01 18:30:01 +053022 select GENERIC_GPIO_LIB
23 select HAVE_FSP_GOP
24 select INTEL_DESCRIPTOR_MODE_CAPABLE
25 select HAVE_SMI_HANDLER
26 select IDT_IN_EVERY_STAGE
Shreesh Chhabbi87c7ec72020-12-03 14:07:15 -080027 select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
Shreesh Chhabbi860c6842020-12-03 15:06:20 -080028 select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
Shreesh Chhabbi42b1d3f2020-11-05 12:06:29 -080029 select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
Subrata Banik91e89c52019-11-01 18:30:01 +053030 select INTEL_GMA_ACPI
31 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
32 select IOAPIC
33 select MRC_SETTINGS_PROTECT
34 select PARALLEL_MP
35 select PARALLEL_MP_AP_WORK
36 select MICROCODE_BLOB_UNDISCLOSED
Subrata Banikb622d4b2020-05-26 18:33:22 +053037 select PLATFORM_USES_FSP2_2
Jonathan Zhang01e38552020-06-17 16:03:18 -070038 select FSP_PEIM_TO_PEIM_INTERFACE
Subrata Banik91e89c52019-11-01 18:30:01 +053039 select REG_SCRIPT
Subrata Banik91e89c52019-11-01 18:30:01 +053040 select PMC_GLOBAL_RESET_ENABLE_LOCK
Subrata Banik0359d9d2020-09-28 18:43:47 +053041 select PMC_LOW_POWER_MODE_PROGRAM
Subrata Banik91e89c52019-11-01 18:30:01 +053042 select SOC_INTEL_COMMON
43 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
44 select SOC_INTEL_COMMON_BLOCK
45 select SOC_INTEL_COMMON_BLOCK_ACPI
Michael Niewöhner8a6c34e2021-01-01 21:26:42 +010046 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
Subrata Banik21974ab2020-10-31 21:40:43 +053047 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banik91e89c52019-11-01 18:30:01 +053048 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Furquan Shaikh23e88132020-10-08 23:44:20 -070049 select SOC_INTEL_COMMON_BLOCK_CNVI
Subrata Banik91e89c52019-11-01 18:30:01 +053050 select SOC_INTEL_COMMON_BLOCK_CPU
51 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Tim Wawrzynczakc5316ec2020-05-29 15:20:56 -060052 select SOC_INTEL_COMMON_BLOCK_DTT
Nick Vaccaroef8258a2019-12-09 22:11:33 -080053 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Duncan Laurie7d971362020-11-05 10:09:58 -080054 select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
Subrata Banik91e89c52019-11-01 18:30:01 +053055 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
56 select SOC_INTEL_COMMON_BLOCK_HDA
Duncan Lauriee997d852020-10-10 00:18:08 +000057 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
Subrata Banik91e89c52019-11-01 18:30:01 +053058 select SOC_INTEL_COMMON_BLOCK_SA
59 select SOC_INTEL_COMMON_BLOCK_SMM
60 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Duncan Laurie6f58b992020-08-28 19:44:42 +000061 select SOC_INTEL_COMMON_BLOCK_USB4
62 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
Duncan Laurie2e9315c2020-10-27 10:29:16 -070063 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
Karthikeyan Ramasubramanianfa9e8f92020-11-04 22:22:46 -070064 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +053065 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banik91e89c52019-11-01 18:30:01 +053066 select SOC_INTEL_COMMON_PCH_BASE
67 select SOC_INTEL_COMMON_RESET
Sumeet R Pawnikard2132462020-05-15 15:55:37 +053068 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Subrata Banik91e89c52019-11-01 18:30:01 +053069 select SSE2
70 select SUPPORT_CPU_UCODE_IN_CBFS
71 select TSC_MONOTONIC_TIMER
72 select UDELAY_TSC
73 select UDK_2017_BINDING
74 select DISPLAY_FSP_VERSION_INFO
75 select HECI_DISABLE_USING_SMM
76
77config DCACHE_RAM_BASE
78 default 0xfef00000
79
80config DCACHE_RAM_SIZE
Maulik V Vaghelae9b1e0f2019-12-16 16:39:53 +053081 default 0x80000
Subrata Banik91e89c52019-11-01 18:30:01 +053082 help
83 The size of the cache-as-ram region required during bootblock
84 and/or romstage.
85
86config DCACHE_BSP_STACK_SIZE
87 hex
Aamir Bohra555c9b62020-03-23 10:13:10 +053088 default 0x40400
Subrata Banik91e89c52019-11-01 18:30:01 +053089 help
90 The amount of anticipated stack usage in CAR by bootblock and
91 other stages. In the case of FSP_USES_CB_STACK default value will be
Aamir Bohra555c9b62020-03-23 10:13:10 +053092 sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
93 (~1KiB).
Subrata Banik91e89c52019-11-01 18:30:01 +053094
95config FSP_TEMP_RAM_SIZE
96 hex
Maulik V Vaghelae9b1e0f2019-12-16 16:39:53 +053097 default 0x20000
Subrata Banik91e89c52019-11-01 18:30:01 +053098 help
99 The amount of anticipated heap usage in CAR by FSP.
100 Refer to Platform FSP integration guide document to know
101 the exact FSP requirement for Heap setup.
102
Duncan Lauriea5bb31f2020-07-29 16:31:18 -0700103config CHIPSET_DEVICETREE
104 string
105 default "soc/intel/tigerlake/chipset.cb"
106
Furquan Shaikhba75c4c2020-11-22 15:45:54 -0800107config EXT_BIOS_WIN_BASE
108 default 0xf8000000
109
110config EXT_BIOS_WIN_SIZE
111 default 0x2000000
112
Subrata Banik91e89c52019-11-01 18:30:01 +0530113config IFD_CHIPSET
114 string
Aamir Bohra555c9b62020-03-23 10:13:10 +0530115 default "tgl"
Subrata Banik91e89c52019-11-01 18:30:01 +0530116
117config IED_REGION_SIZE
118 hex
119 default 0x400000
120
121config HEAP_SIZE
122 hex
Duncan Laurieaab226c2020-06-08 17:36:21 -0700123 default 0x10000
Subrata Banik91e89c52019-11-01 18:30:01 +0530124
125config MAX_ROOT_PORTS
126 int
Aamir Bohra555c9b62020-03-23 10:13:10 +0530127 default 12
Subrata Banik91e89c52019-11-01 18:30:01 +0530128
Ravi Sarawadi2fd49722019-12-16 23:41:36 -0800129config MAX_PCIE_CLOCKS
130 int
Aamir Bohra555c9b62020-03-23 10:13:10 +0530131 default 7
Ravi Sarawadi2fd49722019-12-16 23:41:36 -0800132
Subrata Banik91e89c52019-11-01 18:30:01 +0530133config SMM_TSEG_SIZE
134 hex
135 default 0x800000
136
137config SMM_RESERVED_SIZE
138 hex
139 default 0x200000
140
141config PCR_BASE_ADDRESS
142 hex
143 default 0xfd000000
144 help
145 This option allows you to select MMIO Base Address of sideband bus.
146
147config MMCONF_BASE_ADDRESS
148 hex
149 default 0xc0000000
150
151config CPU_BCLK_MHZ
152 int
153 default 100
154
155config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
156 int
157 default 120
158
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200159config CPU_XTAL_HZ
160 default 38400000
161
Subrata Banik91e89c52019-11-01 18:30:01 +0530162config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
163 int
164 default 133
165
166config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
167 int
Aamir Bohra555c9b62020-03-23 10:13:10 +0530168 default 4
Subrata Banik91e89c52019-11-01 18:30:01 +0530169
170config SOC_INTEL_I2C_DEV_MAX
171 int
172 default 6
173
174config SOC_INTEL_UART_DEV_MAX
175 int
176 default 3
177
178config CONSOLE_UART_BASE_ADDRESS
179 hex
Bora Guvendikc3c3e452020-11-13 21:35:19 -0800180 default 0xfe03e000
Subrata Banik91e89c52019-11-01 18:30:01 +0530181 depends on INTEL_LPSS_UART_FOR_CONSOLE
182
183# Clock divider parameters for 115200 baud rate
Ravi Sarawadi38387012019-12-19 15:04:58 -0800184# Baudrate = (UART source clcok * M) /(N *16)
185# TGL UART source clock: 120MHz
Subrata Banik91e89c52019-11-01 18:30:01 +0530186config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
187 hex
Aamir Bohra555c9b62020-03-23 10:13:10 +0530188 default 0x25a
Subrata Banik91e89c52019-11-01 18:30:01 +0530189
190config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
191 hex
Aamir Bohra555c9b62020-03-23 10:13:10 +0530192 default 0x7fff
Subrata Banik91e89c52019-11-01 18:30:01 +0530193
194config CHROMEOS
195 select CHROMEOS_RAMOOPS_DYNAMIC
196
Jes Klinkee046b712020-08-19 14:01:30 -0700197# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
198# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses.
199config TPM_CR50
200 select CR50_USE_LONG_INTERRUPT_PULSES
201
Srinidhi N Kaushik74c16d02020-11-04 11:29:33 -0800202config VBT_DATA_SIZE_KB
203 int
204 default 9
205
Subrata Banik91e89c52019-11-01 18:30:01 +0530206config VBOOT
207 select VBOOT_SEPARATE_VERSTAGE
208 select VBOOT_MUST_REQUEST_DISPLAY
Subrata Banik91e89c52019-11-01 18:30:01 +0530209 select VBOOT_STARTS_IN_BOOTBLOCK
210 select VBOOT_VBNV_CMOS
211 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
212
213config C_ENV_BOOTBLOCK_SIZE
214 hex
215 default 0xC000
216
217config CBFS_SIZE
218 hex
219 default 0x200000
220
Subrata Banik91e89c52019-11-01 18:30:01 +0530221config FSP_HEADER_PATH
Aamir Bohra555c9b62020-03-23 10:13:10 +0530222 default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/"
Subrata Banik91e89c52019-11-01 18:30:01 +0530223
224config FSP_FD_PATH
Aamir Bohra555c9b62020-03-23 10:13:10 +0530225 default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd"
Subrata Banik91e89c52019-11-01 18:30:01 +0530226
Subrata Banik56626cf2020-02-27 19:39:22 +0530227config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
228 int "Debug Consent for TGL"
229 # USB DBC is more common for developers so make this default to 3 if
230 # SOC_INTEL_DEBUG_CONSENT=y
231 default 3 if SOC_INTEL_DEBUG_CONSENT
232 default 0
233 help
234 This is to control debug interface on SOC.
235 Setting non-zero value will allow to use DBC or DCI to debug SOC.
236 PlatformDebugConsent in FspmUpd.h has the details.
237
238 Desired platform debug type are
239 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
240 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
241 6:Enable (2-wire DCI OOB), 7:Manual
Subrata Banikebf1daa2020-05-19 12:32:41 +0530242
243config PRERAM_CBMEM_CONSOLE_SIZE
244 hex
Anil Kumar033038f2020-09-08 16:18:45 -0700245 default 0x2000
Brandon Breitenstein99b38a92019-12-19 23:12:58 -0800246
247config EARLY_TCSS_DISPLAY
248 bool "Enable early TCSS display"
249 depends on RUN_FSP_GOP
250 help
251 Enable displays to be detected over Type-C ports during boot.
252
Subrata Banik91e89c52019-11-01 18:30:01 +0530253endif