Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 4 | #include <acpi/acpi_gnvs.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpigen.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 6 | #include <console/console.h> |
Felix Singer | 6c3a89c | 2020-07-26 09:26:52 +0200 | [diff] [blame] | 7 | #include <device/device.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 9 | #include <arch/smp/mpspec.h> |
Elyes HAOUAS | cd4fe0f | 2019-03-29 17:12:15 +0100 | [diff] [blame] | 10 | #include <assert.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 12 | #include <gpio.h> |
| 13 | #include <intelblocks/acpi.h> |
| 14 | #include <intelblocks/pmclib.h> |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 15 | #include <intelblocks/sgx.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 16 | #include <intelblocks/p2sb.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 17 | #include <soc/iomap.h> |
| 18 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 19 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 20 | #include <soc/pci_devs.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 21 | #include <soc/systemagent.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 22 | |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 23 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 24 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 25 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 26 | { \ |
| 27 | .space_id = address_space, \ |
| 28 | .bit_width = width, \ |
| 29 | .bit_offset = offset, \ |
| 30 | .addrl = address, \ |
| 31 | } |
| 32 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 33 | static acpi_cstate_t cstate_map[] = { |
| 34 | { |
| 35 | /* C1 */ |
| 36 | .ctype = 1, /* ACPI C1 */ |
| 37 | .latency = 1, |
| 38 | .power = 1000, |
| 39 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 40 | }, |
| 41 | { |
| 42 | .ctype = 2, /* ACPI C2 */ |
| 43 | .latency = 50, |
| 44 | .power = 10, |
| 45 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 46 | }, |
| 47 | { |
| 48 | .ctype = 3, /* ACPI C3 */ |
| 49 | .latency = 150, |
| 50 | .power = 10, |
| 51 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 52 | } |
| 53 | }; |
| 54 | |
| 55 | uint32_t soc_read_sci_irq_select(void) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 56 | { |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 57 | return read32p(soc_read_pmc_base() + IRQ_REG); |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 58 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 59 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 60 | void soc_write_sci_irq_select(uint32_t scis) |
| 61 | { |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 62 | write32p(soc_read_pmc_base() + IRQ_REG, scis); |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 63 | } |
| 64 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 65 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 66 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 67 | *entries = ARRAY_SIZE(cstate_map); |
| 68 | return cstate_map; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 69 | } |
| 70 | |
Kyösti Mälkki | c2b0a4f | 2020-06-28 22:39:59 +0300 | [diff] [blame] | 71 | void soc_fill_gnvs(struct global_nvs *gnvs) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 72 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 73 | struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 74 | cfg = config_of_soc(); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 75 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 76 | /* Enable DPTF based on mainboard configuration */ |
| 77 | gnvs->dpte = cfg->dptf_enable; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 78 | |
| 79 | /* Assign address of PERST_0 if GPIO is defined in devicetree */ |
| 80 | if (cfg->prt0_gpio != GPIO_PRT0_UDEF) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 81 | gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio); |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 82 | |
Venkateswarlu Vinjamuri | 99ce8a9 | 2017-03-22 18:24:52 -0700 | [diff] [blame] | 83 | /* Get sdcard cd GPIO portid if GPIO is defined in devicetree. |
| 84 | * Get offset of sdcard cd pin. |
| 85 | */ |
| 86 | if (cfg->sdcard_cd_gpio) { |
| 87 | gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio); |
| 88 | gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); |
| 89 | } |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 90 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 91 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 92 | sgx_fill_gnvs(gnvs); |
Subrata Banik | b6df6b0 | 2020-01-03 15:29:02 +0530 | [diff] [blame] | 93 | |
| 94 | /* Fill in Above 4GB MMIO resource */ |
| 95 | sa_fill_gnvs(gnvs); |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 96 | } |
| 97 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 98 | int soc_madt_sci_irq_polarity(int sci) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 99 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 100 | return MP_IRQ_POLARITY_LOW; |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 101 | } |
| 102 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 103 | void soc_fill_fadt(acpi_fadt_t *fadt) |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 104 | { |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 105 | const struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 106 | cfg = config_of_soc(); |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 107 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 108 | fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; |
| 109 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 110 | fadt->pm_tmr_len = 4; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 111 | |
| 112 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 113 | |
Elyes HAOUAS | 04071f4 | 2020-07-20 17:05:24 +0200 | [diff] [blame] | 114 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 115 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 116 | fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 117 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 118 | |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 119 | if (cfg->lpss_s0ix_enable) |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 120 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 121 | } |
| 122 | |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 123 | static unsigned long soc_fill_dmar(unsigned long current) |
| 124 | { |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 125 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 126 | uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; |
| 127 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 128 | bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; |
| 129 | unsigned long tmp; |
| 130 | |
| 131 | /* IGD has to be enabled, GFXVTBAR set and enabled. */ |
Subrata Banik | 54a3417 | 2021-06-09 03:54:58 +0530 | [diff] [blame] | 132 | const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten; |
Angel Pons | c05a3f8 | 2020-08-03 12:14:20 +0200 | [diff] [blame] | 133 | |
| 134 | /* First, add DRHD entries */ |
| 135 | if (emit_igd) { |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 136 | tmp = current; |
| 137 | |
| 138 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 139 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 140 | acpi_dmar_drhd_fixup(tmp, current); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | /* DEFVTBAR has to be set and enabled. */ |
| 144 | if (defvtbar && defvten) { |
| 145 | tmp = current; |
Arthur Heymans | 054026c | 2020-11-12 21:09:56 +0100 | [diff] [blame] | 146 | union p2sb_bdf ibdf = p2sb_get_ioapic_bdf(); |
Arthur Heymans | 281868e | 2020-11-12 21:02:11 +0100 | [diff] [blame] | 147 | union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 148 | p2sb_hide(); |
| 149 | |
| 150 | current += acpi_create_dmar_drhd(current, |
| 151 | DRHD_INCLUDE_PCI_ALL, 0, defvtbar); |
| 152 | current += acpi_create_dmar_ds_ioapic(current, |
Arthur Heymans | 054026c | 2020-11-12 21:09:56 +0100 | [diff] [blame] | 153 | 2, ibdf.bus, ibdf.dev, ibdf.fn); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 154 | current += acpi_create_dmar_ds_msi_hpet(current, |
Arthur Heymans | 281868e | 2020-11-12 21:02:11 +0100 | [diff] [blame] | 155 | 0, hbdf.bus, hbdf.dev, hbdf.fn); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 156 | acpi_dmar_drhd_fixup(tmp, current); |
| 157 | } |
| 158 | |
Angel Pons | c05a3f8 | 2020-08-03 12:14:20 +0200 | [diff] [blame] | 159 | /* Then, add RMRR entries after all DRHD entries */ |
| 160 | if (emit_igd) { |
| 161 | tmp = current; |
| 162 | current += acpi_create_dmar_rmrr(current, 0, |
| 163 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 164 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 165 | acpi_dmar_rmrr_fixup(tmp, current); |
| 166 | } |
| 167 | |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 168 | return current; |
| 169 | } |
| 170 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 171 | unsigned long sa_write_acpi_tables(const struct device *const dev, |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 172 | unsigned long current, |
| 173 | struct acpi_rsdp *const rsdp) |
| 174 | { |
| 175 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 176 | |
| 177 | /* Create DMAR table only if virtualization is enabled. Due to some |
| 178 | * constraints on Apollo Lake SoC (some stepping affected), VTD could |
| 179 | * not be enabled together with IPU. Doing so will override and disable |
| 180 | * VTD while leaving CAPID0_A still reporting that VTD is available. |
| 181 | * As in this case FSP will lock VTD to disabled state, we need to make |
| 182 | * sure that DMAR table generation only happens when at least DEFVTBAR |
| 183 | * is enabled. Otherwise the DMAR header will be generated while the |
| 184 | * content of the table will be missing. |
| 185 | */ |
| 186 | |
| 187 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 188 | !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) |
| 189 | return current; |
| 190 | |
| 191 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 192 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); |
| 193 | current += dmar->header.length; |
| 194 | current = acpi_align_current(current); |
| 195 | acpi_add_table(rsdp, dmar); |
| 196 | current = acpi_align_current(current); |
| 197 | |
| 198 | return current; |
| 199 | } |
| 200 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 201 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 202 | { |
| 203 | /* Generate P-state tables */ |
| 204 | generate_p_state_entries(core_id, cores_per_package); |
| 205 | |
| 206 | /* Generate T-state tables */ |
| 207 | generate_t_state_entries(core_id, cores_per_package); |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 208 | } |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 209 | |
| 210 | static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) |
| 211 | { |
| 212 | /* |
| 213 | * Store (\_SB.GPC0 (addr), Local5) |
| 214 | * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in |
| 215 | * gpiolib.asl. |
| 216 | */ |
| 217 | acpigen_write_store(); |
| 218 | acpigen_emit_namestring("\\_SB.GPC0"); |
| 219 | acpigen_write_integer(addr); |
| 220 | acpigen_emit_byte(LOCAL5_OP); |
| 221 | } |
| 222 | |
| 223 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 224 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 225 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 226 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 227 | |
| 228 | acpigen_soc_get_dw0_in_local5(addr); |
| 229 | |
| 230 | /* If (And (Local5, mask)) */ |
| 231 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 232 | |
| 233 | /* Store (One, Local0) */ |
| 234 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 235 | |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 236 | /* Else */ |
| 237 | acpigen_write_else(); |
| 238 | |
| 239 | /* Store (Zero, Local0) */ |
| 240 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 241 | |
| 242 | acpigen_pop_len(); /* Else */ |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 248 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 249 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 250 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 251 | |
| 252 | acpigen_soc_get_dw0_in_local5(addr); |
| 253 | |
| 254 | if (val) { |
| 255 | /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ |
| 256 | acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); |
| 257 | } else { |
| 258 | /* Not (PAD_CFG0_TX_STATE, Local6) */ |
| 259 | acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); |
| 260 | |
| 261 | /* And (Local5, Local6, Local5) */ |
| 262 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * \_SB.SPC0 (addr, Local5) |
| 267 | * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in |
| 268 | * gpiolib.asl. |
| 269 | */ |
| 270 | acpigen_emit_namestring("\\_SB.SPC0"); |
| 271 | acpigen_write_integer(addr); |
| 272 | acpigen_emit_byte(LOCAL5_OP); |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 278 | { |
| 279 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); |
| 280 | } |
| 281 | |
| 282 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 283 | { |
| 284 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); |
| 285 | } |
| 286 | |
| 287 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 288 | { |
| 289 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 290 | } |
| 291 | |
| 292 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 293 | { |
| 294 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 295 | } |