Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 5 | * Copyright 2017 Siemens AG. |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 6 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <arch/acpi.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 20 | #include <arch/acpigen.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 21 | #include <arch/io.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 22 | #include <arch/ioapic.h> |
| 23 | #include <arch/smp/mpspec.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 24 | #include <cbmem.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 25 | #include <cpu/x86/smm.h> |
Aaron Durbin | 1ee6f0b | 2016-06-10 15:50:34 -0500 | [diff] [blame] | 26 | #include <cpu/cpu.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 27 | #include <gpio.h> |
| 28 | #include <intelblocks/acpi.h> |
| 29 | #include <intelblocks/pmclib.h> |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame^] | 30 | #include <intelblocks/sgx.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 31 | #include <soc/iomap.h> |
| 32 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 33 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 34 | #include <soc/pci_devs.h> |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 35 | #include <string.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 36 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 37 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 38 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 39 | { \ |
| 40 | .space_id = address_space, \ |
| 41 | .bit_width = width, \ |
| 42 | .bit_offset = offset, \ |
| 43 | .addrl = address, \ |
| 44 | } |
| 45 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 46 | static acpi_cstate_t cstate_map[] = { |
| 47 | { |
| 48 | /* C1 */ |
| 49 | .ctype = 1, /* ACPI C1 */ |
| 50 | .latency = 1, |
| 51 | .power = 1000, |
| 52 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 53 | }, |
| 54 | { |
| 55 | .ctype = 2, /* ACPI C2 */ |
| 56 | .latency = 50, |
| 57 | .power = 10, |
| 58 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 59 | }, |
| 60 | { |
| 61 | .ctype = 3, /* ACPI C3 */ |
| 62 | .latency = 150, |
| 63 | .power = 10, |
| 64 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 65 | } |
| 66 | }; |
| 67 | |
| 68 | uint32_t soc_read_sci_irq_select(void) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 69 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 70 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 71 | return read32((void *)pmc_bar + IRQ_REG); |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 72 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 73 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 74 | void soc_write_sci_irq_select(uint32_t scis) |
| 75 | { |
| 76 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 77 | write32((void *)pmc_bar + IRQ_REG, scis); |
| 78 | } |
| 79 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 80 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 81 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 82 | *entries = ARRAY_SIZE(cstate_map); |
| 83 | return cstate_map; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 84 | } |
| 85 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 86 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 87 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 88 | struct soc_intel_apollolake_config *cfg; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 89 | struct device *dev = SA_DEV_ROOT; |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 90 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 91 | /* Clear out GNVS. */ |
| 92 | memset(gnvs, 0, sizeof(*gnvs)); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 93 | |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 94 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 95 | gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 96 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 97 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 98 | /* Initialize Verified Boot data */ |
| 99 | chromeos_init_vboot(&gnvs->chromeos); |
| 100 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 101 | } |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 102 | |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 103 | /* Set unknown wake source */ |
| 104 | gnvs->pm1i = ~0ULL; |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 105 | |
Duncan Laurie | 1d359b5 | 2016-09-21 18:30:44 -0700 | [diff] [blame] | 106 | /* CPU core count */ |
| 107 | gnvs->pcnt = dev_count_cpu(); |
| 108 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 109 | if (!dev || !dev->chip_info) { |
| 110 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 111 | return; |
| 112 | } |
| 113 | cfg = dev->chip_info; |
| 114 | |
| 115 | /* Enable DPTF based on mainboard configuration */ |
| 116 | gnvs->dpte = cfg->dptf_enable; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 117 | |
| 118 | /* Assign address of PERST_0 if GPIO is defined in devicetree */ |
| 119 | if (cfg->prt0_gpio != GPIO_PRT0_UDEF) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 120 | gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio); |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 121 | |
Venkateswarlu Vinjamuri | 99ce8a9 | 2017-03-22 18:24:52 -0700 | [diff] [blame] | 122 | /* Get sdcard cd GPIO portid if GPIO is defined in devicetree. |
| 123 | * Get offset of sdcard cd pin. |
| 124 | */ |
| 125 | if (cfg->sdcard_cd_gpio) { |
| 126 | gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio); |
| 127 | gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); |
| 128 | } |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame^] | 129 | |
| 130 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) |
| 131 | sgx_fill_gnvs(gnvs); |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 132 | } |
| 133 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 134 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 135 | const struct chipset_power_state *ps) |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 136 | { |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 137 | /* |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 138 | * WAK_STS bit is set when the system is in one of the sleep states |
| 139 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 140 | * this bit, the PMC will transition the system to the ON state and |
| 141 | * can only be set by hardware and can only be cleared by writing a one |
| 142 | * to this bit position. |
| 143 | */ |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 144 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 145 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 146 | return generic_pm1_en; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 147 | } |
| 148 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 149 | int soc_madt_sci_irq_polarity(int sci) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 150 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 151 | return MP_IRQ_POLARITY_LOW; |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 152 | } |
| 153 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 154 | void soc_fill_fadt(acpi_fadt_t *fadt) |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 155 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 156 | fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; |
| 157 | |
| 158 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 159 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 160 | |
| 161 | fadt->pm_tmr_len = 4; |
| 162 | fadt->duty_width = 3; |
| 163 | |
| 164 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 165 | |
| 166 | fadt->x_pm_tmr_blk.space_id = 1; |
| 167 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 168 | fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; |
| 169 | } |
| 170 | |
| 171 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 172 | { |
| 173 | /* Generate P-state tables */ |
| 174 | generate_p_state_entries(core_id, cores_per_package); |
| 175 | |
| 176 | /* Generate T-state tables */ |
| 177 | generate_t_state_entries(core_id, cores_per_package); |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 178 | } |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 179 | |
| 180 | static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) |
| 181 | { |
| 182 | /* |
| 183 | * Store (\_SB.GPC0 (addr), Local5) |
| 184 | * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in |
| 185 | * gpiolib.asl. |
| 186 | */ |
| 187 | acpigen_write_store(); |
| 188 | acpigen_emit_namestring("\\_SB.GPC0"); |
| 189 | acpigen_write_integer(addr); |
| 190 | acpigen_emit_byte(LOCAL5_OP); |
| 191 | } |
| 192 | |
| 193 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 194 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 195 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 196 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 197 | |
| 198 | acpigen_soc_get_dw0_in_local5(addr); |
| 199 | |
| 200 | /* If (And (Local5, mask)) */ |
| 201 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 202 | |
| 203 | /* Store (One, Local0) */ |
| 204 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 205 | |
| 206 | acpigen_pop_len(); /* If */ |
| 207 | |
| 208 | /* Else */ |
| 209 | acpigen_write_else(); |
| 210 | |
| 211 | /* Store (Zero, Local0) */ |
| 212 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 213 | |
| 214 | acpigen_pop_len(); /* Else */ |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 220 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 221 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 222 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 223 | |
| 224 | acpigen_soc_get_dw0_in_local5(addr); |
| 225 | |
| 226 | if (val) { |
| 227 | /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ |
| 228 | acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); |
| 229 | } else { |
| 230 | /* Not (PAD_CFG0_TX_STATE, Local6) */ |
| 231 | acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); |
| 232 | |
| 233 | /* And (Local5, Local6, Local5) */ |
| 234 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 235 | } |
| 236 | |
| 237 | /* |
| 238 | * \_SB.SPC0 (addr, Local5) |
| 239 | * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in |
| 240 | * gpiolib.asl. |
| 241 | */ |
| 242 | acpigen_emit_namestring("\\_SB.SPC0"); |
| 243 | acpigen_write_integer(addr); |
| 244 | acpigen_emit_byte(LOCAL5_OP); |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 250 | { |
| 251 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); |
| 252 | } |
| 253 | |
| 254 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 255 | { |
| 256 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); |
| 257 | } |
| 258 | |
| 259 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 260 | { |
| 261 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 262 | } |
| 263 | |
| 264 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 265 | { |
| 266 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 267 | } |