Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 5 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <arch/acpi.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 19 | #include <arch/acpigen.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 20 | #include <arch/ioapic.h> |
| 21 | #include <arch/smp/mpspec.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 23 | #include <cpu/x86/smm.h> |
Aaron Durbin | 1ee6f0b | 2016-06-10 15:50:34 -0500 | [diff] [blame] | 24 | #include <cpu/cpu.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 25 | #include <soc/acpi.h> |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 26 | #include <soc/intel/common/acpi.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 27 | #include <soc/iomap.h> |
| 28 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 29 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 30 | #include <soc/pci_devs.h> |
| 31 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 32 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 33 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 34 | { \ |
| 35 | .space_id = address_space, \ |
| 36 | .bit_width = width, \ |
| 37 | .bit_offset = offset, \ |
| 38 | .addrl = address, \ |
| 39 | } |
| 40 | |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 41 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 42 | { |
Lance Zhao | 2c34e31 | 2015-11-16 18:13:23 -0800 | [diff] [blame] | 43 | /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ |
| 44 | current += acpi_create_mcfg_mmconfig((void *) current, |
| 45 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, |
| 46 | 255); |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 47 | return current; |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 48 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 49 | |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 50 | static int acpi_sci_irq(void) |
| 51 | { |
| 52 | int sci_irq = 9; |
| 53 | return sci_irq; |
| 54 | } |
| 55 | |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 56 | static unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 57 | { |
| 58 | int sci = acpi_sci_irq(); |
| 59 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; |
| 60 | |
| 61 | /* INT_SRC_OVR */ |
| 62 | current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); |
| 63 | |
| 64 | /* SCI */ |
| 65 | current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); |
| 66 | |
| 67 | return current; |
| 68 | } |
| 69 | |
| 70 | unsigned long acpi_fill_madt(unsigned long current) |
| 71 | { |
| 72 | /* Local APICs */ |
| 73 | current = acpi_create_madt_lapics(current); |
| 74 | |
| 75 | /* IOAPIC */ |
| 76 | current += acpi_create_madt_ioapic((void *) current, |
| 77 | 2, IO_APIC_ADDR, 0); |
| 78 | |
| 79 | return acpi_madt_irq_overrides(current); |
| 80 | } |
| 81 | |
Aaron Durbin | c3ee3f6 | 2016-05-11 10:35:49 -0500 | [diff] [blame] | 82 | void acpi_fill_fadt(acpi_fadt_t * fadt) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 83 | { |
| 84 | const uint16_t pmbase = ACPI_PMIO_BASE; |
| 85 | |
Aaron Durbin | c3ee3f6 | 2016-05-11 10:35:49 -0500 | [diff] [blame] | 86 | /* Use ACPI 5.0 revision. */ |
| 87 | fadt->header.revision = ACPI_FADT_REV_ACPI_5_0; |
| 88 | |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 89 | fadt->sci_int = acpi_sci_irq(); |
Hannah Williams | 6516422 | 2016-06-24 14:13:45 -0700 | [diff] [blame] | 90 | fadt->smi_cmd = APM_CNT; |
| 91 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 92 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 93 | |
| 94 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 95 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 96 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 97 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 98 | |
| 99 | fadt->pm1_evt_len = 4; |
| 100 | fadt->pm1_cnt_len = 2; |
| 101 | fadt->pm_tmr_len = 4; |
| 102 | /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ |
| 103 | fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| 104 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 105 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 106 | fadt->flush_size = 0x400; /* twice of cache size*/ |
| 107 | fadt->flush_stride = 0x10; /* Cache line width */ |
| 108 | fadt->duty_offset = 1; |
| 109 | fadt->duty_width = 3; |
| 110 | fadt->day_alrm = 0xd; |
| 111 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 112 | |
| 113 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 114 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 115 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | |
| 116 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 117 | |
| 118 | fadt->reset_reg.space_id = 1; |
| 119 | fadt->reset_reg.bit_width = 8; |
| 120 | fadt->reset_reg.addrl = 0xcf9; |
| 121 | fadt->reset_value = 6; |
| 122 | |
| 123 | fadt->x_pm1a_evt_blk.space_id = 1; |
| 124 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
| 125 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 126 | |
| 127 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 128 | |
| 129 | fadt->x_pm1a_cnt_blk.space_id = 1; |
| 130 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
| 131 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 132 | |
| 133 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 134 | |
| 135 | fadt->x_pm_tmr_blk.space_id = 1; |
| 136 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 137 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 138 | |
| 139 | fadt->x_gpe1_blk.space_id = 1; |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 140 | } |
Zhao, Lijian | 30461a9 | 2015-12-01 09:14:20 -0800 | [diff] [blame] | 141 | |
| 142 | unsigned long southbridge_write_acpi_tables(device_t device, |
| 143 | unsigned long current, |
| 144 | struct acpi_rsdp *rsdp) |
| 145 | { |
| 146 | return acpi_write_hpet(device, current, rsdp); |
| 147 | } |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 148 | |
| 149 | static void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 150 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 151 | struct soc_intel_apollolake_config *cfg; |
| 152 | struct device *dev = NB_DEV_ROOT; |
| 153 | |
| 154 | if (!dev || !dev->chip_info) { |
| 155 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 156 | return; |
| 157 | } |
| 158 | cfg = dev->chip_info; |
| 159 | |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 160 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
| 161 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 162 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 163 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 164 | /* Initialize Verified Boot data */ |
| 165 | chromeos_init_vboot(&gnvs->chromeos); |
| 166 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 167 | } |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 168 | |
| 169 | /* Enable DPTF based on mainboard configuration */ |
| 170 | gnvs->dpte = cfg->dptf_enable; |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame^] | 171 | |
| 172 | /* Set unknown wake source */ |
| 173 | gnvs->pm1i = ~0ULL; |
| 174 | } |
| 175 | |
| 176 | /* Save wake source information for calculating ACPI _SWS values */ |
| 177 | int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) |
| 178 | { |
| 179 | struct chipset_power_state *ps; |
| 180 | static uint32_t gpe0_sts[GPE0_REG_MAX]; |
| 181 | uint32_t pm1_en; |
| 182 | int i; |
| 183 | |
| 184 | ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 185 | if (ps == NULL) |
| 186 | return -1; |
| 187 | |
| 188 | /* |
| 189 | * PM1_EN to check the basic wake events which can happen through |
| 190 | * powerbtn or any other wake source like lidopen, key board press etc. |
| 191 | * WAK_STS bit is set when the system is in one of the sleep states |
| 192 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 193 | * this bit, the PMC will transition the system to the ON state and |
| 194 | * can only be set by hardware and can only be cleared by writing a one |
| 195 | * to this bit position. |
| 196 | */ |
| 197 | pm1_en = ps->pm1_en | WAK_STS | RTC_EN | PWRBTN_EN; |
| 198 | *pm1 = ps->pm1_sts & pm1_en; |
| 199 | |
| 200 | /* Mask off GPE0 status bits that are not enabled */ |
| 201 | *gpe0 = &gpe0_sts[0]; |
| 202 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 203 | gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; |
| 204 | |
| 205 | return GPE0_REG_MAX; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | void southbridge_inject_dsdt(device_t device) |
| 209 | { |
| 210 | struct global_nvs_t *gnvs; |
| 211 | |
| 212 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 213 | |
| 214 | if (gnvs) { |
| 215 | acpi_create_gnvs(gnvs); |
| 216 | acpi_save_gnvs((uintptr_t)gnvs); |
Aaron Durbin | 1ee6f0b | 2016-06-10 15:50:34 -0500 | [diff] [blame] | 217 | /* And tell SMI about it */ |
| 218 | smm_setup_structures(gnvs, NULL, NULL); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 219 | |
| 220 | /* Add it to DSDT. */ |
| 221 | acpigen_write_scope("\\"); |
| 222 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 223 | acpigen_pop_len(); |
| 224 | } |
| 225 | } |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 226 | static acpi_cstate_t cstate_map[] = { |
| 227 | { |
| 228 | /* C1 */ |
| 229 | .ctype = 1, /* ACPI C1 */ |
| 230 | .latency = 1, |
| 231 | .power = 1000, |
| 232 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 233 | }, |
| 234 | { |
| 235 | .ctype = 2, /* ACPI C2 */ |
| 236 | .latency = 50, |
| 237 | .power = 10, |
| 238 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 239 | }, |
| 240 | { |
| 241 | .ctype = 3, /* ACPI C3 */ |
| 242 | .latency = 150, |
| 243 | .power = 10, |
| 244 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 245 | } |
| 246 | }; |
| 247 | |
| 248 | acpi_cstate_t *soc_get_cstate_map(int *entries) |
| 249 | { |
| 250 | *entries = ARRAY_SIZE(cstate_map); |
| 251 | return cstate_map; |
| 252 | } |
| 253 | |
| 254 | uint16_t soc_get_acpi_base_address(void) |
| 255 | { |
| 256 | return ACPI_PMIO_BASE; |
| 257 | } |