Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame^] | 5 | * Copyright (C) 2017-2019 Siemens AG |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 6 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <arch/acpi.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 20 | #include <arch/acpigen.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 21 | #include <arch/io.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 22 | #include <arch/smp/mpspec.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame^] | 23 | #include <device/pci_ops.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 24 | #include <cbmem.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 25 | #include <cpu/x86/smm.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 26 | #include <gpio.h> |
| 27 | #include <intelblocks/acpi.h> |
| 28 | #include <intelblocks/pmclib.h> |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 29 | #include <intelblocks/sgx.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame^] | 30 | #include <intelblocks/p2sb.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 31 | #include <soc/iomap.h> |
| 32 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 33 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 34 | #include <soc/pci_devs.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame^] | 35 | #include <soc/systemagent.h> |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 36 | #include <string.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 37 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 38 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 39 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 40 | { \ |
| 41 | .space_id = address_space, \ |
| 42 | .bit_width = width, \ |
| 43 | .bit_offset = offset, \ |
| 44 | .addrl = address, \ |
| 45 | } |
| 46 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 47 | static acpi_cstate_t cstate_map[] = { |
| 48 | { |
| 49 | /* C1 */ |
| 50 | .ctype = 1, /* ACPI C1 */ |
| 51 | .latency = 1, |
| 52 | .power = 1000, |
| 53 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 54 | }, |
| 55 | { |
| 56 | .ctype = 2, /* ACPI C2 */ |
| 57 | .latency = 50, |
| 58 | .power = 10, |
| 59 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 60 | }, |
| 61 | { |
| 62 | .ctype = 3, /* ACPI C3 */ |
| 63 | .latency = 150, |
| 64 | .power = 10, |
| 65 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 66 | } |
| 67 | }; |
| 68 | |
| 69 | uint32_t soc_read_sci_irq_select(void) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 70 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 71 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 72 | return read32((void *)pmc_bar + IRQ_REG); |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 73 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 74 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 75 | void soc_write_sci_irq_select(uint32_t scis) |
| 76 | { |
| 77 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 78 | write32((void *)pmc_bar + IRQ_REG, scis); |
| 79 | } |
| 80 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 81 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 82 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 83 | *entries = ARRAY_SIZE(cstate_map); |
| 84 | return cstate_map; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 85 | } |
| 86 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 87 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 88 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 89 | struct soc_intel_apollolake_config *cfg; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 90 | struct device *dev = SA_DEV_ROOT; |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 91 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 92 | /* Clear out GNVS. */ |
| 93 | memset(gnvs, 0, sizeof(*gnvs)); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 94 | |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 95 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 96 | gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 97 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 98 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 99 | /* Initialize Verified Boot data */ |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 100 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 101 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 102 | } |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 103 | |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 104 | /* Set unknown wake source */ |
| 105 | gnvs->pm1i = ~0ULL; |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 106 | |
Duncan Laurie | 1d359b5 | 2016-09-21 18:30:44 -0700 | [diff] [blame] | 107 | /* CPU core count */ |
| 108 | gnvs->pcnt = dev_count_cpu(); |
| 109 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 110 | if (!dev || !dev->chip_info) { |
| 111 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 112 | return; |
| 113 | } |
| 114 | cfg = dev->chip_info; |
| 115 | |
| 116 | /* Enable DPTF based on mainboard configuration */ |
| 117 | gnvs->dpte = cfg->dptf_enable; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 118 | |
| 119 | /* Assign address of PERST_0 if GPIO is defined in devicetree */ |
| 120 | if (cfg->prt0_gpio != GPIO_PRT0_UDEF) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 121 | gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio); |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 122 | |
Venkateswarlu Vinjamuri | 99ce8a9 | 2017-03-22 18:24:52 -0700 | [diff] [blame] | 123 | /* Get sdcard cd GPIO portid if GPIO is defined in devicetree. |
| 124 | * Get offset of sdcard cd pin. |
| 125 | */ |
| 126 | if (cfg->sdcard_cd_gpio) { |
| 127 | gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio); |
| 128 | gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); |
| 129 | } |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 130 | |
| 131 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) |
| 132 | sgx_fill_gnvs(gnvs); |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 135 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 136 | const struct chipset_power_state *ps) |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 137 | { |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 138 | /* |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 139 | * WAK_STS bit is set when the system is in one of the sleep states |
| 140 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 141 | * this bit, the PMC will transition the system to the ON state and |
| 142 | * can only be set by hardware and can only be cleared by writing a one |
| 143 | * to this bit position. |
| 144 | */ |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 145 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 146 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 147 | return generic_pm1_en; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 148 | } |
| 149 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 150 | int soc_madt_sci_irq_polarity(int sci) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 151 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 152 | return MP_IRQ_POLARITY_LOW; |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 153 | } |
| 154 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 155 | void soc_fill_fadt(acpi_fadt_t *fadt) |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 156 | { |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 157 | const struct soc_intel_apollolake_config *cfg; |
| 158 | struct device *dev = SA_DEV_ROOT; |
| 159 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 160 | fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; |
| 161 | |
| 162 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 163 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 164 | |
| 165 | fadt->pm_tmr_len = 4; |
| 166 | fadt->duty_width = 3; |
| 167 | |
| 168 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 169 | |
| 170 | fadt->x_pm_tmr_blk.space_id = 1; |
| 171 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 172 | fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 173 | |
| 174 | if (!dev || !dev->chip_info) { |
| 175 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 176 | return; |
| 177 | } |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 178 | cfg = dev->chip_info; |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 179 | |
| 180 | if(cfg->lpss_s0ix_enable) |
| 181 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 182 | } |
| 183 | |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame^] | 184 | static unsigned long soc_fill_dmar(unsigned long current) |
| 185 | { |
| 186 | struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); |
| 187 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 188 | uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; |
| 189 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 190 | bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; |
| 191 | unsigned long tmp; |
| 192 | |
| 193 | /* IGD has to be enabled, GFXVTBAR set and enabled. */ |
| 194 | if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { |
| 195 | tmp = current; |
| 196 | |
| 197 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 198 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 199 | acpi_dmar_drhd_fixup(tmp, current); |
| 200 | |
| 201 | /* Add RMRR entry */ |
| 202 | tmp = current; |
| 203 | current += acpi_create_dmar_rmrr(current, 0, |
| 204 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 205 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 206 | acpi_dmar_rmrr_fixup(tmp, current); |
| 207 | } |
| 208 | |
| 209 | /* DEFVTBAR has to be set and enabled. */ |
| 210 | if (defvtbar && defvten) { |
| 211 | tmp = current; |
| 212 | /* |
| 213 | * P2SB may already be hidden. There's no clear rule, when. |
| 214 | * It is needed to get bus, device and function for IOAPIC and |
| 215 | * HPET device which is stored in P2SB device. So unhide it to |
| 216 | * get the info and hide it again when done. |
| 217 | */ |
| 218 | p2sb_unhide(); |
| 219 | struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); |
| 220 | uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); |
| 221 | uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); |
| 222 | p2sb_hide(); |
| 223 | |
| 224 | current += acpi_create_dmar_drhd(current, |
| 225 | DRHD_INCLUDE_PCI_ALL, 0, defvtbar); |
| 226 | current += acpi_create_dmar_ds_ioapic(current, |
| 227 | 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); |
| 228 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 229 | 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); |
| 230 | acpi_dmar_drhd_fixup(tmp, current); |
| 231 | } |
| 232 | |
| 233 | return current; |
| 234 | } |
| 235 | |
| 236 | unsigned long sa_write_acpi_tables(struct device *const dev, |
| 237 | unsigned long current, |
| 238 | struct acpi_rsdp *const rsdp) |
| 239 | { |
| 240 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 241 | |
| 242 | /* Create DMAR table only if virtualization is enabled. Due to some |
| 243 | * constraints on Apollo Lake SoC (some stepping affected), VTD could |
| 244 | * not be enabled together with IPU. Doing so will override and disable |
| 245 | * VTD while leaving CAPID0_A still reporting that VTD is available. |
| 246 | * As in this case FSP will lock VTD to disabled state, we need to make |
| 247 | * sure that DMAR table generation only happens when at least DEFVTBAR |
| 248 | * is enabled. Otherwise the DMAR header will be generated while the |
| 249 | * content of the table will be missing. |
| 250 | */ |
| 251 | |
| 252 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 253 | !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) |
| 254 | return current; |
| 255 | |
| 256 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 257 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); |
| 258 | current += dmar->header.length; |
| 259 | current = acpi_align_current(current); |
| 260 | acpi_add_table(rsdp, dmar); |
| 261 | current = acpi_align_current(current); |
| 262 | |
| 263 | return current; |
| 264 | } |
| 265 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 266 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 267 | { |
| 268 | /* Generate P-state tables */ |
| 269 | generate_p_state_entries(core_id, cores_per_package); |
| 270 | |
| 271 | /* Generate T-state tables */ |
| 272 | generate_t_state_entries(core_id, cores_per_package); |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 273 | } |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 274 | |
| 275 | static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) |
| 276 | { |
| 277 | /* |
| 278 | * Store (\_SB.GPC0 (addr), Local5) |
| 279 | * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in |
| 280 | * gpiolib.asl. |
| 281 | */ |
| 282 | acpigen_write_store(); |
| 283 | acpigen_emit_namestring("\\_SB.GPC0"); |
| 284 | acpigen_write_integer(addr); |
| 285 | acpigen_emit_byte(LOCAL5_OP); |
| 286 | } |
| 287 | |
| 288 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 289 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 290 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 291 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 292 | |
| 293 | acpigen_soc_get_dw0_in_local5(addr); |
| 294 | |
| 295 | /* If (And (Local5, mask)) */ |
| 296 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 297 | |
| 298 | /* Store (One, Local0) */ |
| 299 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 300 | |
| 301 | acpigen_pop_len(); /* If */ |
| 302 | |
| 303 | /* Else */ |
| 304 | acpigen_write_else(); |
| 305 | |
| 306 | /* Store (Zero, Local0) */ |
| 307 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 308 | |
| 309 | acpigen_pop_len(); /* Else */ |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 315 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 316 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 317 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 318 | |
| 319 | acpigen_soc_get_dw0_in_local5(addr); |
| 320 | |
| 321 | if (val) { |
| 322 | /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ |
| 323 | acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); |
| 324 | } else { |
| 325 | /* Not (PAD_CFG0_TX_STATE, Local6) */ |
| 326 | acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); |
| 327 | |
| 328 | /* And (Local5, Local6, Local5) */ |
| 329 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * \_SB.SPC0 (addr, Local5) |
| 334 | * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in |
| 335 | * gpiolib.asl. |
| 336 | */ |
| 337 | acpigen_emit_namestring("\\_SB.SPC0"); |
| 338 | acpigen_write_integer(addr); |
| 339 | acpigen_emit_byte(LOCAL5_OP); |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 345 | { |
| 346 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); |
| 347 | } |
| 348 | |
| 349 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 350 | { |
| 351 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); |
| 352 | } |
| 353 | |
| 354 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 355 | { |
| 356 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 357 | } |
| 358 | |
| 359 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 360 | { |
| 361 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 362 | } |