Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 5 | * Copyright (C) 2017-2019 Siemens AG |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 6 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <arch/acpi.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 20 | #include <arch/acpigen.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 21 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 22 | #include <device/mmio.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 23 | #include <arch/smp/mpspec.h> |
Elyes HAOUAS | cd4fe0f | 2019-03-29 17:12:15 +0100 | [diff] [blame] | 24 | #include <assert.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 25 | #include <device/pci_ops.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 26 | #include <cbmem.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 27 | #include <cpu/x86/smm.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 28 | #include <gpio.h> |
| 29 | #include <intelblocks/acpi.h> |
| 30 | #include <intelblocks/pmclib.h> |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 31 | #include <intelblocks/sgx.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 32 | #include <intelblocks/p2sb.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 33 | #include <soc/iomap.h> |
| 34 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 35 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 36 | #include <soc/pci_devs.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 37 | #include <soc/systemagent.h> |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 38 | #include <string.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 39 | |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 40 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 41 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 42 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 43 | { \ |
| 44 | .space_id = address_space, \ |
| 45 | .bit_width = width, \ |
| 46 | .bit_offset = offset, \ |
| 47 | .addrl = address, \ |
| 48 | } |
| 49 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 50 | static acpi_cstate_t cstate_map[] = { |
| 51 | { |
| 52 | /* C1 */ |
| 53 | .ctype = 1, /* ACPI C1 */ |
| 54 | .latency = 1, |
| 55 | .power = 1000, |
| 56 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 57 | }, |
| 58 | { |
| 59 | .ctype = 2, /* ACPI C2 */ |
| 60 | .latency = 50, |
| 61 | .power = 10, |
| 62 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 63 | }, |
| 64 | { |
| 65 | .ctype = 3, /* ACPI C3 */ |
| 66 | .latency = 150, |
| 67 | .power = 10, |
| 68 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 69 | } |
| 70 | }; |
| 71 | |
| 72 | uint32_t soc_read_sci_irq_select(void) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 73 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 74 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 75 | return read32((void *)pmc_bar + IRQ_REG); |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 76 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 77 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 78 | void soc_write_sci_irq_select(uint32_t scis) |
| 79 | { |
| 80 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 81 | write32((void *)pmc_bar + IRQ_REG, scis); |
| 82 | } |
| 83 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 84 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 85 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 86 | *entries = ARRAY_SIZE(cstate_map); |
| 87 | return cstate_map; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 88 | } |
| 89 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 90 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 91 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 92 | struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame^] | 93 | cfg = config_of_path(SA_DEVFN_ROOT); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 94 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 95 | /* Clear out GNVS. */ |
| 96 | memset(gnvs, 0, sizeof(*gnvs)); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 97 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 98 | if (CONFIG(CONSOLE_CBMEM)) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 99 | gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 100 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 101 | if (CONFIG(CHROMEOS)) { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 102 | /* Initialize Verified Boot data */ |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 103 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 104 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 105 | } |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 106 | |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 107 | /* Set unknown wake source */ |
| 108 | gnvs->pm1i = ~0ULL; |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 109 | |
Duncan Laurie | 1d359b5 | 2016-09-21 18:30:44 -0700 | [diff] [blame] | 110 | /* CPU core count */ |
| 111 | gnvs->pcnt = dev_count_cpu(); |
| 112 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 113 | /* Enable DPTF based on mainboard configuration */ |
| 114 | gnvs->dpte = cfg->dptf_enable; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 115 | |
| 116 | /* Assign address of PERST_0 if GPIO is defined in devicetree */ |
| 117 | if (cfg->prt0_gpio != GPIO_PRT0_UDEF) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 118 | gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio); |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 119 | |
Venkateswarlu Vinjamuri | 99ce8a9 | 2017-03-22 18:24:52 -0700 | [diff] [blame] | 120 | /* Get sdcard cd GPIO portid if GPIO is defined in devicetree. |
| 121 | * Get offset of sdcard cd pin. |
| 122 | */ |
| 123 | if (cfg->sdcard_cd_gpio) { |
| 124 | gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio); |
| 125 | gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); |
| 126 | } |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 127 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 128 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 129 | sgx_fill_gnvs(gnvs); |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 130 | } |
| 131 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 132 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 133 | const struct chipset_power_state *ps) |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 134 | { |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 135 | /* |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 136 | * WAK_STS bit is set when the system is in one of the sleep states |
| 137 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 138 | * this bit, the PMC will transition the system to the ON state and |
| 139 | * can only be set by hardware and can only be cleared by writing a one |
| 140 | * to this bit position. |
| 141 | */ |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 142 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 143 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 144 | return generic_pm1_en; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 145 | } |
| 146 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 147 | int soc_madt_sci_irq_polarity(int sci) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 148 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 149 | return MP_IRQ_POLARITY_LOW; |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 150 | } |
| 151 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 152 | void soc_fill_fadt(acpi_fadt_t *fadt) |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 153 | { |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 154 | const struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame^] | 155 | cfg = config_of_path(SA_DEVFN_ROOT); |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 156 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 157 | fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; |
| 158 | |
| 159 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 160 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 161 | |
| 162 | fadt->pm_tmr_len = 4; |
| 163 | fadt->duty_width = 3; |
| 164 | |
| 165 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 166 | |
| 167 | fadt->x_pm_tmr_blk.space_id = 1; |
| 168 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 169 | fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 170 | |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 171 | |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame^] | 172 | if (cfg->lpss_s0ix_enable) |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 173 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 174 | } |
| 175 | |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 176 | static unsigned long soc_fill_dmar(unsigned long current) |
| 177 | { |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 178 | struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 179 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 180 | uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; |
| 181 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 182 | bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; |
| 183 | unsigned long tmp; |
| 184 | |
| 185 | /* IGD has to be enabled, GFXVTBAR set and enabled. */ |
| 186 | if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { |
| 187 | tmp = current; |
| 188 | |
| 189 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 190 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 191 | acpi_dmar_drhd_fixup(tmp, current); |
| 192 | |
| 193 | /* Add RMRR entry */ |
| 194 | tmp = current; |
| 195 | current += acpi_create_dmar_rmrr(current, 0, |
| 196 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 197 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 198 | acpi_dmar_rmrr_fixup(tmp, current); |
| 199 | } |
| 200 | |
| 201 | /* DEFVTBAR has to be set and enabled. */ |
| 202 | if (defvtbar && defvten) { |
| 203 | tmp = current; |
| 204 | /* |
| 205 | * P2SB may already be hidden. There's no clear rule, when. |
| 206 | * It is needed to get bus, device and function for IOAPIC and |
| 207 | * HPET device which is stored in P2SB device. So unhide it to |
| 208 | * get the info and hide it again when done. |
| 209 | */ |
| 210 | p2sb_unhide(); |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 211 | struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 212 | uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); |
| 213 | uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); |
| 214 | p2sb_hide(); |
| 215 | |
| 216 | current += acpi_create_dmar_drhd(current, |
| 217 | DRHD_INCLUDE_PCI_ALL, 0, defvtbar); |
| 218 | current += acpi_create_dmar_ds_ioapic(current, |
| 219 | 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); |
| 220 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 221 | 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); |
| 222 | acpi_dmar_drhd_fixup(tmp, current); |
| 223 | } |
| 224 | |
| 225 | return current; |
| 226 | } |
| 227 | |
| 228 | unsigned long sa_write_acpi_tables(struct device *const dev, |
| 229 | unsigned long current, |
| 230 | struct acpi_rsdp *const rsdp) |
| 231 | { |
| 232 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 233 | |
| 234 | /* Create DMAR table only if virtualization is enabled. Due to some |
| 235 | * constraints on Apollo Lake SoC (some stepping affected), VTD could |
| 236 | * not be enabled together with IPU. Doing so will override and disable |
| 237 | * VTD while leaving CAPID0_A still reporting that VTD is available. |
| 238 | * As in this case FSP will lock VTD to disabled state, we need to make |
| 239 | * sure that DMAR table generation only happens when at least DEFVTBAR |
| 240 | * is enabled. Otherwise the DMAR header will be generated while the |
| 241 | * content of the table will be missing. |
| 242 | */ |
| 243 | |
| 244 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 245 | !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) |
| 246 | return current; |
| 247 | |
| 248 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 249 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); |
| 250 | current += dmar->header.length; |
| 251 | current = acpi_align_current(current); |
| 252 | acpi_add_table(rsdp, dmar); |
| 253 | current = acpi_align_current(current); |
| 254 | |
| 255 | return current; |
| 256 | } |
| 257 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 258 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 259 | { |
| 260 | /* Generate P-state tables */ |
| 261 | generate_p_state_entries(core_id, cores_per_package); |
| 262 | |
| 263 | /* Generate T-state tables */ |
| 264 | generate_t_state_entries(core_id, cores_per_package); |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 265 | } |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 266 | |
| 267 | static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) |
| 268 | { |
| 269 | /* |
| 270 | * Store (\_SB.GPC0 (addr), Local5) |
| 271 | * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in |
| 272 | * gpiolib.asl. |
| 273 | */ |
| 274 | acpigen_write_store(); |
| 275 | acpigen_emit_namestring("\\_SB.GPC0"); |
| 276 | acpigen_write_integer(addr); |
| 277 | acpigen_emit_byte(LOCAL5_OP); |
| 278 | } |
| 279 | |
| 280 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 281 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 282 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 283 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 284 | |
| 285 | acpigen_soc_get_dw0_in_local5(addr); |
| 286 | |
| 287 | /* If (And (Local5, mask)) */ |
| 288 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 289 | |
| 290 | /* Store (One, Local0) */ |
| 291 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 292 | |
| 293 | acpigen_pop_len(); /* If */ |
| 294 | |
| 295 | /* Else */ |
| 296 | acpigen_write_else(); |
| 297 | |
| 298 | /* Store (Zero, Local0) */ |
| 299 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 300 | |
| 301 | acpigen_pop_len(); /* Else */ |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 307 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 308 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 309 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 310 | |
| 311 | acpigen_soc_get_dw0_in_local5(addr); |
| 312 | |
| 313 | if (val) { |
| 314 | /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ |
| 315 | acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); |
| 316 | } else { |
| 317 | /* Not (PAD_CFG0_TX_STATE, Local6) */ |
| 318 | acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); |
| 319 | |
| 320 | /* And (Local5, Local6, Local5) */ |
| 321 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * \_SB.SPC0 (addr, Local5) |
| 326 | * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in |
| 327 | * gpiolib.asl. |
| 328 | */ |
| 329 | acpigen_emit_namestring("\\_SB.SPC0"); |
| 330 | acpigen_write_integer(addr); |
| 331 | acpigen_emit_byte(LOCAL5_OP); |
| 332 | |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 337 | { |
| 338 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); |
| 339 | } |
| 340 | |
| 341 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 342 | { |
| 343 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); |
| 344 | } |
| 345 | |
| 346 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 347 | { |
| 348 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 349 | } |
| 350 | |
| 351 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 352 | { |
| 353 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 354 | } |