Patrick Georgi | 02363b5 | 2020-05-05 20:48:50 +0200 | [diff] [blame] | 1 | /* This file is part of the coreboot project. */ |
Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame^] | 2 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 3 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
| 5 | #include <acpi/acpigen.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 6 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 8 | #include <arch/smp/mpspec.h> |
Elyes HAOUAS | cd4fe0f | 2019-03-29 17:12:15 +0100 | [diff] [blame] | 9 | #include <assert.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 11 | #include <cbmem.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 12 | #include <cpu/x86/smm.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 13 | #include <gpio.h> |
| 14 | #include <intelblocks/acpi.h> |
| 15 | #include <intelblocks/pmclib.h> |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 16 | #include <intelblocks/sgx.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 17 | #include <intelblocks/p2sb.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 18 | #include <soc/iomap.h> |
| 19 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 20 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 21 | #include <soc/pci_devs.h> |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 22 | #include <soc/systemagent.h> |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 23 | #include <string.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 24 | |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 25 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 26 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 27 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 28 | { \ |
| 29 | .space_id = address_space, \ |
| 30 | .bit_width = width, \ |
| 31 | .bit_offset = offset, \ |
| 32 | .addrl = address, \ |
| 33 | } |
| 34 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 35 | static acpi_cstate_t cstate_map[] = { |
| 36 | { |
| 37 | /* C1 */ |
| 38 | .ctype = 1, /* ACPI C1 */ |
| 39 | .latency = 1, |
| 40 | .power = 1000, |
| 41 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 42 | }, |
| 43 | { |
| 44 | .ctype = 2, /* ACPI C2 */ |
| 45 | .latency = 50, |
| 46 | .power = 10, |
| 47 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 48 | }, |
| 49 | { |
| 50 | .ctype = 3, /* ACPI C3 */ |
| 51 | .latency = 150, |
| 52 | .power = 10, |
| 53 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 54 | } |
| 55 | }; |
| 56 | |
| 57 | uint32_t soc_read_sci_irq_select(void) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 58 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 59 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 60 | return read32((void *)pmc_bar + IRQ_REG); |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 61 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 62 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 63 | void soc_write_sci_irq_select(uint32_t scis) |
| 64 | { |
| 65 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 66 | write32((void *)pmc_bar + IRQ_REG, scis); |
| 67 | } |
| 68 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 69 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 70 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 71 | *entries = ARRAY_SIZE(cstate_map); |
| 72 | return cstate_map; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 73 | } |
| 74 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 75 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 76 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 77 | struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 78 | cfg = config_of_soc(); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 79 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 80 | /* Clear out GNVS. */ |
| 81 | memset(gnvs, 0, sizeof(*gnvs)); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 82 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 83 | if (CONFIG(CONSOLE_CBMEM)) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 84 | gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 85 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 86 | if (CONFIG(CHROMEOS)) { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 87 | /* Initialize Verified Boot data */ |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 88 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 89 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 90 | } |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 91 | |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 92 | /* Set unknown wake source */ |
| 93 | gnvs->pm1i = ~0ULL; |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 94 | |
Duncan Laurie | 1d359b5 | 2016-09-21 18:30:44 -0700 | [diff] [blame] | 95 | /* CPU core count */ |
| 96 | gnvs->pcnt = dev_count_cpu(); |
| 97 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 98 | /* Enable DPTF based on mainboard configuration */ |
| 99 | gnvs->dpte = cfg->dptf_enable; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 100 | |
| 101 | /* Assign address of PERST_0 if GPIO is defined in devicetree */ |
| 102 | if (cfg->prt0_gpio != GPIO_PRT0_UDEF) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 103 | gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio); |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 104 | |
Venkateswarlu Vinjamuri | 99ce8a9 | 2017-03-22 18:24:52 -0700 | [diff] [blame] | 105 | /* Get sdcard cd GPIO portid if GPIO is defined in devicetree. |
| 106 | * Get offset of sdcard cd pin. |
| 107 | */ |
| 108 | if (cfg->sdcard_cd_gpio) { |
| 109 | gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio); |
| 110 | gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); |
| 111 | } |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 112 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 113 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) |
Pratik Prajapati | d06c764 | 2017-10-11 11:52:16 -0700 | [diff] [blame] | 114 | sgx_fill_gnvs(gnvs); |
Subrata Banik | b6df6b0 | 2020-01-03 15:29:02 +0530 | [diff] [blame] | 115 | |
| 116 | /* Fill in Above 4GB MMIO resource */ |
| 117 | sa_fill_gnvs(gnvs); |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 120 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 121 | const struct chipset_power_state *ps) |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 122 | { |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 123 | /* |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 124 | * WAK_STS bit is set when the system is in one of the sleep states |
| 125 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 126 | * this bit, the PMC will transition the system to the ON state and |
| 127 | * can only be set by hardware and can only be cleared by writing a one |
| 128 | * to this bit position. |
| 129 | */ |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 130 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 131 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 132 | return generic_pm1_en; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 135 | int soc_madt_sci_irq_polarity(int sci) |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 136 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 137 | return MP_IRQ_POLARITY_LOW; |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 140 | void soc_fill_fadt(acpi_fadt_t *fadt) |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 141 | { |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 142 | const struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 143 | cfg = config_of_soc(); |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 144 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 145 | fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; |
| 146 | |
| 147 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 148 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 149 | |
| 150 | fadt->pm_tmr_len = 4; |
| 151 | fadt->duty_width = 3; |
| 152 | |
| 153 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 154 | |
| 155 | fadt->x_pm_tmr_blk.space_id = 1; |
| 156 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 157 | fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 158 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 159 | |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 160 | if (cfg->lpss_s0ix_enable) |
Shaunak Saha | 7210ec0 | 2017-12-13 09:37:05 -0800 | [diff] [blame] | 161 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 164 | static unsigned long soc_fill_dmar(unsigned long current) |
| 165 | { |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 166 | struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 167 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 168 | uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; |
| 169 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 170 | bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; |
| 171 | unsigned long tmp; |
| 172 | |
| 173 | /* IGD has to be enabled, GFXVTBAR set and enabled. */ |
| 174 | if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { |
| 175 | tmp = current; |
| 176 | |
| 177 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 178 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 179 | acpi_dmar_drhd_fixup(tmp, current); |
| 180 | |
| 181 | /* Add RMRR entry */ |
| 182 | tmp = current; |
| 183 | current += acpi_create_dmar_rmrr(current, 0, |
| 184 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 185 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 186 | acpi_dmar_rmrr_fixup(tmp, current); |
| 187 | } |
| 188 | |
| 189 | /* DEFVTBAR has to be set and enabled. */ |
| 190 | if (defvtbar && defvten) { |
| 191 | tmp = current; |
| 192 | /* |
| 193 | * P2SB may already be hidden. There's no clear rule, when. |
| 194 | * It is needed to get bus, device and function for IOAPIC and |
| 195 | * HPET device which is stored in P2SB device. So unhide it to |
| 196 | * get the info and hide it again when done. |
| 197 | */ |
| 198 | p2sb_unhide(); |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 199 | struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 200 | uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); |
| 201 | uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); |
| 202 | p2sb_hide(); |
| 203 | |
| 204 | current += acpi_create_dmar_drhd(current, |
| 205 | DRHD_INCLUDE_PCI_ALL, 0, defvtbar); |
| 206 | current += acpi_create_dmar_ds_ioapic(current, |
| 207 | 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); |
| 208 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 209 | 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); |
| 210 | acpi_dmar_drhd_fixup(tmp, current); |
| 211 | } |
| 212 | |
| 213 | return current; |
| 214 | } |
| 215 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 216 | unsigned long sa_write_acpi_tables(const struct device *const dev, |
Werner Zeh | 90cc7e2 | 2018-12-14 13:26:04 +0100 | [diff] [blame] | 217 | unsigned long current, |
| 218 | struct acpi_rsdp *const rsdp) |
| 219 | { |
| 220 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 221 | |
| 222 | /* Create DMAR table only if virtualization is enabled. Due to some |
| 223 | * constraints on Apollo Lake SoC (some stepping affected), VTD could |
| 224 | * not be enabled together with IPU. Doing so will override and disable |
| 225 | * VTD while leaving CAPID0_A still reporting that VTD is available. |
| 226 | * As in this case FSP will lock VTD to disabled state, we need to make |
| 227 | * sure that DMAR table generation only happens when at least DEFVTBAR |
| 228 | * is enabled. Otherwise the DMAR header will be generated while the |
| 229 | * content of the table will be missing. |
| 230 | */ |
| 231 | |
| 232 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 233 | !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) |
| 234 | return current; |
| 235 | |
| 236 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 237 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); |
| 238 | current += dmar->header.length; |
| 239 | current = acpi_align_current(current); |
| 240 | acpi_add_table(rsdp, dmar); |
| 241 | current = acpi_align_current(current); |
| 242 | |
| 243 | return current; |
| 244 | } |
| 245 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 246 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 247 | { |
| 248 | /* Generate P-state tables */ |
| 249 | generate_p_state_entries(core_id, cores_per_package); |
| 250 | |
| 251 | /* Generate T-state tables */ |
| 252 | generate_t_state_entries(core_id, cores_per_package); |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 253 | } |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 254 | |
| 255 | static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) |
| 256 | { |
| 257 | /* |
| 258 | * Store (\_SB.GPC0 (addr), Local5) |
| 259 | * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in |
| 260 | * gpiolib.asl. |
| 261 | */ |
| 262 | acpigen_write_store(); |
| 263 | acpigen_emit_namestring("\\_SB.GPC0"); |
| 264 | acpigen_write_integer(addr); |
| 265 | acpigen_emit_byte(LOCAL5_OP); |
| 266 | } |
| 267 | |
| 268 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 269 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 270 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 271 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 272 | |
| 273 | acpigen_soc_get_dw0_in_local5(addr); |
| 274 | |
| 275 | /* If (And (Local5, mask)) */ |
| 276 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 277 | |
| 278 | /* Store (One, Local0) */ |
| 279 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 280 | |
| 281 | acpigen_pop_len(); /* If */ |
| 282 | |
| 283 | /* Else */ |
| 284 | acpigen_write_else(); |
| 285 | |
| 286 | /* Store (Zero, Local0) */ |
| 287 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 288 | |
| 289 | acpigen_pop_len(); /* Else */ |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 295 | { |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 296 | assert(gpio_num < TOTAL_PADS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 297 | uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 298 | |
| 299 | acpigen_soc_get_dw0_in_local5(addr); |
| 300 | |
| 301 | if (val) { |
| 302 | /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ |
| 303 | acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); |
| 304 | } else { |
| 305 | /* Not (PAD_CFG0_TX_STATE, Local6) */ |
| 306 | acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); |
| 307 | |
| 308 | /* And (Local5, Local6, Local5) */ |
| 309 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 310 | } |
| 311 | |
| 312 | /* |
| 313 | * \_SB.SPC0 (addr, Local5) |
| 314 | * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in |
| 315 | * gpiolib.asl. |
| 316 | */ |
| 317 | acpigen_emit_namestring("\\_SB.SPC0"); |
| 318 | acpigen_write_integer(addr); |
| 319 | acpigen_emit_byte(LOCAL5_OP); |
| 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 325 | { |
| 326 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); |
| 327 | } |
| 328 | |
| 329 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 330 | { |
| 331 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); |
| 332 | } |
| 333 | |
| 334 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 335 | { |
| 336 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 337 | } |
| 338 | |
| 339 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 340 | { |
| 341 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 342 | } |