Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include "psp_verstage.h" |
| 4 | |
Felix Held | 26935d1 | 2020-12-08 00:40:04 +0100 | [diff] [blame] | 5 | #include <amdblocks/acpimmio.h> |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 6 | #include <bl_uapp/bl_syscall_public.h> |
| 7 | #include <boot_device.h> |
Martin Roth | e21698b | 2020-06-26 08:55:15 -0600 | [diff] [blame] | 8 | #include <cbfs.h> |
Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 9 | #include <commonlib/region.h> |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 10 | #include <console/console.h> |
Martin Roth | e21698b | 2020-06-26 08:55:15 -0600 | [diff] [blame] | 11 | #include <fmap.h> |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 12 | #include <pc80/mc146818rtc.h> |
Kangheui Won | fab6e44 | 2021-10-18 15:35:28 +1100 | [diff] [blame] | 13 | #include <soc/iomap.h> |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 14 | #include <soc/psp_transfer.h> |
Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 15 | #include <security/tpm/tspi.h> |
| 16 | #include <security/tpm/tss.h> |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 17 | #include <security/vboot/vbnv.h> |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 18 | #include <security/vboot/misc.h> |
| 19 | #include <security/vboot/symbols.h> |
| 20 | #include <security/vboot/vboot_common.h> |
| 21 | #include <arch/stages.h> |
| 22 | #include <stdarg.h> |
| 23 | #include <stdio.h> |
Kangheui Won | 4e2f5fd | 2020-09-17 16:37:13 +1000 | [diff] [blame] | 24 | #include <timestamp.h> |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 25 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 26 | extern char _bss_start, _bss_end; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 27 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 28 | void __weak verstage_mainboard_init(void) {} |
Rob Barnes | 188be6b | 2021-11-09 13:21:28 -0700 | [diff] [blame] | 29 | |
Kangheui Won | 695732b | 2021-04-25 12:11:17 +1000 | [diff] [blame] | 30 | uint32_t __weak get_max_workbuf_size(uint32_t *size) |
| 31 | { |
| 32 | /* This svc only exists in picasso and deprecated for later platforms. |
| 33 | * Provide sane default function here for those platforms. |
| 34 | */ |
| 35 | *size = (uint32_t)((uintptr_t)_etransfer_buffer - (uintptr_t)_transfer_buffer); |
| 36 | return 0; |
| 37 | } |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 38 | |
| 39 | static void reboot_into_recovery(struct vb2_context *ctx, uint32_t subcode) |
| 40 | { |
| 41 | subcode += PSP_VBOOT_ERROR_SUBCODE; |
| 42 | svc_write_postcode(subcode); |
| 43 | |
Martin Roth | c9689e0 | 2020-08-20 17:25:37 -0600 | [diff] [blame] | 44 | /* |
| 45 | * If there's an error but the PSP_verstage is already booting to RO, |
| 46 | * don't reset the system. It may be that the error is fatal, but if |
| 47 | * the system is stuck, don't intentionally force it into a reboot loop. |
| 48 | */ |
| 49 | if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { |
| 50 | printk(BIOS_ERR, "Already in recovery mode. Staying in RO.\n"); |
| 51 | return; |
| 52 | } |
| 53 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 54 | vb2api_fail(ctx, VB2_RECOVERY_RO_UNSPECIFIED, (int)subcode); |
| 55 | vboot_save_data(ctx); |
| 56 | |
| 57 | svc_debug_print("Rebooting into recovery\n"); |
| 58 | vboot_reboot(); |
| 59 | } |
| 60 | |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 61 | static uint32_t check_cmos_recovery(void) |
| 62 | { |
| 63 | /* Only reset if cmos is valid */ |
| 64 | if (vbnv_cmos_failed()) |
| 65 | return 0; |
| 66 | |
| 67 | /* If the byte is set, clear it, then return error to reboot */ |
| 68 | if (cmos_read(CMOS_RECOVERY_BYTE) == CMOS_RECOVERY_MAGIC_VAL) { |
| 69 | cmos_write(0x00, CMOS_RECOVERY_BYTE); |
| 70 | printk(BIOS_DEBUG, "Reboot into recovery requested by coreboot\n"); |
| 71 | return POSTCODE_CMOS_RECOVERY; |
| 72 | } |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 77 | /* |
| 78 | * Tell the PSP where to load the rest of the firmware from |
| 79 | */ |
| 80 | static uint32_t update_boot_region(struct vb2_context *ctx) |
| 81 | { |
Kangheui Won | 26bb4aa | 2021-10-18 15:31:45 +1100 | [diff] [blame] | 82 | struct embedded_firmware *ef_table; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 83 | uint32_t psp_dir_addr, bios_dir_addr; |
| 84 | uint32_t *psp_dir_in_spi, *bios_dir_in_spi; |
Kangheui Won | ac7ec27 | 2021-01-15 15:04:25 +1100 | [diff] [blame] | 85 | const char *fname; |
| 86 | void *amdfw_location; |
Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 87 | void *boot_dev_base = rdev_mmap_full(boot_device_ro()); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 88 | |
| 89 | /* Continue booting from RO */ |
| 90 | if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { |
| 91 | printk(BIOS_ERR, "In recovery mode. Staying in RO.\n"); |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | if (vboot_is_firmware_slot_a(ctx)) { |
Martin Roth | e21698b | 2020-06-26 08:55:15 -0600 | [diff] [blame] | 96 | fname = "apu/amdfw_a"; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 97 | } else { |
Martin Roth | e21698b | 2020-06-26 08:55:15 -0600 | [diff] [blame] | 98 | fname = "apu/amdfw_b"; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 99 | } |
| 100 | |
Kangheui Won | ac7ec27 | 2021-01-15 15:04:25 +1100 | [diff] [blame] | 101 | amdfw_location = cbfs_map(fname, NULL); |
Martin Roth | e21698b | 2020-06-26 08:55:15 -0600 | [diff] [blame] | 102 | if (!amdfw_location) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 103 | printk(BIOS_ERR, "AMD Firmware table not found.\n"); |
Martin Roth | e21698b | 2020-06-26 08:55:15 -0600 | [diff] [blame] | 104 | return POSTCODE_AMD_FW_MISSING; |
| 105 | } |
Kangheui Won | 26bb4aa | 2021-10-18 15:31:45 +1100 | [diff] [blame] | 106 | ef_table = (struct embedded_firmware *)amdfw_location; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 107 | if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 108 | printk(BIOS_ERR, "ROMSIG address is not correct.\n"); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 109 | return POSTCODE_ROMSIG_MISMATCH_ERROR; |
| 110 | } |
| 111 | |
Kangheui Won | 26bb4aa | 2021-10-18 15:31:45 +1100 | [diff] [blame] | 112 | psp_dir_addr = ef_table->combo_psp_directory; |
Kangheui Won | 5858fb4 | 2021-05-06 13:30:51 +1000 | [diff] [blame] | 113 | bios_dir_addr = get_bios_dir_addr(ef_table); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 114 | psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + |
Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 115 | (uint32_t)boot_dev_base); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 116 | bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + |
Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 117 | (uint32_t)boot_dev_base); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 118 | if (*psp_dir_in_spi != PSP_COOKIE) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 119 | printk(BIOS_ERR, "PSP Directory address is not correct.\n"); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 120 | return POSTCODE_PSP_COOKIE_MISMATCH_ERROR; |
| 121 | } |
| 122 | if (*bios_dir_in_spi != BDT1_COOKIE) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 123 | printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 124 | return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; |
| 125 | } |
| 126 | |
Kangheui Won | fab6e44 | 2021-10-18 15:35:28 +1100 | [diff] [blame] | 127 | /* EFS2 uses relative address and PSP isn't happy with that */ |
| 128 | if (ef_table->efs_gen.gen == EFS_SECOND_GEN) { |
| 129 | psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK); |
| 130 | bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK); |
| 131 | } |
| 132 | |
Kangheui Won | 26bb4aa | 2021-10-18 15:31:45 +1100 | [diff] [blame] | 133 | if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 134 | printk(BIOS_ERR, "Updated BIOS Directory could not be set.\n"); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 135 | return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; |
| 136 | } |
| 137 | |
| 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Save workbuf (and soon memory console and timestamps) to the bootloader to pass |
| 143 | * back to coreboot. |
| 144 | */ |
| 145 | static uint32_t save_buffers(struct vb2_context **ctx) |
| 146 | { |
| 147 | uint32_t retval; |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 148 | uint32_t buffer_size = MIN_TRANSFER_BUFFER_SIZE; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 149 | uint32_t max_buffer_size; |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 150 | struct transfer_info_struct buffer_info = {0}; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 151 | |
| 152 | /* |
Kangheui Won | 695732b | 2021-04-25 12:11:17 +1000 | [diff] [blame] | 153 | * This should never fail on picasso, but if it does, we should still |
| 154 | * try to save the buffer. If that fails, then we should go to |
| 155 | * recovery mode. |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 156 | */ |
Kangheui Won | 695732b | 2021-04-25 12:11:17 +1000 | [diff] [blame] | 157 | if (get_max_workbuf_size(&max_buffer_size)) { |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 158 | post_code(POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE); |
| 159 | printk(BIOS_NOTICE, "Notice: using default transfer buffer size.\n"); |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 160 | max_buffer_size = MIN_TRANSFER_BUFFER_SIZE; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 161 | } |
| 162 | printk(BIOS_DEBUG, "\nMaximum buffer size: %d bytes\n", max_buffer_size); |
| 163 | |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 164 | /* Shrink workbuf if MP2 is in use and cannot be used to save buffer */ |
| 165 | if (max_buffer_size < VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) { |
| 166 | retval = vb2api_relocate(_vboot2_work, _vboot2_work, MIN_WORKBUF_TRANSFER_SIZE, |
| 167 | ctx); |
| 168 | if (retval != VB2_SUCCESS) { |
| 169 | printk(BIOS_ERR, "Error shrinking workbuf. Error code %#x\n", retval); |
| 170 | buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE; |
| 171 | post_code(POSTCODE_WORKBUF_RESIZE_WARNING); |
| 172 | } |
| 173 | } else { |
| 174 | buffer_size = |
| 175 | (uint32_t)((uintptr_t)_etransfer_buffer - (uintptr_t)_transfer_buffer); |
| 176 | |
| 177 | buffer_info.console_offset = (uint32_t)((uintptr_t)_preram_cbmem_console - |
| 178 | (uintptr_t)_transfer_buffer); |
| 179 | buffer_info.timestamp_offset = (uint32_t)((uintptr_t)_timestamp - |
| 180 | (uintptr_t)_transfer_buffer); |
| 181 | buffer_info.fmap_offset = (uint32_t)((uintptr_t)_fmap_cache - |
| 182 | (uintptr_t)_transfer_buffer); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | if (buffer_size > max_buffer_size) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 186 | printk(BIOS_ERR, "Buffer is larger than max buffer size.\n"); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 187 | post_code(POSTCODE_WORKBUF_BUFFER_SIZE_ERROR); |
| 188 | return POSTCODE_WORKBUF_BUFFER_SIZE_ERROR; |
| 189 | } |
| 190 | |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 191 | buffer_info.magic_val = TRANSFER_MAGIC_VAL; |
| 192 | buffer_info.struct_bytes = sizeof(buffer_info); |
| 193 | buffer_info.buffer_size = buffer_size; |
| 194 | buffer_info.workbuf_offset = (uint32_t)((uintptr_t)_fmap_cache - |
| 195 | (uintptr_t)_vboot2_work); |
| 196 | |
Kangheui Won | 5f027fa | 2020-08-25 18:12:19 +1000 | [diff] [blame] | 197 | memcpy(_transfer_buffer, &buffer_info, sizeof(buffer_info)); |
| 198 | |
Kangheui Won | a767eb4 | 2021-04-14 09:35:28 +1000 | [diff] [blame] | 199 | retval = save_uapp_data((void *)_transfer_buffer, buffer_size); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 200 | if (retval) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 201 | printk(BIOS_ERR, "Could not save workbuf. Error code 0x%08x\n", retval); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 202 | return POSTCODE_WORKBUF_SAVE_ERROR; |
| 203 | } |
| 204 | |
| 205 | return 0; |
| 206 | } |
| 207 | |
Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 208 | /* |
| 209 | * S0i3 resume in PSP verstage is a special case. The FSDL is restoring mostly |
| 210 | * everything, so do the minimum necessary here. Unlike normal boot, subsequent |
| 211 | * coreboot stages are not run after s0i3 verstage. |
| 212 | * If the TPM is reset in S0i3, it must be re-initialized here. |
| 213 | */ |
| 214 | static void psp_verstage_s0i3_resume(void) |
| 215 | { |
| 216 | uint32_t rv; |
| 217 | |
| 218 | post_code(POSTCODE_VERSTAGE_S0I3_RESUME); |
| 219 | |
| 220 | printk(BIOS_DEBUG, "Entering PSP verstage S0i3 resume\n"); |
| 221 | |
| 222 | if (!CONFIG(PSP_INIT_TPM_ON_S0I3_RESUME)) |
| 223 | return; |
| 224 | |
| 225 | rv = tpm_setup(true); |
| 226 | if (rv != TPM_SUCCESS) { |
| 227 | printk(BIOS_ERR, "tpm_setup failed rv:%d\n", rv); |
| 228 | reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); |
| 229 | } |
| 230 | |
| 231 | rv = tlcl_disable_platform_hierarchy(); |
| 232 | if (rv != TPM_SUCCESS) { |
| 233 | printk(BIOS_ERR, "tlcl_disable_platform_hierarchy failed rv:%d\n", rv); |
| 234 | reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); |
| 235 | } |
| 236 | } |
| 237 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 238 | void Main(void) |
| 239 | { |
| 240 | uint32_t retval; |
| 241 | struct vb2_context *ctx = NULL; |
Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 242 | void *boot_dev_base; |
Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 243 | uint32_t bootmode; |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 244 | |
| 245 | /* |
| 246 | * Do not use printk() before console_init() |
| 247 | * Do not use post_code() before verstage_mainboard_init() |
| 248 | */ |
Kangheui Won | 4e2f5fd | 2020-09-17 16:37:13 +1000 | [diff] [blame] | 249 | timestamp_init(timestamp_get()); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 250 | svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); |
| 251 | svc_debug_print("Entering verstage on PSP\n"); |
| 252 | memset(&_bss_start, '\0', &_bss_end - &_bss_start); |
| 253 | |
| 254 | svc_write_postcode(POSTCODE_CONSOLE_INIT); |
| 255 | console_init(); |
| 256 | |
| 257 | svc_write_postcode(POSTCODE_EARLY_INIT); |
| 258 | retval = verstage_soc_early_init(); |
| 259 | if (retval) { |
Rob Barnes | c30a1fa | 2021-11-08 06:43:07 -0700 | [diff] [blame] | 260 | /* |
| 261 | * If verstage_soc_early_init fails, cmos is probably not |
| 262 | * accessible, so rebooting into recovery is not an option. |
| 263 | * Just reboot and hope for the best. |
| 264 | */ |
| 265 | svc_write_postcode(POSTCODE_EARLY_INIT_ERROR); |
| 266 | svc_debug_print("verstage_soc_early_init failed! -- rebooting\n"); |
| 267 | vboot_reboot(); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 268 | } |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 269 | |
Rob Barnes | f6e421f | 2021-11-08 13:04:18 -0700 | [diff] [blame] | 270 | printk(BIOS_DEBUG, "calling verstage_mainboard_espi_init\n"); |
| 271 | verstage_mainboard_espi_init(); |
| 272 | |
Rob Barnes | 188be6b | 2021-11-09 13:21:28 -0700 | [diff] [blame] | 273 | printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); |
| 274 | verstage_soc_espi_init(); |
| 275 | |
| 276 | printk(BIOS_DEBUG, "calling verstage_mainboard_tpm_init\n"); |
| 277 | /* mainboard_tpm_init may check board_id, so make sure espi is ready first */ |
| 278 | verstage_mainboard_tpm_init(); |
| 279 | |
Rob Barnes | 847a39f | 2021-11-15 12:56:34 -0700 | [diff] [blame] | 280 | printk(BIOS_DEBUG, "calling verstage_soc_aoac_init\n"); |
| 281 | verstage_soc_aoac_init(); |
| 282 | |
| 283 | printk(BIOS_DEBUG, "calling verstage_soc_i2c_init\n"); |
| 284 | verstage_soc_i2c_init(); |
| 285 | |
Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 286 | /* |
| 287 | * S0i3 resume in PSP verstage is a special case, handle it separately. |
| 288 | * Make sure TPM i2c is ready first. |
| 289 | */ |
| 290 | svc_get_boot_mode(&bootmode); |
| 291 | if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { |
| 292 | psp_verstage_s0i3_resume(); |
| 293 | unmap_fch_devices(); |
| 294 | svc_exit(0); |
| 295 | } |
| 296 | |
| 297 | printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); |
| 298 | verstage_mainboard_early_init(); |
| 299 | |
| 300 | svc_write_postcode(POSTCODE_LATE_INIT); |
| 301 | fch_io_enable_legacy_io(); |
| 302 | |
Rob Barnes | 847a39f | 2021-11-15 12:56:34 -0700 | [diff] [blame] | 303 | printk(BIOS_DEBUG, "calling verstage_soc_spi_init\n"); |
| 304 | verstage_soc_spi_init(); |
| 305 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 306 | verstage_mainboard_init(); |
| 307 | |
| 308 | post_code(POSTCODE_VERSTAGE_MAIN); |
| 309 | |
Kangheui Won | ac7ec27 | 2021-01-15 15:04:25 +1100 | [diff] [blame] | 310 | vboot_run_logic(); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 311 | |
Martin Roth | c9689e0 | 2020-08-20 17:25:37 -0600 | [diff] [blame] | 312 | ctx = vboot_get_context(); |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 313 | retval = check_cmos_recovery(); |
| 314 | if (retval) |
Martin Roth | c9689e0 | 2020-08-20 17:25:37 -0600 | [diff] [blame] | 315 | reboot_into_recovery(ctx, retval); |
Martin Roth | 0c12abe | 2020-06-26 08:40:56 -0600 | [diff] [blame] | 316 | |
Kangheui Won | 7e91db7 | 2022-01-25 18:55:04 +1100 | [diff] [blame] | 317 | platform_report_mode(vboot_developer_mode_enabled()); |
| 318 | |
Kangheui Won | ac7ec27 | 2021-01-15 15:04:25 +1100 | [diff] [blame] | 319 | post_code(POSTCODE_UPDATE_BOOT_REGION); |
Kangheui Won | 9752725 | 2021-05-20 10:02:00 +1000 | [diff] [blame] | 320 | |
| 321 | /* |
| 322 | * Since psp_verstage doesn't load next stage we never call |
| 323 | * any cbfs API on RO path. However we still need to initialize |
| 324 | * RO CBFS MCACHE manually to pass it in transfer_buffer. |
| 325 | * In RW path, MCACHE build will be skipped for RO region since |
| 326 | * we already built here. |
| 327 | */ |
| 328 | cbfs_get_boot_device(true); |
| 329 | |
Kangheui Won | ac7ec27 | 2021-01-15 15:04:25 +1100 | [diff] [blame] | 330 | retval = update_boot_region(ctx); |
| 331 | if (retval) |
| 332 | reboot_into_recovery(ctx, retval); |
| 333 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 334 | post_code(POSTCODE_SAVE_BUFFERS); |
| 335 | retval = save_buffers(&ctx); |
| 336 | if (retval) |
Martin Roth | c9689e0 | 2020-08-20 17:25:37 -0600 | [diff] [blame] | 337 | reboot_into_recovery(ctx, retval); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 338 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 339 | |
| 340 | post_code(POSTCODE_UNMAP_SPI_ROM); |
Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 341 | boot_dev_base = rdev_mmap_full(boot_device_ro()); |
| 342 | if (boot_dev_base) { |
| 343 | if (svc_unmap_spi_rom((void *)boot_dev_base)) |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 344 | printk(BIOS_ERR, "Error unmapping SPI rom\n"); |
| 345 | } |
| 346 | |
| 347 | post_code(POSTCODE_UNMAP_FCH_DEVICES); |
| 348 | unmap_fch_devices(); |
| 349 | |
| 350 | post_code(POSTCODE_LEAVING_VERSTAGE); |
| 351 | |
| 352 | printk(BIOS_DEBUG, "Leaving verstage on PSP\n"); |
| 353 | svc_exit(retval); |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 354 | } |
| 355 | |
Martin Roth | c7acf16 | 2020-05-28 00:44:50 -0600 | [diff] [blame] | 356 | /* |
| 357 | * The stage_entry function is not used directly, but stage_entry() is marked as an entry |
| 358 | * point in arm/arch/header.h, so if stage_entry() isn't present and calling Main(), all |
| 359 | * the verstage code gets dropped by the linker. Slightly hacky, but mostly harmless. |
| 360 | */ |
| 361 | void stage_entry(uintptr_t stage_arg) |
| 362 | { |
| 363 | Main(); |
| 364 | } |