Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 2 | |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 3 | menu "Devices" |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 4 | |
Nico Huber | ce642f0 | 2017-05-19 15:08:21 +0200 | [diff] [blame] | 5 | config HAVE_VGA_TEXT_FRAMEBUFFER |
Vladimir Serbinenko | 160e9a0 | 2014-02-22 10:34:47 +0100 | [diff] [blame] | 6 | bool |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 7 | depends on !(NO_GFX_INIT && NO_EARLY_GFX_INIT) |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 8 | help |
| 9 | Selected by graphics drivers that support legacy VGA text mode. |
| 10 | |
| 11 | config HAVE_VBE_LINEAR_FRAMEBUFFER |
| 12 | bool |
Michael Niewöhner | 1513d72 | 2019-10-29 20:38:10 +0100 | [diff] [blame] | 13 | depends on !NO_GFX_INIT |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 14 | help |
| 15 | Selected by graphics drivers that can set up a VBE linear-framebuffer |
| 16 | mode. |
| 17 | |
| 18 | config HAVE_LINEAR_FRAMEBUFFER |
| 19 | bool |
Michael Niewöhner | 1513d72 | 2019-10-29 20:38:10 +0100 | [diff] [blame] | 20 | depends on !NO_GFX_INIT |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 21 | help |
| 22 | Selected by graphics drivers that can set up a generic linear |
| 23 | framebuffer. |
Vladimir Serbinenko | 160e9a0 | 2014-02-22 10:34:47 +0100 | [diff] [blame] | 24 | |
Nico Huber | 2e7f6cc | 2017-05-22 15:58:03 +0200 | [diff] [blame] | 25 | config HAVE_FSP_GOP |
| 26 | bool |
| 27 | help |
| 28 | Selected by drivers that support to run a blob that implements |
| 29 | the Graphics Output Protocol (GOP). |
| 30 | |
Michael Niewöhner | d61a40e | 2019-10-26 10:37:42 +0200 | [diff] [blame] | 31 | config MAINBOARD_NO_FSP_GOP |
| 32 | bool |
| 33 | help |
| 34 | Selected by mainboards that do not have any graphics ports connected to the SoC. |
| 35 | |
Nico Huber | 26ce9af | 2017-05-22 13:22:09 +0200 | [diff] [blame] | 36 | config MAINBOARD_HAS_NATIVE_VGA_INIT |
| 37 | def_bool n |
| 38 | help |
| 39 | Selected by mainboards / drivers that provide native graphics |
| 40 | init within coreboot. |
| 41 | |
| 42 | config MAINBOARD_FORCE_NATIVE_VGA_INIT |
| 43 | def_bool n |
| 44 | depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT |
Nico Huber | 26ce9af | 2017-05-22 13:22:09 +0200 | [diff] [blame] | 45 | help |
| 46 | Selected by mainboards / chipsets whose graphics driver can't or |
| 47 | shouldn't be disabled. |
| 48 | |
Subrata Banik | af03936 | 2020-12-30 16:09:56 +0530 | [diff] [blame] | 49 | config VGA_ROM_RUN_DEFAULT |
| 50 | def_bool n |
| 51 | help |
| 52 | Selected by mainboards whose graphics initialization depends on VGA OpROM. |
| 53 | coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX. |
| 54 | |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 55 | config MAINBOARD_HAS_LIBGFXINIT |
| 56 | def_bool n |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 57 | help |
| 58 | Selected by mainboards that implement support for `libgfxinit`. |
| 59 | Usually this requires a list of ports to be probed for displays. |
| 60 | |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 61 | config MAINBOARD_HAS_EARLY_LIBGFXINIT |
| 62 | def_bool n |
| 63 | help |
| 64 | Selected by mainboards that implement early (cache-as-ram |
| 65 | stage) support of `libgfxinit`. Usually this requires a list |
| 66 | of ports to be probed for displays. |
| 67 | |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 68 | choice |
| 69 | prompt "Graphics initialization" |
Subrata Banik | af03936 | 2020-12-30 16:09:56 +0530 | [diff] [blame] | 70 | default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS |
| 71 | default VGA_ROM_RUN if VGA_ROM_RUN_DEFAULT |
Matt DeVillier | 8107c81 | 2020-03-27 03:09:21 -0500 | [diff] [blame] | 72 | default MAINBOARD_DO_NATIVE_VGA_INIT |
| 73 | default MAINBOARD_USE_LIBGFXINIT |
Matt DeVillier | 175ffd8 | 2020-03-29 18:20:23 -0500 | [diff] [blame] | 74 | default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 75 | |
| 76 | config MAINBOARD_DO_NATIVE_VGA_INIT |
| 77 | bool "Use native graphics init" |
| 78 | depends on MAINBOARD_HAS_NATIVE_VGA_INIT |
| 79 | help |
| 80 | Some mainboards, such as the Google Link, allow initializing the |
| 81 | display without the need of a binary only VGA OPROM. Enabling this |
| 82 | option may be faster, but also lacks flexibility in setting modes. |
| 83 | |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 84 | config MAINBOARD_USE_LIBGFXINIT |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 85 | bool "Use libgfxinit" |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 86 | depends on MAINBOARD_HAS_LIBGFXINIT |
Nico Huber | ce642f0 | 2017-05-19 15:08:21 +0200 | [diff] [blame] | 87 | select HAVE_VGA_TEXT_FRAMEBUFFER |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 88 | select HAVE_LINEAR_FRAMEBUFFER |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 89 | select VGA if VGA_TEXT_FRAMEBUFFER |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 90 | help |
| 91 | Use the SPARK library `libgfxinit` for the native graphics |
| 92 | initialization. This requires an Ada toolchain. |
| 93 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 94 | # TODO: Explain differences (if any) for onboard cards. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 95 | config VGA_ROM_RUN |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 96 | bool "Run VGA Option ROMs" |
Jonathan Neuschäfer | c22ad58 | 2018-11-30 00:06:50 +0100 | [diff] [blame] | 97 | depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT |
Nico Huber | ce642f0 | 2017-05-19 15:08:21 +0200 | [diff] [blame] | 98 | select HAVE_VGA_TEXT_FRAMEBUFFER |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 99 | help |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 100 | Execute VGA Option ROMs in coreboot if found. This can be used |
Peter Stuge | b6fa47c | 2012-10-27 13:45:51 +0200 | [diff] [blame] | 101 | to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS |
| 102 | payload. |
| 103 | |
| 104 | When using a SeaBIOS payload it runs all option ROMs with much |
| 105 | more complete BIOS interrupt services available than coreboot, |
| 106 | which some option ROMs require in order to function correctly. |
| 107 | |
Arthur Heymans | 4ad1f7d | 2018-01-16 17:22:20 +0100 | [diff] [blame] | 108 | config RUN_FSP_GOP |
| 109 | bool "Run a GOP driver" |
Michael Niewöhner | d61a40e | 2019-10-26 10:37:42 +0200 | [diff] [blame] | 110 | depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP |
Arthur Heymans | 4ad1f7d | 2018-01-16 17:22:20 +0100 | [diff] [blame] | 111 | select HAVE_LINEAR_FRAMEBUFFER |
| 112 | help |
| 113 | Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support |
| 114 | to run a GOP blob. This option enables graphics initialization with |
| 115 | such a blob. |
| 116 | |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 117 | config NO_GFX_INIT |
| 118 | bool "None" |
| 119 | depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT |
| 120 | help |
| 121 | Select this to not perform any graphics initialization in |
| 122 | coreboot. This is useful if the payload (e.g. SeaBIOS) can |
| 123 | initialize graphics or if pre-boot graphics are not required. |
| 124 | |
| 125 | endchoice |
Myles Watson | e680495 | 2009-08-28 14:36:12 +0000 | [diff] [blame] | 126 | |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 127 | choice |
| 128 | prompt "Early (romstage) graphics initialization" |
| 129 | default MAINBOARD_USE_EARLY_LIBGFXINIT if MAINBOARD_HAS_EARLY_LIBGFXINIT |
| 130 | default NO_EARLY_GFX_INIT |
| 131 | |
| 132 | config NO_EARLY_GFX_INIT |
| 133 | bool "None" |
| 134 | help |
| 135 | Select this to not perform any graphics initialization at |
| 136 | romstage. |
| 137 | |
| 138 | config MAINBOARD_USE_EARLY_LIBGFXINIT |
| 139 | bool "Use libgfxinit" |
| 140 | depends on MAINBOARD_HAS_EARLY_LIBGFXINIT |
| 141 | select ROMSTAGE_VGA |
| 142 | help |
| 143 | Use the SPARK library `libgfxinit` for the romstage native |
| 144 | graphics initialization. This requires an Ada |
| 145 | toolchain. Graphics at romstage is limited to VGA text mode. |
| 146 | |
| 147 | endchoice |
| 148 | |
Paul Menzel | c4062c7 | 2021-02-11 10:43:14 +0100 | [diff] [blame] | 149 | config PRE_GRAPHICS_DELAY_MS |
Kyösti Mälkki | 0f30063 | 2020-12-19 23:43:56 +0200 | [diff] [blame] | 150 | int "Graphics initialization delay in ms" |
| 151 | default 0 |
| 152 | depends on VGA_ROM_RUN |
| 153 | help |
| 154 | On some systems, coreboot boots so fast that connected monitors |
| 155 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 156 | VBIOS. On those systems we need to wait for a bit before executing |
| 157 | the VBIOS. |
| 158 | |
Arthur Heymans | b43ec47 | 2019-03-24 20:39:45 +0100 | [diff] [blame] | 159 | config ONBOARD_VGA_IS_PRIMARY |
| 160 | bool "Use onboard VGA as primary video device" |
| 161 | default n |
| 162 | depends on PCI |
| 163 | help |
| 164 | This option lets you select which VGA device will be used |
| 165 | to decode legacy VGA cycles. Not all chipsets implement this |
| 166 | however. If not selected, the last adapter found will be used, |
| 167 | else the onboard adapter is used. |
| 168 | |
Stefan Reinauer | 0a50084 | 2011-09-23 10:33:58 -0700 | [diff] [blame] | 169 | config S3_VGA_ROM_RUN |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 170 | bool "Re-run VGA Option ROMs on S3 resume" |
Stefan Reinauer | 0a50084 | 2011-09-23 10:33:58 -0700 | [diff] [blame] | 171 | default y |
| 172 | depends on VGA_ROM_RUN && HAVE_ACPI_RESUME |
| 173 | help |
Peter Stuge | b6fa47c | 2012-10-27 13:45:51 +0200 | [diff] [blame] | 174 | Execute VGA Option ROMs in coreboot when resuming from S3 suspend. |
| 175 | |
| 176 | When using a SeaBIOS payload it runs all option ROMs with much |
| 177 | more complete BIOS interrupt services available than coreboot, |
| 178 | which some option ROMs require in order to function correctly. |
| 179 | |
| 180 | If unsure, say N when using SeaBIOS as payload, Y otherwise. |
Stefan Reinauer | 0a50084 | 2011-09-23 10:33:58 -0700 | [diff] [blame] | 181 | |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 182 | config ALWAYS_LOAD_OPROM |
| 183 | def_bool n |
| 184 | depends on VGA_ROM_RUN |
| 185 | help |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 186 | Always load option ROMs if any are found. The decision to run |
| 187 | the ROM is still determined at runtime, but the distinction |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 188 | between loading and not running comes into play for CHROMEOS. |
| 189 | |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 190 | An example where this is required is that VBT (Video BIOS Tables) |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 191 | are needed for the kernel's display driver to know how a piece of |
| 192 | hardware is configured to be used. |
| 193 | |
Aaron Durbin | 1051025 | 2018-01-30 10:04:02 -0700 | [diff] [blame] | 194 | config ALWAYS_RUN_OPROM |
| 195 | def_bool n |
| 196 | depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM |
| 197 | help |
Martin Roth | 0949e73 | 2021-10-01 14:28:22 -0600 | [diff] [blame] | 198 | Always unconditionally run the option regardless of other |
Aaron Durbin | 1051025 | 2018-01-30 10:04:02 -0700 | [diff] [blame] | 199 | policies. |
| 200 | |
Patrick Rudolph | 647e34d | 2016-02-11 08:36:50 +0100 | [diff] [blame] | 201 | config ON_DEVICE_ROM_LOAD |
| 202 | bool "Load Option ROMs on PCI devices" |
Peter Stuge | be0ede4 | 2012-10-27 14:17:04 +0200 | [diff] [blame] | 203 | default n if PAYLOAD_SEABIOS |
| 204 | default y if !PAYLOAD_SEABIOS |
Nico Huber | 49d99fc | 2017-05-20 17:56:02 +0200 | [diff] [blame] | 205 | depends on VGA_ROM_RUN |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 206 | help |
Nico Huber | 49d99fc | 2017-05-20 17:56:02 +0200 | [diff] [blame] | 207 | Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot. |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 208 | |
Peter Stuge | b6fa47c | 2012-10-27 13:45:51 +0200 | [diff] [blame] | 209 | If disabled, only Option ROMs stored in CBFS will be executed by |
| 210 | coreboot. If you are concerned about security, you might want to |
| 211 | disable this option, but it might leave your system in a state of |
| 212 | degraded functionality. |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 213 | |
Peter Stuge | b6fa47c | 2012-10-27 13:45:51 +0200 | [diff] [blame] | 214 | When using a SeaBIOS payload it runs all option ROMs with much |
| 215 | more complete BIOS interrupt services available than coreboot, |
| 216 | which some option ROMs require in order to function correctly. |
| 217 | |
| 218 | If unsure, say N when using SeaBIOS as payload, Y otherwise. |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 219 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 220 | choice |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 221 | prompt "Option ROM execution type" |
Stefan Reinauer | 14be4d0 | 2010-01-31 21:46:12 +0000 | [diff] [blame] | 222 | default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 |
| 223 | default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86 |
Arthur Heymans | 57f70a1 | 2018-12-20 10:27:19 +0100 | [diff] [blame] | 224 | depends on VGA_ROM_RUN |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 225 | |
| 226 | config PCI_OPTION_ROM_RUN_REALMODE |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 227 | prompt "Native mode" |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 228 | bool |
Arthur Heymans | e095c46 | 2022-11-12 16:21:03 +0100 | [diff] [blame] | 229 | depends on ARCH_X86 && !ARCH_RAMSTAGE_X86_64 |
Myles Watson | 28412f5 | 2009-09-17 16:54:46 +0000 | [diff] [blame] | 230 | help |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 231 | If you select this option, PCI Option ROMs will be executed |
Stefan Reinauer | 14be4d0 | 2010-01-31 21:46:12 +0000 | [diff] [blame] | 232 | natively on the CPU in real mode. No CPU emulation is involved, |
| 233 | so this is the fastest, but also the least secure option. |
| 234 | (only works on x86/x64 systems) |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 235 | |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 236 | config PCI_OPTION_ROM_RUN_YABEL |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 237 | prompt "Secure mode" |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 238 | bool |
| 239 | help |
Stefan Reinauer | 14be4d0 | 2010-01-31 21:46:12 +0000 | [diff] [blame] | 240 | If you select this option, the x86emu CPU emulator will be used to |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 241 | execute PCI Option ROMs. |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 242 | |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 243 | This option prevents Option ROMs from doing dirty tricks with the |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 244 | system (such as installing SMM modules or hypervisors), but it is |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 245 | also significantly slower than the native Option ROM initialization |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 246 | method. |
| 247 | |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 248 | This is the default choice for non-x86 systems. |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 249 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 250 | endchoice |
Uwe Hermann | 5ec2c2b | 2009-08-25 00:53:22 +0000 | [diff] [blame] | 251 | |
Stefan Reinauer | 9a35853 | 2010-02-12 09:32:17 +0000 | [diff] [blame] | 252 | config YABEL_PCI_ACCESS_OTHER_DEVICES |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 253 | prompt "Allow Option ROMs to access other devices" |
Stefan Reinauer | 9a35853 | 2010-02-12 09:32:17 +0000 | [diff] [blame] | 254 | bool |
| 255 | depends on PCI_OPTION_ROM_RUN_YABEL |
| 256 | help |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 257 | Per default, YABEL only allows Option ROMs to access the PCI device |
Stefan Reinauer | 9a35853 | 2010-02-12 09:32:17 +0000 | [diff] [blame] | 258 | that they are associated with. However, this causes trouble for some |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 259 | onboard graphics chips whose Option ROM needs to reconfigure the |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 260 | north bridge. |
Stefan Reinauer | 9a35853 | 2010-02-12 09:32:17 +0000 | [diff] [blame] | 261 | |
Patrick Georgi | c4b2a1b | 2012-07-20 13:44:50 +0200 | [diff] [blame] | 262 | config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG |
| 263 | prompt "Fake success on writing other device's config space" |
| 264 | bool |
| 265 | depends on YABEL_PCI_ACCESS_OTHER_DEVICES |
| 266 | help |
| 267 | By default, YABEL aborts when the Option ROM tries to write to other |
| 268 | devices' config spaces. With this option enabled, the write doesn't |
| 269 | follow through, but the Option ROM is allowed to go on. |
| 270 | This can create issues such as hanging Option ROMs (if it depends on |
| 271 | that other register changing to the written value), so test for |
| 272 | impact before using this option. |
| 273 | |
Stefan Reinauer | 9a35853 | 2010-02-12 09:32:17 +0000 | [diff] [blame] | 274 | config YABEL_VIRTMEM_LOCATION |
| 275 | prompt "Location of YABEL's virtual memory" |
| 276 | hex |
Alexandru Gagniuc | fdbc1af | 2015-08-26 10:11:02 -0400 | [diff] [blame] | 277 | depends on PCI_OPTION_ROM_RUN_YABEL |
Stefan Reinauer | 9a35853 | 2010-02-12 09:32:17 +0000 | [diff] [blame] | 278 | default 0x1000000 |
| 279 | help |
| 280 | YABEL requires 1MB memory for its CPU emulation. This memory is |
| 281 | normally located at 16MB. |
| 282 | |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 283 | config YABEL_DIRECTHW |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 284 | prompt "Direct hardware access" |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 285 | bool |
Stefan Reinauer | 91f1423 | 2012-12-07 16:55:12 -0800 | [diff] [blame] | 286 | depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_X86 |
Myles Watson | e680495 | 2009-08-28 14:36:12 +0000 | [diff] [blame] | 287 | help |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 288 | YABEL consists of two parts: It uses x86emu for the CPU emulation and |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 289 | additionally provides a PC system emulation that filters bad device |
| 290 | and memory access (such as PCI config space access to other devices |
| 291 | than the initialized one). |
| 292 | |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 293 | When choosing this option, x86emu will pass through all hardware |
Uwe Hermann | 548dbe7 | 2010-02-22 16:41:49 +0000 | [diff] [blame] | 294 | accesses to memory and I/O devices to the underlying memory and I/O |
Stefan Reinauer | afaa257 | 2011-10-06 16:47:51 -0700 | [diff] [blame] | 295 | addresses. While this option prevents Option ROMs from doing dirty |
Stefan Reinauer | d650e99 | 2010-02-22 04:33:13 +0000 | [diff] [blame] | 296 | tricks with the CPU (such as installing SMM modules or hypervisors), |
| 297 | they can still access all devices in the system. |
| 298 | Enable this option for a good compromise between security and speed. |
| 299 | |
Stefan Reinauer | abc0c85 | 2010-11-22 08:09:50 +0000 | [diff] [blame] | 300 | config MULTIPLE_VGA_ADAPTERS |
Myles Watson | 28412f5 | 2009-09-17 16:54:46 +0000 | [diff] [blame] | 301 | bool |
| 302 | default n |
| 303 | |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 304 | menu "Display" |
| 305 | depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER |
| 306 | |
| 307 | config FRAMEBUFFER_SET_VESA_MODE |
| 308 | prompt "Set framebuffer graphics resolution" |
| 309 | bool |
Nico Huber | 7ebb018 | 2019-07-22 18:17:40 +0200 | [diff] [blame] | 310 | default y if CHROMEOS |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 311 | depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE |
| 312 | select HAVE_VBE_LINEAR_FRAMEBUFFER |
| 313 | help |
| 314 | Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) |
| 315 | |
| 316 | if FRAMEBUFFER_SET_VESA_MODE |
| 317 | |
| 318 | choice |
| 319 | prompt "framebuffer graphics resolution" |
Mike Banon | 749fe1e | 2019-02-23 21:43:05 +0300 | [diff] [blame] | 320 | default FRAMEBUFFER_VESA_MODE_118 |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 321 | help |
| 322 | This option sets the resolution used for the coreboot framebuffer (and |
| 323 | bootsplash screen). |
| 324 | |
| 325 | config FRAMEBUFFER_VESA_MODE_100 |
| 326 | bool "640x400 256-color" |
| 327 | |
| 328 | config FRAMEBUFFER_VESA_MODE_101 |
| 329 | bool "640x480 256-color" |
| 330 | |
| 331 | config FRAMEBUFFER_VESA_MODE_102 |
| 332 | bool "800x600 16-color" |
| 333 | |
| 334 | config FRAMEBUFFER_VESA_MODE_103 |
| 335 | bool "800x600 256-color" |
| 336 | |
| 337 | config FRAMEBUFFER_VESA_MODE_104 |
| 338 | bool "1024x768 16-color" |
| 339 | |
| 340 | config FRAMEBUFFER_VESA_MODE_105 |
| 341 | bool "1024x768 256-color" |
| 342 | |
| 343 | config FRAMEBUFFER_VESA_MODE_106 |
| 344 | bool "1280x1024 16-color" |
| 345 | |
| 346 | config FRAMEBUFFER_VESA_MODE_107 |
| 347 | bool "1280x1024 256-color" |
| 348 | |
| 349 | config FRAMEBUFFER_VESA_MODE_108 |
| 350 | bool "80x60 text" |
| 351 | |
| 352 | config FRAMEBUFFER_VESA_MODE_109 |
| 353 | bool "132x25 text" |
| 354 | |
| 355 | config FRAMEBUFFER_VESA_MODE_10A |
| 356 | bool "132x43 text" |
| 357 | |
| 358 | config FRAMEBUFFER_VESA_MODE_10B |
| 359 | bool "132x50 text" |
| 360 | |
| 361 | config FRAMEBUFFER_VESA_MODE_10C |
| 362 | bool "132x60 text" |
| 363 | |
| 364 | config FRAMEBUFFER_VESA_MODE_10D |
| 365 | bool "320x200 32k-color (1:5:5:5)" |
| 366 | |
| 367 | config FRAMEBUFFER_VESA_MODE_10E |
| 368 | bool "320x200 64k-color (5:6:5)" |
| 369 | |
| 370 | config FRAMEBUFFER_VESA_MODE_10F |
| 371 | bool "320x200 16.8M-color (8:8:8)" |
| 372 | |
| 373 | config FRAMEBUFFER_VESA_MODE_110 |
| 374 | bool "640x480 32k-color (1:5:5:5)" |
| 375 | |
| 376 | config FRAMEBUFFER_VESA_MODE_111 |
| 377 | bool "640x480 64k-color (5:6:5)" |
| 378 | |
| 379 | config FRAMEBUFFER_VESA_MODE_112 |
| 380 | bool "640x480 16.8M-color (8:8:8)" |
| 381 | |
| 382 | config FRAMEBUFFER_VESA_MODE_113 |
| 383 | bool "800x600 32k-color (1:5:5:5)" |
| 384 | |
| 385 | config FRAMEBUFFER_VESA_MODE_114 |
| 386 | bool "800x600 64k-color (5:6:5)" |
| 387 | |
| 388 | config FRAMEBUFFER_VESA_MODE_115 |
| 389 | bool "800x600 16.8M-color (8:8:8)" |
| 390 | |
| 391 | config FRAMEBUFFER_VESA_MODE_116 |
| 392 | bool "1024x768 32k-color (1:5:5:5)" |
| 393 | |
| 394 | config FRAMEBUFFER_VESA_MODE_117 |
| 395 | bool "1024x768 64k-color (5:6:5)" |
| 396 | |
| 397 | config FRAMEBUFFER_VESA_MODE_118 |
| 398 | bool "1024x768 16.8M-color (8:8:8)" |
| 399 | |
| 400 | config FRAMEBUFFER_VESA_MODE_119 |
| 401 | bool "1280x1024 32k-color (1:5:5:5)" |
| 402 | |
| 403 | config FRAMEBUFFER_VESA_MODE_11A |
| 404 | bool "1280x1024 64k-color (5:6:5)" |
| 405 | |
| 406 | config FRAMEBUFFER_VESA_MODE_11B |
| 407 | bool "1280x1024 16.8M-color (8:8:8)" |
| 408 | |
| 409 | config FRAMEBUFFER_VESA_MODE_USER |
| 410 | bool "Manually select VESA mode" |
| 411 | |
| 412 | endchoice |
| 413 | |
| 414 | # Map the config names to an integer (KB). |
| 415 | config FRAMEBUFFER_VESA_MODE |
| 416 | prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER |
| 417 | hex |
| 418 | default 0x100 if FRAMEBUFFER_VESA_MODE_100 |
| 419 | default 0x101 if FRAMEBUFFER_VESA_MODE_101 |
| 420 | default 0x102 if FRAMEBUFFER_VESA_MODE_102 |
| 421 | default 0x103 if FRAMEBUFFER_VESA_MODE_103 |
| 422 | default 0x104 if FRAMEBUFFER_VESA_MODE_104 |
| 423 | default 0x105 if FRAMEBUFFER_VESA_MODE_105 |
| 424 | default 0x106 if FRAMEBUFFER_VESA_MODE_106 |
| 425 | default 0x107 if FRAMEBUFFER_VESA_MODE_107 |
| 426 | default 0x108 if FRAMEBUFFER_VESA_MODE_108 |
| 427 | default 0x109 if FRAMEBUFFER_VESA_MODE_109 |
| 428 | default 0x10A if FRAMEBUFFER_VESA_MODE_10A |
| 429 | default 0x10B if FRAMEBUFFER_VESA_MODE_10B |
| 430 | default 0x10C if FRAMEBUFFER_VESA_MODE_10C |
| 431 | default 0x10D if FRAMEBUFFER_VESA_MODE_10D |
| 432 | default 0x10E if FRAMEBUFFER_VESA_MODE_10E |
| 433 | default 0x10F if FRAMEBUFFER_VESA_MODE_10F |
| 434 | default 0x110 if FRAMEBUFFER_VESA_MODE_110 |
| 435 | default 0x111 if FRAMEBUFFER_VESA_MODE_111 |
| 436 | default 0x112 if FRAMEBUFFER_VESA_MODE_112 |
| 437 | default 0x113 if FRAMEBUFFER_VESA_MODE_113 |
| 438 | default 0x114 if FRAMEBUFFER_VESA_MODE_114 |
| 439 | default 0x115 if FRAMEBUFFER_VESA_MODE_115 |
| 440 | default 0x116 if FRAMEBUFFER_VESA_MODE_116 |
| 441 | default 0x117 if FRAMEBUFFER_VESA_MODE_117 |
| 442 | default 0x118 if FRAMEBUFFER_VESA_MODE_118 |
| 443 | default 0x119 if FRAMEBUFFER_VESA_MODE_119 |
| 444 | default 0x11A if FRAMEBUFFER_VESA_MODE_11A |
| 445 | default 0x11B if FRAMEBUFFER_VESA_MODE_11B |
Mike Banon | 749fe1e | 2019-02-23 21:43:05 +0300 | [diff] [blame] | 446 | default 0x118 if FRAMEBUFFER_VESA_MODE_USER |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 447 | endif # FRAMEBUFFER_SET_VESA_MODE |
| 448 | |
Angel Pons | 4cb2f76 | 2020-06-16 19:49:53 +0200 | [diff] [blame] | 449 | config WANT_LINEAR_FRAMEBUFFER |
| 450 | bool |
| 451 | default y if CHROMEOS |
Sean Rhodes | 38c99b5 | 2022-07-13 10:11:44 +0100 | [diff] [blame] | 452 | default y if PAYLOAD_EDK2 |
Nicholas Chin | 8d88557 | 2021-08-28 09:40:41 -0600 | [diff] [blame] | 453 | default y if COREDOOM_SECONDARY_PAYLOAD |
Angel Pons | 4cb2f76 | 2020-06-16 19:49:53 +0200 | [diff] [blame] | 454 | |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 455 | choice |
| 456 | prompt "Framebuffer mode" |
Angel Pons | 4cb2f76 | 2020-06-16 19:49:53 +0200 | [diff] [blame] | 457 | default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER |
| 458 | default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 459 | default VGA_TEXT_FRAMEBUFFER |
| 460 | |
| 461 | config VGA_TEXT_FRAMEBUFFER |
| 462 | bool "Legacy VGA text mode" |
| 463 | depends on HAVE_VGA_TEXT_FRAMEBUFFER |
| 464 | help |
| 465 | If this option is enabled, coreboot will initialize graphics in |
| 466 | legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set, |
| 467 | switch to text mode before handing control to a payload. |
| 468 | |
| 469 | config VBE_LINEAR_FRAMEBUFFER |
| 470 | bool "VESA framebuffer" |
| 471 | depends on HAVE_VBE_LINEAR_FRAMEBUFFER |
| 472 | help |
| 473 | This option keeps the framebuffer mode set after coreboot finishes |
| 474 | execution. If this option is enabled, coreboot will pass a |
| 475 | framebuffer entry in its coreboot table and the payload will need a |
| 476 | compatible driver. |
| 477 | |
| 478 | config GENERIC_LINEAR_FRAMEBUFFER |
| 479 | bool "Linear \"high-resolution\" framebuffer" |
| 480 | depends on HAVE_LINEAR_FRAMEBUFFER |
| 481 | help |
| 482 | This option enables a high-resolution, linear framebuffer. If this |
| 483 | option is enabled, coreboot will pass a framebuffer entry in its |
| 484 | coreboot table and the payload will need a compatible driver. |
| 485 | |
| 486 | endchoice |
| 487 | |
| 488 | # Workaround to have LINEAR_FRAMEBUFFER set in both cases |
| 489 | # VBE_LINEAR_FRAMEBUFFER and GENERIC_LINEAR_FRAMEBUFFER. |
| 490 | # `kconfig_lint` doesn't let us use the same name with |
| 491 | # different texts in the choice above. |
| 492 | config LINEAR_FRAMEBUFFER |
| 493 | def_bool y |
| 494 | depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER |
| 495 | |
Johanna Schander | c544a85 | 2019-07-28 09:28:33 +0200 | [diff] [blame] | 496 | config BOOTSPLASH |
| 497 | prompt "Show graphical bootsplash" |
| 498 | bool |
| 499 | depends on LINEAR_FRAMEBUFFER |
| 500 | help |
| 501 | This option shows a graphical bootsplash screen. The graphics are |
| 502 | loaded from the CBFS file bootsplash.jpg. |
| 503 | |
| 504 | You can either specify the location and file name of the |
| 505 | image in the 'General' section or add it manually to CBFS, using, |
| 506 | for example, cbfstool. |
| 507 | |
Nico Huber | 2bc892c | 2019-01-01 22:28:47 +0100 | [diff] [blame] | 508 | config LINEAR_FRAMEBUFFER_MAX_WIDTH |
| 509 | int "Maximum width in pixels" |
| 510 | depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT |
Matt DeVillier | d14461f | 2022-12-05 09:45:19 -0600 | [diff] [blame] | 511 | default 2560 if SYSTEM_TYPE_LAPTOP |
| 512 | default 3840 |
Nico Huber | 2bc892c | 2019-01-01 22:28:47 +0100 | [diff] [blame] | 513 | help |
| 514 | Set the maximum width of the framebuffer. This may help with |
| 515 | default fonts too tiny for high-resolution displays. |
| 516 | |
| 517 | config LINEAR_FRAMEBUFFER_MAX_HEIGHT |
| 518 | int "Maximum height in pixels" |
| 519 | depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT |
Matt DeVillier | d14461f | 2022-12-05 09:45:19 -0600 | [diff] [blame] | 520 | default 1600 if SYSTEM_TYPE_LAPTOP |
| 521 | default 2160 |
Nico Huber | 2bc892c | 2019-01-01 22:28:47 +0100 | [diff] [blame] | 522 | help |
| 523 | Set the maximum height of the framebuffer. This may help with |
| 524 | default fonts too tiny for high-resolution displays. |
| 525 | |
Nico Huber | a2cf686 | 2017-05-20 17:57:01 +0200 | [diff] [blame] | 526 | endmenu # "Display" |
| 527 | |
Ronald G. Minnich | 78a1667 | 2012-11-29 16:28:21 -0800 | [diff] [blame] | 528 | config PCI |
| 529 | bool |
| 530 | default n |
| 531 | |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 532 | if PCI |
| 533 | |
Nico Huber | ae81497 | 2023-05-10 18:06:27 +0200 | [diff] [blame] | 534 | config DOMAIN_RESOURCE_32BIT_LIMIT |
| 535 | hex |
| 536 | default 0xfe000000 |
| 537 | help |
| 538 | When the default pci_domain_read_resources() is used, |
| 539 | keep 32-bit memory resources below this limit. This is |
| 540 | used as a workaround for missing/wrong reservations of |
| 541 | chipset resources that usually reside above this limit. |
| 542 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 543 | config NO_ECAM_MMCONF_SUPPORT |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 544 | bool |
Kyösti Mälkki | 3d15e10 | 2016-11-29 16:46:56 +0200 | [diff] [blame] | 545 | default n |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 546 | help |
| 547 | Disable the use of the Enhanced Configuration |
| 548 | Access mechanism (ECAM) method for accessing PCI config |
| 549 | address space. |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 550 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 551 | config ECAM_MMCONF_SUPPORT |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 552 | bool |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 553 | default !NO_ECAM_MMCONF_SUPPORT |
| 554 | help |
| 555 | Enable the use of the Enhanced Configuration |
| 556 | Access mechanism (ECAM) method for accessing PCI config |
| 557 | address space. |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 558 | |
Ronald G. Minnich | 876d7e9 | 2009-08-28 14:23:38 +0000 | [diff] [blame] | 559 | config PCIX_PLUGIN_SUPPORT |
| 560 | bool |
Myles Watson | ed03556 | 2009-09-22 21:29:32 +0000 | [diff] [blame] | 561 | default y |
Ronald G. Minnich | 876d7e9 | 2009-08-28 14:23:38 +0000 | [diff] [blame] | 562 | |
Ronald G. Minnich | 876d7e9 | 2009-08-28 14:23:38 +0000 | [diff] [blame] | 563 | config CARDBUS_PLUGIN_SUPPORT |
| 564 | bool |
Myles Watson | ed03556 | 2009-09-22 21:29:32 +0000 | [diff] [blame] | 565 | default y |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 566 | |
Felix Held | bc6a690 | 2023-11-09 14:08:53 +0100 | [diff] [blame] | 567 | config AZALIA_HDA_CODEC_SUPPORT |
Andrew Wu | b7bb70d | 2013-08-12 20:07:47 +0800 | [diff] [blame] | 568 | bool |
Andrew Wu | b7bb70d | 2013-08-12 20:07:47 +0800 | [diff] [blame] | 569 | default n |
Felix Held | bc6a690 | 2023-11-09 14:08:53 +0100 | [diff] [blame] | 570 | help |
| 571 | Select this option to include the code to initialize Azalia HD audio |
| 572 | codec chips. This will also add the hda_verb.c file from the |
| 573 | mainboard directory to the build which contain the board-specific HD |
| 574 | audio codec configuration. |
Andrew Wu | b7bb70d | 2013-08-12 20:07:47 +0800 | [diff] [blame] | 575 | |
Angel Pons | b922cbb | 2021-03-22 14:21:28 +0100 | [diff] [blame] | 576 | config AZALIA_LOCK_DOWN_R_WO_GCAP |
| 577 | def_bool n |
Felix Held | bc6a690 | 2023-11-09 14:08:53 +0100 | [diff] [blame] | 578 | depends on AZALIA_HDA_CODEC_SUPPORT |
Angel Pons | b922cbb | 2021-03-22 14:21:28 +0100 | [diff] [blame] | 579 | help |
| 580 | The GCAP register is implemented as R/WO (Read / Write Once) on some |
| 581 | HD Audio controllers, such as Intel 6-series PCHs. Select this option |
| 582 | to lock down the GCAP register after deasserting the controller reset |
| 583 | bit. Locking is done by reading GCAP and writing back the read value. |
| 584 | |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 585 | config PCIEXP_PLUGIN_SUPPORT |
| 586 | bool |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 587 | default y |
| 588 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 589 | config ECAM_MMCONF_BASE_ADDRESS |
Angel Pons | 7d63878 | 2021-01-28 12:51:11 +0100 | [diff] [blame] | 590 | hex |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 591 | depends on ECAM_MMCONF_SUPPORT |
Angel Pons | 7d63878 | 2021-01-28 12:51:11 +0100 | [diff] [blame] | 592 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 593 | config ECAM_MMCONF_BUS_NUMBER |
Angel Pons | 7d63878 | 2021-01-28 12:51:11 +0100 | [diff] [blame] | 594 | int |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 595 | depends on ECAM_MMCONF_SUPPORT |
Angel Pons | 7d63878 | 2021-01-28 12:51:11 +0100 | [diff] [blame] | 596 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 597 | config ECAM_MMCONF_LENGTH |
Angel Pons | 5063287 | 2021-01-28 13:04:06 +0100 | [diff] [blame] | 598 | hex |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 599 | depends on ECAM_MMCONF_SUPPORT |
| 600 | default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64 |
| 601 | default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128 |
| 602 | default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256 |
Angel Pons | 5063287 | 2021-01-28 13:04:06 +0100 | [diff] [blame] | 603 | default 0x0 |
| 604 | |
Felix Singer | e4a7d9f | 2020-06-15 15:00:56 +0200 | [diff] [blame] | 605 | config PCI_ALLOW_BUS_MASTER |
Felix Singer | 05b883e | 2020-10-13 15:12:01 +0200 | [diff] [blame] | 606 | bool "Allow coreboot to set optional PCI bus master bits" |
Felix Singer | e4a7d9f | 2020-06-15 15:00:56 +0200 | [diff] [blame] | 607 | default y |
| 608 | help |
| 609 | For security reasons, bus mastering should be enabled as late as |
| 610 | possible. In coreboot, it's usually not necessary and payloads |
| 611 | should only enable it for devices they use. Since not all payloads |
| 612 | enable bus mastering properly yet, this option gives some sort of |
| 613 | "backwards compatibility" and is enabled by default to keep the |
| 614 | traditional behaviour for now. This is currently necessary, for |
| 615 | instance, for libpayload based payloads as the drivers don't enable |
| 616 | bus mastering for PCI bridges. |
| 617 | |
Felix Singer | 3d9fa08 | 2020-09-07 13:57:49 +0200 | [diff] [blame] | 618 | if PCI_ALLOW_BUS_MASTER |
| 619 | |
Felix Singer | 205b53e | 2020-09-07 15:21:21 +0200 | [diff] [blame] | 620 | config PCI_SET_BUS_MASTER_PCI_BRIDGES |
| 621 | bool "PCI bridges" |
| 622 | default y |
| 623 | help |
| 624 | Let coreboot configure bus mastering for PCI bridges. Enabling bus |
| 625 | mastering for a PCI bridge also allows it to forward requests from |
| 626 | downstream devices. Currently, payloads ignore this and only enable |
| 627 | bus mastering for the downstream device. Hence, this option is needed |
| 628 | for compatibility until payloads are fixed. |
| 629 | |
Felix Singer | 3d9fa08 | 2020-09-07 13:57:49 +0200 | [diff] [blame] | 630 | config PCI_ALLOW_BUS_MASTER_ANY_DEVICE |
| 631 | bool "Any devices" |
| 632 | default y |
Felix Singer | 205b53e | 2020-09-07 15:21:21 +0200 | [diff] [blame] | 633 | select PCI_SET_BUS_MASTER_PCI_BRIDGES |
Felix Singer | 3d9fa08 | 2020-09-07 13:57:49 +0200 | [diff] [blame] | 634 | help |
| 635 | Allow coreboot to enable PCI bus mastering for any device. The actual |
| 636 | selection of devices depends on the various PCI drivers in coreboot. |
| 637 | |
| 638 | endif # PCI_ALLOW_BUS_MASTER |
| 639 | |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 640 | endif # PCI |
| 641 | |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 642 | if PCIEXP_PLUGIN_SUPPORT |
| 643 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 644 | config PCIEXP_COMMON_CLOCK |
| 645 | prompt "Enable PCIe Common Clock" |
| 646 | bool |
| 647 | default n |
| 648 | help |
| 649 | Detect and enable Common Clock on PCIe links. |
| 650 | |
| 651 | config PCIEXP_ASPM |
| 652 | prompt "Enable PCIe ASPM" |
| 653 | bool |
| 654 | default n |
| 655 | help |
Jonathan Neuschäfer | 8c50e68 | 2016-12-27 16:31:28 +0100 | [diff] [blame] | 656 | Detect and enable ASPM (Active State Power Management) on PCIe links. |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 657 | |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 658 | config PCIEXP_CLK_PM |
| 659 | prompt "Enable PCIe Clock Power Management" |
| 660 | bool |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 661 | default n |
| 662 | help |
| 663 | Detect and enable Clock Power Management on PCIe. |
| 664 | |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 665 | config PCIEXP_L1_SUB_STATE |
| 666 | prompt "Enable PCIe ASPM L1 SubState" |
| 667 | bool |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 668 | depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 669 | default n |
| 670 | help |
| 671 | Detect and enable ASPM on PCIe links. |
| 672 | |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 673 | config PCIEXP_SUPPORT_RESIZABLE_BARS |
| 674 | prompt "Support PCIe Resizable BARs" |
| 675 | bool |
| 676 | depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) |
| 677 | default n |
| 678 | help |
| 679 | When enabled, this will check PCIe devices for Resizable BAR support, |
| 680 | and if found, will use this to discover the preferred BAR sizes of |
| 681 | the device in preference over the traditional moving bits method. The |
| 682 | amount of address space given out to devices in this manner (since |
| 683 | it can range up to 8 EB) can be limited with the |
| 684 | PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS Kconfig setting below. |
| 685 | |
| 686 | if PCIEXP_SUPPORT_RESIZABLE_BARS |
| 687 | |
| 688 | config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS |
| 689 | int "Bits of address space to give to Resizable BARs" |
| 690 | range 20 63 # 1 MiB - 8 EiB |
| 691 | default 29 # 512 MiB |
| 692 | help |
| 693 | This is the maximum number of bits of address space to allocate for |
| 694 | PCIe devices with resizable BARs. For instance, if a device requests |
| 695 | 30 bits of address space (1 GiB), but this field is set to 29, then |
| 696 | the device will only be allocated 29 bits worth of address space (512 |
| 697 | MiB). Valid values range from 20 (1 MiB) to 63 (8 EiB); these come |
| 698 | from the Resizable BAR portion of the PCIe spec (7.8.6). |
| 699 | |
| 700 | endif # PCIEXP_SUPPORT_RESIZABLE_BARS |
| 701 | |
Wilson Chou | c8a8695 | 2022-08-29 02:08:24 +0000 | [diff] [blame] | 702 | config PCIEXP_LANE_ERR_STAT_CLEAR |
| 703 | prompt "Enable Clear PCIe Lane Error Status" |
| 704 | bool |
| 705 | default n |
| 706 | help |
| 707 | Clear the PCIe Lane Error Status at the end of link training. |
| 708 | |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 709 | config PCIEXP_HOTPLUG |
| 710 | prompt "Enable PCIe Hotplug Support" |
| 711 | bool |
| 712 | default n |
| 713 | help |
| 714 | Allocate resources for PCIe hotplug bridges |
| 715 | |
| 716 | if PCIEXP_HOTPLUG |
| 717 | |
| 718 | config PCIEXP_HOTPLUG_BUSES |
| 719 | int "PCI Express Hotplug Buses" |
Arthur Heymans | caf27ad | 2023-04-26 09:41:54 +0200 | [diff] [blame] | 720 | default 8 |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 721 | help |
| 722 | This is the number of buses allocated for hotplug PCI express |
Arthur Heymans | caf27ad | 2023-04-26 09:41:54 +0200 | [diff] [blame] | 723 | bridges, for use by hotplugged child devices. The default is 8 |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 724 | buses. |
| 725 | |
| 726 | config PCIEXP_HOTPLUG_MEM |
| 727 | hex "PCI Express Hotplug Memory" |
| 728 | default 0x800000 |
| 729 | help |
| 730 | This is the amount of memory space, in bytes, to allocate to |
| 731 | hotplug PCI express bridges, for use by hotplugged child devices. |
| 732 | This size should be page-aligned. The default is 8 MiB. |
| 733 | |
| 734 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 735 | hex "PCI Express Hotplug Prefetch Memory" |
| 736 | default 0x10000000 |
| 737 | help |
| 738 | This is the amount of pre-fetchable memory space, in bytes, to |
| 739 | allocate to hot-plug PCI express bridges, for use by hotplugged |
| 740 | child devices. This size should be page-aligned. The default is |
| 741 | 256 MiB. |
| 742 | |
Furquan Shaikh | 32f385e | 2020-05-15 23:35:00 -0700 | [diff] [blame] | 743 | config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G |
| 744 | bool |
Furquan Shaikh | 32f385e | 2020-05-15 23:35:00 -0700 | [diff] [blame] | 745 | default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G |
| 746 | default n |
| 747 | help |
| 748 | This enables prefetch memory allocation above 4G boundary for the |
| 749 | hotplug resources. |
| 750 | |
| 751 | config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G |
| 752 | bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary" |
| 753 | default n |
| 754 | help |
| 755 | This enables prefetch memory allocation below 4G boundary for the |
| 756 | hotplug resources. |
| 757 | |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 758 | config PCIEXP_HOTPLUG_IO |
| 759 | hex "PCI Express Hotplug I/O Space" |
Arthur Heymans | caf27ad | 2023-04-26 09:41:54 +0200 | [diff] [blame] | 760 | default 0x800 |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 761 | help |
| 762 | This is the amount of I/O space to allocate to hot-plug PCI |
| 763 | express bridges, for use by hotplugged child devices. The default |
Arthur Heymans | caf27ad | 2023-04-26 09:41:54 +0200 | [diff] [blame] | 764 | is 2 KiB. |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 765 | |
| 766 | endif # PCIEXP_HOTPLUG |
| 767 | |
Kyösti Mälkki | 91bfa8e | 2016-11-20 20:39:56 +0200 | [diff] [blame] | 768 | endif # PCIEXP_PLUGIN_SUPPORT |
| 769 | |
Martin Roth | f3a6729 | 2023-01-10 09:58:46 -0700 | [diff] [blame] | 770 | config DEFAULT_SOFTWARE_CONNECTION_MANAGER |
| 771 | bool |
| 772 | help |
| 773 | select to default to using the Software Connection Manager |
| 774 | |
Sean Rhodes | 060df17 | 2022-05-21 10:39:27 +0100 | [diff] [blame] | 775 | choice |
| 776 | prompt "Connection Manager" |
Martin Roth | f3a6729 | 2023-01-10 09:58:46 -0700 | [diff] [blame] | 777 | default SOFTWARE_CONNECTION_MANAGER if DEFAULT_SOFTWARE_CONNECTION_MANAGER |
Sean Rhodes | 060df17 | 2022-05-21 10:39:27 +0100 | [diff] [blame] | 778 | default FIRMWARE_CONNECTION_MANAGER |
| 779 | help |
| 780 | Software Connection Manager doesn't work with Linux 5.13 or later, |
| 781 | resulting in TBT ports timing out. Firmware Connection Manager works |
| 782 | correctly. |
| 783 | |
| 784 | Linux patch: |
| 785 | torvalds/linux@c6da62a |
| 786 | c6da62a219d028de10f2e22e93a34c7ee2b88d03 |
| 787 | |
| 788 | config FIRMWARE_CONNECTION_MANAGER |
| 789 | bool "Firmware Connection Manager" |
| 790 | help |
| 791 | Disable SCM so that FCM can be used |
| 792 | |
| 793 | config SOFTWARE_CONNECTION_MANAGER |
| 794 | bool "Software Connection Manager" |
| 795 | help |
| 796 | Enable SCM so it's used instead of FCM. |
| 797 | |
| 798 | endchoice |
| 799 | |
Kyösti Mälkki | 4c686f2 | 2014-02-14 12:45:09 +0200 | [diff] [blame] | 800 | config EARLY_PCI_BRIDGE |
| 801 | bool "Early PCI bridge" |
| 802 | depends on PCI |
| 803 | default n |
| 804 | help |
| 805 | While coreboot is executing code from ROM, the coreboot resource |
| 806 | allocator has not been running yet. Hence PCI devices living behind |
| 807 | a bridge are not yet visible to the system. |
| 808 | |
| 809 | This option enables static configuration for a single pre-defined |
| 810 | PCI bridge function on bus 0. |
| 811 | |
| 812 | if EARLY_PCI_BRIDGE |
| 813 | |
| 814 | config EARLY_PCI_BRIDGE_DEVICE |
| 815 | hex "bridge device" |
| 816 | default 0x0 |
| 817 | |
| 818 | config EARLY_PCI_BRIDGE_FUNCTION |
| 819 | hex "bridge function" |
| 820 | default 0x0 |
| 821 | |
| 822 | config EARLY_PCI_MMIO_BASE |
| 823 | hex "MMIO window base" |
| 824 | default 0x0 |
| 825 | |
| 826 | endif # EARLY_PCI_BRIDGE |
| 827 | |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 828 | config SUBSYSTEM_VENDOR_ID |
| 829 | hex "Override PCI Subsystem Vendor ID" |
| 830 | depends on PCI |
Martin Roth | 3b87812 | 2016-09-30 14:43:01 -0600 | [diff] [blame] | 831 | default 0x0000 |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 832 | help |
| 833 | This config option will override the devicetree settings for |
| 834 | PCI Subsystem Vendor ID. |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 835 | |
Michael Niewöhner | e0d749c | 2020-09-18 03:12:00 +0200 | [diff] [blame] | 836 | Note: This option is not meant for a board's Kconfig; use the |
| 837 | devicetree setting `subsystemid` instead. |
| 838 | |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 839 | config SUBSYSTEM_DEVICE_ID |
| 840 | hex "Override PCI Subsystem Device ID" |
| 841 | depends on PCI |
Martin Roth | 3b87812 | 2016-09-30 14:43:01 -0600 | [diff] [blame] | 842 | default 0x0000 |
Stefan Reinauer | 58470e3 | 2014-10-17 13:08:36 +0200 | [diff] [blame] | 843 | help |
| 844 | This config option will override the devicetree settings for |
| 845 | PCI Subsystem Device ID. |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 846 | |
Michael Niewöhner | e0d749c | 2020-09-18 03:12:00 +0200 | [diff] [blame] | 847 | Note: This option is not meant for a board's Kconfig; use the |
| 848 | devicetree setting `subsystemid` instead. |
| 849 | |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 850 | config VGA_BIOS |
| 851 | bool "Add a VGA BIOS image" |
Vladimir Serbinenko | d51a089 | 2016-03-04 09:20:20 +0100 | [diff] [blame] | 852 | depends on ARCH_X86 |
Subrata Banik | af03936 | 2020-12-30 16:09:56 +0530 | [diff] [blame] | 853 | select VGA_ROM_RUN_DEFAULT |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 854 | help |
| 855 | Select this option if you have a VGA BIOS image that you would |
| 856 | like to add to your ROM. |
| 857 | |
| 858 | You will be able to specify the location and file name of the |
| 859 | image later. |
| 860 | |
| 861 | config VGA_BIOS_FILE |
| 862 | string "VGA BIOS path and filename" |
| 863 | depends on VGA_BIOS |
| 864 | default "vgabios.bin" |
| 865 | help |
| 866 | The path and filename of the file to use as VGA BIOS. |
| 867 | |
| 868 | config VGA_BIOS_ID |
| 869 | string "VGA device PCI IDs" |
| 870 | depends on VGA_BIOS |
| 871 | default "1106,3230" |
| 872 | help |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 873 | The comma-separated PCI vendor and device ID with optional revision if that |
| 874 | feature is enabled that would associate your vBIOS to your video card. |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 875 | |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 876 | Example: 1106,3230 or 1106,3230,a3 |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 877 | |
| 878 | In the above example 1106 is the PCI vendor ID (in hex, but without |
| 879 | the "0x" prefix) and 3230 specifies the PCI device ID of the |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 880 | video card (also in hex, without "0x" prefix). a3 specifies the revision. |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 881 | |
Felix Held | 337deb6 | 2023-03-08 18:16:56 +0100 | [diff] [blame] | 882 | This ID needs to match the PCI VID and DID in the VGA BIOS file's |
| 883 | header and also needs to match the value returned by map_oprom_vendev |
| 884 | or map_oprom_vendev_rev if the remapping feature is used. |
| 885 | |
Daniele Forsi | f2fb7d9 | 2014-07-17 11:59:41 +0200 | [diff] [blame] | 886 | Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. |
| 887 | |
Martin Roth | 4cc2cac | 2019-12-06 19:11:08 -0700 | [diff] [blame] | 888 | config VGA_BIOS_SECOND |
| 889 | bool "Add a 2nd video BIOS image" |
| 890 | depends on ARCH_X86 && VGA_BIOS |
| 891 | help |
| 892 | Select this option if you have a 2nd video BIOS image that you would |
| 893 | like to add to your ROM. |
| 894 | |
| 895 | config VGA_BIOS_SECOND_FILE |
| 896 | string "2nd video BIOS path and filename" |
| 897 | depends on VGA_BIOS_SECOND |
| 898 | default "vbios2.bin" |
| 899 | help |
| 900 | The path and filename of the file to use as video BIOS. |
| 901 | |
| 902 | config VGA_BIOS_SECOND_ID |
| 903 | string "Graphics device PCI IDs" |
| 904 | depends on VGA_BIOS_SECOND |
| 905 | help |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 906 | The comma-separated PCI vendor and device ID with optional revision if that |
| 907 | feature is enabled that would associate your vBIOS to your video card. |
Martin Roth | 4cc2cac | 2019-12-06 19:11:08 -0700 | [diff] [blame] | 908 | |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 909 | Example: 1106,3230 or 1106,3230,a3 |
Martin Roth | 4cc2cac | 2019-12-06 19:11:08 -0700 | [diff] [blame] | 910 | |
| 911 | In the above example 1106 is the PCI vendor ID (in hex, but without |
| 912 | the "0x" prefix) and 3230 specifies the PCI device ID of the |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 913 | video card (also in hex, without "0x" prefix). a3 specifies the revision. |
Martin Roth | 4cc2cac | 2019-12-06 19:11:08 -0700 | [diff] [blame] | 914 | |
| 915 | Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. |
| 916 | |
Martin Roth | a616a4b | 2020-01-21 09:28:40 -0700 | [diff] [blame] | 917 | config CHECK_REV_IN_OPROM_NAME |
| 918 | def_bool n |
| 919 | help |
| 920 | Select this in the platform BIOS or chipset if the option rom has a revision |
| 921 | that needs to be checked when searching CBFS. |
| 922 | |
Mike Banon | 0f8547e | 2019-02-17 19:51:53 +0300 | [diff] [blame] | 923 | config VGA_BIOS_DGPU |
| 924 | bool "Add a discrete VGA BIOS image" |
| 925 | depends on VGA_BIOS |
| 926 | help |
| 927 | Select this option if you have a VGA BIOS image for discrete GPU |
| 928 | that you would like to add to your ROM. |
| 929 | |
| 930 | You will be able to specify the location and file name of the |
| 931 | image later. |
| 932 | |
| 933 | config VGA_BIOS_DGPU_FILE |
| 934 | string "Discrete VGA BIOS path and filename" |
| 935 | depends on VGA_BIOS_DGPU |
| 936 | default "vgabios_dgpu.bin" |
| 937 | help |
| 938 | The path and filename of the file to use as VGA BIOS for discrete GPU. |
| 939 | |
| 940 | config VGA_BIOS_DGPU_ID |
| 941 | string "Discrete VGA device PCI IDs" |
| 942 | depends on VGA_BIOS_DGPU |
| 943 | default "1002,6663" |
| 944 | help |
| 945 | The comma-separated PCI vendor and device ID that would associate |
| 946 | your VGA BIOS to your discrete video card. |
| 947 | |
| 948 | Examples: |
| 949 | 1002,6663 for HD 8570M |
| 950 | 1002,6665 for R5 M230 |
| 951 | |
| 952 | In the above examples 1002 is the PCI vendor ID (in hex, but without |
| 953 | the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the |
| 954 | discrete video card (also in hex, without "0x" prefix). |
| 955 | |
| 956 | Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. |
| 957 | |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 958 | config INTEL_GMA_HAVE_VBT |
Arthur Heymans | 7225a36 | 2018-05-28 21:09:21 +0200 | [diff] [blame] | 959 | bool |
| 960 | help |
| 961 | Select this in the mainboard Kconfig to indicate the board has |
| 962 | a data.vbt file. |
| 963 | |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 964 | config INTEL_GMA_ADD_VBT |
Patrick Rudolph | 4c17098 | 2017-07-17 19:53:56 +0200 | [diff] [blame] | 965 | depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON |
Elyes HAOUAS | 6dc9d03 | 2020-02-16 16:22:52 +0100 | [diff] [blame] | 966 | bool "Add a Video BIOS Table (VBT) binary to CBFS" |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 967 | default y if INTEL_GMA_HAVE_VBT |
Patrick Rudolph | 4c17098 | 2017-07-17 19:53:56 +0200 | [diff] [blame] | 968 | help |
| 969 | Add a VBT data file to CBFS. The VBT describes the integrated |
| 970 | GPU and connections, and is needed by the GOP driver integrated into |
| 971 | FSP and the OS driver in order to initialize the display. |
| 972 | |
| 973 | config INTEL_GMA_VBT_FILE |
| 974 | string "VBT binary path and filename" |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 975 | depends on INTEL_GMA_ADD_VBT |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 976 | default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(VARIANT_DIR)/data.vbt" \ |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 977 | if INTEL_GMA_HAVE_VBT && VARIANT_DIR != "" |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 978 | default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if INTEL_GMA_HAVE_VBT |
| 979 | default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vbt.bin" |
Patrick Rudolph | 4c17098 | 2017-07-17 19:53:56 +0200 | [diff] [blame] | 980 | help |
| 981 | The path and filename of the VBT binary. |
| 982 | |
Julius Werner | 37d7ac8 | 2014-05-05 18:03:46 -0700 | [diff] [blame] | 983 | config SOFTWARE_I2C |
| 984 | bool "Enable I2C controller emulation in software" |
| 985 | default n |
| 986 | help |
| 987 | This config option will enable code to override the i2c_transfer |
| 988 | routine with a (simple) software emulation of the protocol. This may |
| 989 | be useful for debugging or on platforms where a driver for the real |
| 990 | I2C controller is not (yet) available. The platform code needs to |
| 991 | provide bindings to manually toggle I2C lines. |
Kyösti Mälkki | a91e1e6 | 2014-12-31 10:36:08 +0200 | [diff] [blame] | 992 | |
Jes Klinke | 19baa9d | 2022-02-22 16:00:09 -0800 | [diff] [blame] | 993 | config I2C_TRANSFER_TIMEOUT_US |
| 994 | int "I2C transfer timeout in microseconds" |
| 995 | default 500000 |
| 996 | help |
| 997 | Timeout for a read/write transfers on the I2C bus, that is, the |
| 998 | maximum time a device could stretch clock bits before the transfer |
| 999 | is aborted and an error returned. |
| 1000 | |
Nico Huber | 526c642 | 2020-05-25 00:03:14 +0200 | [diff] [blame] | 1001 | config RESOURCE_ALLOCATION_TOP_DOWN |
Nico Huber | a959f0a | 2023-07-07 13:56:21 +0200 | [diff] [blame] | 1002 | bool "Allocate resources from top down" |
| 1003 | default n if PAYLOAD_EDK2 |
| 1004 | default y |
Nico Huber | 21ddf55 | 2022-09-04 21:58:03 +0200 | [diff] [blame] | 1005 | help |
Nico Huber | 5226301 | 2020-05-23 19:15:36 +0200 | [diff] [blame] | 1006 | Top-down allocation is required to place resources above 4G by |
| 1007 | default (i.e. even when there is still space below). On some |
| 1008 | platforms, it might make a difference because of conflicts with |
Nico Huber | a959f0a | 2023-07-07 13:56:21 +0200 | [diff] [blame] | 1009 | undeclared resources. EDK2 is currently reported to also have |
| 1010 | problems on some platforms, at least with Intel's IGD. |
Nico Huber | 526c642 | 2020-05-25 00:03:14 +0200 | [diff] [blame] | 1011 | |
Raul E Rangel | a5b7ddf | 2020-05-29 17:16:20 -0600 | [diff] [blame] | 1012 | config XHCI_UTILS |
| 1013 | def_bool n |
| 1014 | help |
| 1015 | Provides xHCI utility functions. |
| 1016 | |
Sean Rhodes | aa8c6a2 | 2023-04-13 12:15:38 +0100 | [diff] [blame] | 1017 | config D3COLD_SUPPORT |
| 1018 | bool |
| 1019 | default y |
| 1020 | help |
| 1021 | Enable this option if all devices on your system support the |
| 1022 | D3Cold power management state. The D3Cold state is a low-power |
| 1023 | state where the device has been powered down and is no longer |
| 1024 | able to maintain its context. This state can help reduce |
| 1025 | overall system power consumption, which can be beneficial for |
| 1026 | energy savings and thermal management. |
| 1027 | |
| 1028 | Please note that enabling D3Cold support may break system |
| 1029 | suspend-to-RAM (S3) functionality. |
| 1030 | |
Martin Roth | a666af7 | 2022-10-29 13:27:22 -0600 | [diff] [blame] | 1031 | source "src/device/dram/Kconfig" |
| 1032 | |
Stefan Reinauer | 95a6396 | 2012-11-13 17:00:01 -0800 | [diff] [blame] | 1033 | endmenu |