Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 6 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/chip.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <delay.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 12 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 13 | #include "raminit_native.h" |
| 14 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 15 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 16 | #include "sandybridge.h" |
| 17 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 18 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 19 | |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame^] | 20 | /* Number of programmed IOSAV subsequences. */ |
| 21 | static unsigned int ssq_count = 0; |
| 22 | |
| 23 | static void iosav_write_ssq(const int ch, const int n, const struct iosav_ssq *ssq) |
| 24 | { |
| 25 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; |
| 26 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; |
| 27 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; |
| 28 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; |
| 29 | |
| 30 | ssq_count++; |
| 31 | } |
| 32 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 33 | /* length: [1..4] */ |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 34 | static void iosav_run_queue(const int ch, const u8 loops, const u8 length, const u8 as_timer) |
| 35 | { |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame^] | 36 | MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); |
| 37 | |
| 38 | ssq_count = 0; |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 39 | } |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 40 | |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 41 | static void iosav_run_once(const int ch, const u8 length) |
| 42 | { |
| 43 | iosav_run_queue(ch, 1, length, 0); |
| 44 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 45 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 46 | static void sfence(void) |
| 47 | { |
| 48 | asm volatile ("sfence"); |
| 49 | } |
| 50 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 51 | /* Toggle IO reset bit */ |
| 52 | static void toggle_io_reset(void) |
| 53 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 54 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 55 | MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 56 | udelay(1); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 57 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 58 | udelay(1); |
| 59 | } |
| 60 | |
| 61 | static u32 get_XOVER_CLK(u8 rankmap) |
| 62 | { |
| 63 | return rankmap << 24; |
| 64 | } |
| 65 | |
| 66 | static u32 get_XOVER_CMD(u8 rankmap) |
| 67 | { |
| 68 | u32 reg; |
| 69 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 70 | /* Enable xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 71 | reg = 0x4000; |
| 72 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 73 | /* Enable xover ctl */ |
| 74 | if (rankmap & 0x03) |
| 75 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 76 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 77 | if (rankmap & 0x0c) |
| 78 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 79 | |
| 80 | return reg; |
| 81 | } |
| 82 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 83 | /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 84 | u8 get_CWL(u32 tCK) |
| 85 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 86 | /* Get CWL based on tCK using the following rule */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 87 | switch (tCK) { |
| 88 | case TCK_1333MHZ: |
| 89 | return 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 90 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 91 | case TCK_1200MHZ: |
| 92 | case TCK_1100MHZ: |
| 93 | return 11; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 94 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 95 | case TCK_1066MHZ: |
| 96 | case TCK_1000MHZ: |
| 97 | return 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 98 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 99 | case TCK_933MHZ: |
| 100 | case TCK_900MHZ: |
| 101 | return 9; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 102 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 103 | case TCK_800MHZ: |
| 104 | case TCK_700MHZ: |
| 105 | return 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 106 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 107 | case TCK_666MHZ: |
| 108 | return 7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 109 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 110 | case TCK_533MHZ: |
| 111 | return 6; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 112 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 113 | default: |
| 114 | return 5; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | void dram_find_common_params(ramctr_timing *ctrl) |
| 119 | { |
| 120 | size_t valid_dimms; |
| 121 | int channel, slot; |
| 122 | dimm_info *dimms = &ctrl->info; |
| 123 | |
| 124 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 125 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 126 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 127 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 128 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 129 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 130 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 131 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 132 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 133 | valid_dimms++; |
| 134 | |
| 135 | /* Find all possible CAS combinations */ |
| 136 | ctrl->cas_supported &= dimm->cas_supported; |
| 137 | |
| 138 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 139 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 140 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 141 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 142 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 143 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 144 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 145 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 146 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 147 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 148 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 149 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 150 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 151 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 155 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 156 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 157 | if (!valid_dimms) |
| 158 | die("No valid DIMMs found"); |
| 159 | } |
| 160 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 161 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 162 | { |
| 163 | u32 reg; |
| 164 | int channel; |
| 165 | |
| 166 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 167 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 168 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 169 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 170 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 171 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 172 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 173 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 174 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 175 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 179 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 180 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 181 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 182 | |
| 183 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 184 | /* |
| 185 | * ODT stretch: |
| 186 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 187 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 188 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 189 | if (stretch == 2) |
| 190 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 191 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 192 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 193 | MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); |
| 194 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 195 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 196 | addr = TC_OTHP_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 197 | MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 198 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 199 | } |
| 200 | } |
| 201 | |
| 202 | void dram_timing_regs(ramctr_timing *ctrl) |
| 203 | { |
| 204 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 205 | int channel; |
| 206 | |
| 207 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 208 | /* BIN parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 209 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 210 | reg |= (ctrl->tRCD << 0); |
| 211 | reg |= (ctrl->tRP << 4); |
| 212 | reg |= (ctrl->CAS << 8); |
| 213 | reg |= (ctrl->CWL << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 214 | reg |= (ctrl->tRAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 215 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); |
| 216 | MCHBAR32(TC_DBP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 217 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 218 | /* Regular access parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 219 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 220 | reg |= (ctrl->tRRD << 0); |
| 221 | reg |= (ctrl->tRTP << 4); |
| 222 | reg |= (ctrl->tCKE << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 223 | reg |= (ctrl->tWTR << 12); |
| 224 | reg |= (ctrl->tFAW << 16); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 225 | reg |= (ctrl->tWR << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 226 | reg |= (3 << 30); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 227 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); |
| 228 | MCHBAR32(TC_RAP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 229 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 230 | /* Other parameters */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 231 | addr = TC_OTHP_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 232 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | reg |= (ctrl->tXPDLL << 0); |
| 234 | reg |= (ctrl->tXP << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 235 | reg |= (ctrl->tAONPD << 8); |
| 236 | reg |= 0xa0000; |
| 237 | printram("OTHP [%x] = %x\n", addr, reg); |
| 238 | MCHBAR32(addr) = reg; |
| 239 | |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 240 | /* Debug parameters - only applies to Ivy Bridge */ |
| 241 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 242 | reg = 0; |
| 243 | |
| 244 | /* |
| 245 | * If tXP and tXPDLL are very high, we need to increase them by one. |
| 246 | * This can only happen on Ivy Bridge, and when overclocking the RAM. |
| 247 | */ |
| 248 | if (ctrl->tXP >= 8) |
| 249 | reg |= (1 << 12); |
| 250 | |
| 251 | if (ctrl->tXPDLL >= 32) |
| 252 | reg |= (1 << 13); |
| 253 | |
| 254 | MCHBAR32(TC_DTP_ch(channel)) = reg; |
| 255 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 256 | |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 257 | MCHBAR32_OR(addr, 0x00020000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 258 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 259 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 260 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 261 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 262 | * TC-Refresh timing parameters: |
| 263 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 264 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 265 | */ |
| 266 | val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 267 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 268 | reg = ((ctrl->tREFI & 0xffff) << 0) | |
| 269 | ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); |
| 270 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 271 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); |
| 272 | MCHBAR32(TC_RFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 273 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 274 | MCHBAR32_OR(TC_RFP_ch(channel), 0xff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 275 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 276 | /* Self-refresh timing parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 277 | reg = 0; |
| 278 | val32 = tDLLK; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 279 | reg = (reg & ~0x00000fff) | (val32 << 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 280 | val32 = ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 281 | reg = (reg & ~0x0000f000) | (val32 << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 282 | val32 = tDLLK - ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 283 | reg = (reg & ~0x03ff0000) | (val32 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 284 | val32 = ctrl->tMOD - 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 285 | reg = (reg & ~0xf0000000) | (val32 << 28); |
| 286 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 287 | MCHBAR32(TC_SRFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 288 | } |
| 289 | } |
| 290 | |
| 291 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 292 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 293 | int channel; |
| 294 | dimm_info *info = &ctrl->info; |
| 295 | |
| 296 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 297 | dimm_attr *dimmA, *dimmB; |
| 298 | u32 reg = 0; |
| 299 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 300 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 301 | dimmA = &info->dimm[channel][0]; |
| 302 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 303 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 304 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 305 | dimmA = &info->dimm[channel][1]; |
| 306 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 307 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 308 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 309 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 310 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 311 | reg |= (dimmA->size_mb / 256) << 0; |
| 312 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 313 | reg |= (dimmA->width / 8 - 1) << 19; |
| 314 | } |
| 315 | |
| 316 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 317 | reg |= (dimmB->size_mb / 256) << 8; |
| 318 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 319 | reg |= (dimmB->width / 8 - 1) << 20; |
| 320 | } |
| 321 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 322 | reg |= 1 << 21; /* Rank interleave */ |
| 323 | reg |= 1 << 22; /* Enhanced interleave */ |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 324 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 325 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 326 | ctrl->mad_dimm[channel] = reg; |
| 327 | } else { |
| 328 | ctrl->mad_dimm[channel] = 0; |
| 329 | } |
| 330 | } |
| 331 | } |
| 332 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 333 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 334 | { |
| 335 | int channel; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 336 | u32 ecc; |
| 337 | |
| 338 | if (ctrl->ecc_enabled) |
| 339 | ecc = training ? (1 << 24) : (3 << 24); |
| 340 | else |
| 341 | ecc = 0; |
| 342 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 343 | FOR_ALL_CHANNELS { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 344 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 345 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 346 | |
| 347 | //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 348 | } |
| 349 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 350 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 351 | { |
| 352 | u32 reg, ch0size, ch1size; |
| 353 | u8 val; |
| 354 | reg = 0; |
| 355 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 356 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 357 | if (training) { |
| 358 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 359 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 360 | } else { |
| 361 | ch0size = ctrl->channel_size_mb[0]; |
| 362 | ch1size = ctrl->channel_size_mb[1]; |
| 363 | } |
| 364 | |
| 365 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 366 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 367 | val = ch1size / 256; |
| 368 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 369 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 370 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 371 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 372 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 373 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 374 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 375 | val = ch0size / 256; |
| 376 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 377 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 378 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 379 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 380 | } |
| 381 | } |
| 382 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 383 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 384 | |
| 385 | static unsigned int get_mmio_size(void) |
| 386 | { |
| 387 | const struct device *dev; |
| 388 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 389 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 390 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 391 | if (dev) |
| 392 | cfg = dev->chip_info; |
| 393 | |
| 394 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 395 | if (!cfg || cfg->pci_mmio_size == 0) |
| 396 | return DEFAULT_PCI_MMIO_SIZE; |
| 397 | else |
| 398 | return cfg->pci_mmio_size; |
| 399 | } |
| 400 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 401 | /* |
| 402 | * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. |
| 403 | * The ME/PCU/.. has the ability to change this. |
| 404 | * Return 0: ECC is optional |
| 405 | * Return 1: ECC is forced |
| 406 | */ |
| 407 | bool get_host_ecc_forced(void) |
| 408 | { |
| 409 | /* read Capabilities A Register */ |
| 410 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 411 | return !!(reg32 & (1 << 24)); |
| 412 | } |
| 413 | |
| 414 | /* |
| 415 | * Returns the ECC capability. |
| 416 | * The ME/PCU/.. has the ability to change this. |
| 417 | * Return 0: ECC is disabled |
| 418 | * Return 1: ECC is possible |
| 419 | */ |
| 420 | bool get_host_ecc_cap(void) |
| 421 | { |
| 422 | /* read Capabilities A Register */ |
| 423 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 424 | return !(reg32 & (1 << 25)); |
| 425 | } |
| 426 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 427 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 428 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 429 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 430 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 431 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 432 | uint16_t ggc; |
| 433 | |
| 434 | mmiosize = get_mmio_size(); |
| 435 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 436 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 437 | if (!(ggc & 2)) { |
| 438 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 439 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 440 | } else { |
| 441 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 442 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 446 | |
| 447 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 448 | |
| 449 | mestolenbase = tom - me_uma_size; |
| 450 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 451 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 452 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 453 | gfxstolenbase = toludbase - gfxstolen; |
| 454 | gttbase = gfxstolenbase - gttsize; |
| 455 | |
| 456 | tsegbase = gttbase - tsegsize; |
| 457 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 458 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 459 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 460 | tsegbase &= ~(tsegsize - 1); |
| 461 | |
| 462 | gttbase -= tsegbasedelta; |
| 463 | gfxstolenbase -= tsegbasedelta; |
| 464 | toludbase -= tsegbasedelta; |
| 465 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 466 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 467 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 468 | /* Reclaim is possible */ |
| 469 | reclaim = 1; |
| 470 | remapbase = MAX(4096, tom - me_uma_size); |
| 471 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 472 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 473 | } else { |
| 474 | // Reclaim not possible |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 475 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 476 | touudbase = tom - me_uma_size; |
| 477 | } |
| 478 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 479 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 480 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 481 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 482 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 483 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 484 | val = tom & 0xfff; |
| 485 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 486 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 487 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 488 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 489 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 490 | val = tom & 0xfffff000; |
| 491 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 492 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 493 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 494 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 495 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 496 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 497 | val = toludbase & 0xfff; |
| 498 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 499 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 500 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 501 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 502 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 503 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 504 | val = touudbase & 0xfff; |
| 505 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 506 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 507 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 508 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 509 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 510 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 511 | val = touudbase & 0xfffff000; |
| 512 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 513 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 514 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 515 | |
| 516 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 517 | /* REMAP BASE */ |
| 518 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 519 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 520 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 521 | /* REMAP LIMIT */ |
| 522 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 523 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 524 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 525 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 526 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 527 | val = tsegbase & 0xfff; |
| 528 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 529 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 530 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 531 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 532 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 533 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 534 | val = gfxstolenbase & 0xfff; |
| 535 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 536 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 537 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 538 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 539 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 540 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 541 | val = gttbase & 0xfff; |
| 542 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 543 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 544 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 545 | |
| 546 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 547 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 548 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 549 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 550 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 551 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 552 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 553 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 554 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 555 | val = mestolenbase & 0xfff; |
| 556 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 557 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 558 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 559 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 560 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 561 | val = mestolenbase & 0xfffff000; |
| 562 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 563 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 564 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 565 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 567 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 568 | val = (0x80000 - me_uma_size) & 0xfff; |
| 569 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 570 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 571 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 572 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 573 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 574 | } |
| 575 | } |
| 576 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 577 | static void wait_for_iosav(int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 578 | { |
| 579 | while (1) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 580 | if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 581 | return; |
| 582 | } |
| 583 | } |
| 584 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 585 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 586 | { |
| 587 | int channel, slotrank; |
| 588 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 589 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 590 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 591 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 592 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 593 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 594 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 595 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 596 | |
| 597 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 598 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 599 | IOSAV_ZQCS, 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 600 | 1, 3, 8, SSQ_NA, |
| 601 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 602 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 603 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 604 | /* |
| 605 | * Execute command queue - why is bit 22 set here?! |
| 606 | * |
| 607 | * This is actually using the IOSAV state machine as a timer, so refresh is allowed. |
| 608 | */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 609 | iosav_run_queue(channel, 1, 1, true); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 610 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 611 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 612 | } |
| 613 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 614 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 615 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 616 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 617 | int channel; |
| 618 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 619 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 620 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 621 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 622 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 623 | } while ((reg & 0x14) == 0); |
| 624 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 625 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 626 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 627 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 628 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 629 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 630 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 631 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 632 | /* Assert DIMM reset signal */ |
| 633 | MCHBAR32_AND(MC_INIT_STATE_G, ~2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 634 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 635 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 636 | udelay(200); |
| 637 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 638 | /* Deassert DIMM reset signal */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 639 | MCHBAR32_OR(MC_INIT_STATE_G, 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 640 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 641 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 642 | udelay(500); |
| 643 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 644 | /* Enable DCLK */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 645 | MCHBAR32_OR(MC_INIT_STATE_G, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 646 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 647 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 648 | udelay(1); |
| 649 | |
| 650 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 651 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 652 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 653 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 654 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 655 | /* Wait 10ns for ranks to settle */ |
| 656 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 657 | |
| 658 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 659 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 660 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 661 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 662 | write_reset(ctrl); |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) |
| 667 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 668 | /* Get ODT based on rankmap */ |
| 669 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 670 | |
| 671 | if (dimms_per_ch == 1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 672 | return (const odtmap){60, 60}; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 673 | } else { |
| 674 | return (const odtmap){120, 30}; |
| 675 | } |
| 676 | } |
| 677 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 678 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 679 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 680 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 681 | |
| 682 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 683 | /* DDR3 Rank1 Address mirror |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 684 | swap the following pins: |
| 685 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 686 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 687 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | /* DRAM command MRS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 691 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 692 | IOSAV_MRS, 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 693 | 1, 4, 4, SSQ_NA, |
| 694 | val, 6, reg, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 695 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 696 | |
| 697 | /* DRAM command MRS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 698 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 699 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 700 | 1, 4, 4, SSQ_NA, |
| 701 | val, 6, reg, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 702 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 703 | |
| 704 | /* DRAM command MRS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 705 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 706 | IOSAV_MRS, 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 707 | 1, 4, ctrl->tMOD, SSQ_NA, |
| 708 | val, 6, reg, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 709 | 0, 0, 0, 0, 0, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 710 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 711 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 712 | iosav_run_once(channel, 3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 713 | } |
| 714 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 715 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 716 | { |
| 717 | u16 mr0reg, mch_cas, mch_wr; |
| 718 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 719 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 720 | |
| 721 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 722 | mr0reg = 0x100; |
| 723 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 724 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 725 | if (ctrl->CAS < 12) { |
| 726 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 727 | } else { |
| 728 | mch_cas = (u16) (ctrl->CAS - 12); |
| 729 | mch_cas = ((mch_cas << 1) | 0x1); |
| 730 | } |
| 731 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 732 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 733 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 734 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 735 | mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); |
| 736 | mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); |
| 737 | mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 738 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 739 | /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ |
| 740 | mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 741 | return mr0reg; |
| 742 | } |
| 743 | |
| 744 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 745 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 746 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | static u32 encode_odt(u32 odt) |
| 750 | { |
| 751 | switch (odt) { |
| 752 | case 30: |
| 753 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 754 | case 60: |
| 755 | return (1 << 2); // RZQ/4 |
| 756 | case 120: |
| 757 | return (1 << 6); // RZQ/2 |
| 758 | default: |
| 759 | case 0: |
| 760 | return 0; |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 765 | { |
| 766 | odtmap odt; |
| 767 | u32 mr1reg; |
| 768 | |
| 769 | odt = get_ODT(ctrl, rank, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 770 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 771 | |
| 772 | mr1reg |= encode_odt(odt.rttnom); |
| 773 | |
| 774 | return mr1reg; |
| 775 | } |
| 776 | |
| 777 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 778 | { |
| 779 | u16 mr1reg; |
| 780 | |
| 781 | mr1reg = make_mr1(ctrl, rank, channel); |
| 782 | |
| 783 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 784 | } |
| 785 | |
| 786 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 787 | { |
| 788 | u16 pasr, cwl, mr2reg; |
| 789 | odtmap odt; |
| 790 | int srt; |
| 791 | |
| 792 | pasr = 0; |
| 793 | cwl = ctrl->CWL - 5; |
| 794 | odt = get_ODT(ctrl, rank, channel); |
| 795 | |
| 796 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
| 797 | |
| 798 | mr2reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 799 | mr2reg = (mr2reg & ~0x07) | pasr; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 800 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 801 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 802 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 803 | mr2reg |= (odt.rttwr / 60) << 9; |
| 804 | |
| 805 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
| 806 | } |
| 807 | |
| 808 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 809 | { |
| 810 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 811 | } |
| 812 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 813 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 814 | { |
| 815 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 816 | int channel; |
| 817 | |
| 818 | FOR_ALL_POPULATED_CHANNELS { |
| 819 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 820 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 821 | dram_mr2(ctrl, slotrank, channel); |
| 822 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 823 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 824 | dram_mr3(ctrl, slotrank, channel); |
| 825 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 826 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 827 | dram_mr1(ctrl, slotrank, channel); |
| 828 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 829 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 830 | dram_mr0(ctrl, slotrank, channel); |
| 831 | } |
| 832 | } |
| 833 | |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 834 | /* DRAM command NOP (without ODT nor chip selects) */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 835 | IOSAV_SUBSEQUENCE(BROADCAST_CH, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 836 | IOSAV_NOP & ~(0xff << 8), 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 837 | 1, 4, 15, SSQ_NA, |
| 838 | 2, 6, 0, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 839 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 840 | |
| 841 | /* DRAM command ZQCL */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 842 | IOSAV_SUBSEQUENCE(BROADCAST_CH, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 843 | IOSAV_ZQCS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 844 | 1, 4, 400, SSQ_NA, |
| 845 | 1024, 6, 0, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 846 | 0, 0, 0, 1, 20, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 847 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 848 | /* Execute command queue on all channels. Do it four times. */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 849 | iosav_run_queue(BROADCAST_CH, 4, 2, false); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 850 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 851 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 852 | /* Wait for ref drained */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 853 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 854 | } |
| 855 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 856 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 857 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 858 | |
| 859 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 860 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 861 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 862 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 863 | |
| 864 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 865 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 866 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 867 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 868 | |
| 869 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 870 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 871 | IOSAV_ZQCS, 0, |
Angel Pons | 2be5900 | 2020-05-02 22:15:03 +0200 | [diff] [blame] | 872 | 1, 4, 101, SSQ_NA, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 873 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 874 | 0, 0, 0, 0, 31, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 875 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 876 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 877 | iosav_run_once(channel, 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 878 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 879 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 880 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 881 | } |
| 882 | } |
| 883 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 884 | static const u32 lane_base[] = { |
| 885 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 886 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 887 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 888 | }; |
| 889 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 890 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 891 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 892 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 893 | int lane; |
| 894 | int slotrank, slot; |
| 895 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 896 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 897 | |
| 898 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 899 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 900 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 901 | } |
| 902 | |
| 903 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 904 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 905 | case 0: |
| 906 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 907 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 908 | break; |
| 909 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 910 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 911 | ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 912 | break; |
| 913 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 914 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 915 | ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 916 | break; |
| 917 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 918 | pi_coding_ctrl[slot] = |
| 919 | (ctrl->timings[channel][2 * slot].pi_coding + |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 920 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 921 | break; |
| 922 | } |
| 923 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 924 | /* Enable CMD XOVER */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 925 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 926 | reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; |
| 927 | reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 928 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 929 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 930 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 931 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 932 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 933 | /* Enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 934 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 935 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 936 | |
| 937 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 938 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 939 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 940 | if (shift < 0) |
| 941 | shift = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 942 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 943 | offset_pi_code = ctrl->pi_code_offset + shift; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 944 | |
| 945 | /* Set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 946 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 947 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 948 | } |
| 949 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 950 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 951 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 952 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 953 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 954 | reg_io_latency &= 0xffff0000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 955 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 956 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 957 | |
| 958 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 959 | int post_timA_min_high = 7, pre_timA_min_high = 7; |
| 960 | int post_timA_max_high = 0, pre_timA_max_high = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 961 | int shift_402x = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 962 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 963 | |
| 964 | if (shift < 0) |
| 965 | shift = 0; |
| 966 | |
| 967 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 968 | post_timA_min_high = MIN(post_timA_min_high, |
| 969 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 970 | timA + shift) >> 6); |
| 971 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 972 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 973 | timA >> 6); |
| 974 | post_timA_max_high = MAX(post_timA_max_high, |
| 975 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 976 | timA + shift) >> 6); |
| 977 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 978 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 979 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 980 | } |
| 981 | |
| 982 | if (pre_timA_max_high - pre_timA_min_high < |
| 983 | post_timA_max_high - post_timA_min_high) |
| 984 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 985 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 986 | else if (pre_timA_max_high - pre_timA_min_high > |
| 987 | post_timA_max_high - post_timA_min_high) |
| 988 | shift_402x = -1; |
| 989 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 990 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 991 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 992 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 993 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 994 | reg_roundtrip_latency |= |
| 995 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 996 | shift_402x) << (8 * slotrank); |
| 997 | |
| 998 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 999 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1000 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1001 | timA + shift) & 0x3f) |
| 1002 | | |
| 1003 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1004 | rising + shift) << 8) |
| 1005 | | |
| 1006 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1007 | timA + shift - |
| 1008 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1009 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1010 | falling + shift) << 20)); |
| 1011 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1012 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1013 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1014 | timC + shift) & 0x3f) |
| 1015 | | |
| 1016 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1017 | timB + shift) & 0x3f) << 8) |
| 1018 | | |
| 1019 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1020 | timB + shift) & 0x1c0) << 9) |
| 1021 | | |
| 1022 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1023 | timC + shift) & 0x40) << 13)); |
| 1024 | } |
| 1025 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1026 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1027 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1028 | } |
| 1029 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1030 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1031 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1032 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1033 | |
| 1034 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1035 | write MR3 MPR enable |
| 1036 | in this mode only RD and RDA are allowed |
| 1037 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1038 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1039 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1040 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1041 | 4, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1042 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1043 | |
| 1044 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1045 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1046 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1047 | 1, 3, 4, SSQ_RD, |
| 1048 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1049 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1050 | |
| 1051 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1052 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1053 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1054 | 15, 4, ctrl->CAS + 36, SSQ_NA, |
| 1055 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1056 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1057 | |
| 1058 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1059 | write MR3 MPR disable */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1060 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1061 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1062 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1063 | 0, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1064 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1065 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1066 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1067 | iosav_run_once(channel, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1068 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1069 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1070 | } |
| 1071 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1072 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1073 | { |
| 1074 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1075 | |
| 1076 | return (MCHBAR32(lane_base[lane] + |
| 1077 | GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1078 | } |
| 1079 | |
| 1080 | struct run { |
| 1081 | int middle; |
| 1082 | int end; |
| 1083 | int start; |
| 1084 | int all; |
| 1085 | int length; |
| 1086 | }; |
| 1087 | |
| 1088 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1089 | { |
| 1090 | int i, ls; |
| 1091 | int bl = 0, bs = 0; |
| 1092 | struct run ret; |
| 1093 | |
| 1094 | ls = 0; |
| 1095 | for (i = 0; i < 2 * sz; i++) |
| 1096 | if (seq[i % sz]) { |
| 1097 | if (i - ls > bl) { |
| 1098 | bl = i - ls; |
| 1099 | bs = ls; |
| 1100 | } |
| 1101 | ls = i + 1; |
| 1102 | } |
| 1103 | if (bl == 0) { |
| 1104 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1105 | ret.start = 0; |
| 1106 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1107 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1108 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1109 | return ret; |
| 1110 | } |
| 1111 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1112 | ret.start = bs % sz; |
| 1113 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1114 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1115 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1116 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1117 | |
| 1118 | return ret; |
| 1119 | } |
| 1120 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1121 | static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1122 | { |
| 1123 | int timA; |
| 1124 | int statistics[NUM_LANES][128]; |
| 1125 | int lane; |
| 1126 | |
| 1127 | for (timA = 0; timA < 128; timA++) { |
| 1128 | FOR_ALL_LANES { |
| 1129 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1130 | } |
| 1131 | program_timings(ctrl, channel); |
| 1132 | |
| 1133 | test_timA(ctrl, channel, slotrank); |
| 1134 | |
| 1135 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1136 | statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1137 | } |
| 1138 | } |
| 1139 | FOR_ALL_LANES { |
| 1140 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1141 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1142 | upperA[lane] = rn.end; |
| 1143 | if (upperA[lane] < rn.middle) |
| 1144 | upperA[lane] += 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1145 | |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1146 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1147 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1148 | } |
| 1149 | } |
| 1150 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1151 | static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1152 | { |
| 1153 | int timA_delta; |
| 1154 | int statistics[NUM_LANES][51]; |
| 1155 | int lane, i; |
| 1156 | |
| 1157 | memset(statistics, 0, sizeof(statistics)); |
| 1158 | |
| 1159 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1160 | |
| 1161 | FOR_ALL_LANES { |
| 1162 | ctrl->timings[channel][slotrank].lanes[lane].timA |
| 1163 | = upperA[lane] + timA_delta + 0x40; |
| 1164 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1165 | program_timings(ctrl, channel); |
| 1166 | |
| 1167 | for (i = 0; i < 100; i++) { |
| 1168 | test_timA(ctrl, channel, slotrank); |
| 1169 | FOR_ALL_LANES { |
| 1170 | statistics[lane][timA_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1171 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1172 | } |
| 1173 | } |
| 1174 | } |
| 1175 | FOR_ALL_LANES { |
| 1176 | int last_zero, first_all; |
| 1177 | |
| 1178 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1179 | if (statistics[lane][last_zero + 25]) |
| 1180 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1181 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1182 | last_zero--; |
| 1183 | for (first_all = -25; first_all <= 25; first_all++) |
| 1184 | if (statistics[lane][first_all + 25] == 100) |
| 1185 | break; |
| 1186 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1187 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1188 | |
| 1189 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1190 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1191 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1192 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1193 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1194 | } |
| 1195 | } |
| 1196 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1197 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1198 | { |
| 1199 | int works[NUM_LANES]; |
| 1200 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1201 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1202 | while (1) { |
| 1203 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1204 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1205 | program_timings(ctrl, channel); |
| 1206 | test_timA(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1207 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1208 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1209 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1210 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1211 | if (works[lane]) |
| 1212 | some_works = 1; |
| 1213 | else |
| 1214 | all_works = 0; |
| 1215 | } |
| 1216 | if (all_works) |
| 1217 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1218 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1219 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1220 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1221 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1222 | channel, slotrank); |
| 1223 | return MAKE_ERR; |
| 1224 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1225 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1226 | printram("4024 -= 2;\n"); |
| 1227 | continue; |
| 1228 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1229 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1230 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1231 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1232 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1233 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1234 | channel, slotrank); |
| 1235 | return MAKE_ERR; |
| 1236 | } |
| 1237 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1238 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1239 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1240 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1241 | } |
| 1242 | } |
| 1243 | return 0; |
| 1244 | } |
| 1245 | |
| 1246 | struct timA_minmax { |
| 1247 | int timA_min_high, timA_max_high; |
| 1248 | }; |
| 1249 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1250 | static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1251 | struct timA_minmax *mnmx) |
| 1252 | { |
| 1253 | int lane; |
| 1254 | mnmx->timA_min_high = 7; |
| 1255 | mnmx->timA_max_high = 0; |
| 1256 | |
| 1257 | FOR_ALL_LANES { |
| 1258 | if (mnmx->timA_min_high > |
| 1259 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1260 | mnmx->timA_min_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1261 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1262 | if (mnmx->timA_max_high < |
| 1263 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1264 | mnmx->timA_max_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1265 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1266 | } |
| 1267 | } |
| 1268 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1269 | static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1270 | struct timA_minmax *mnmx) |
| 1271 | { |
| 1272 | struct timA_minmax post; |
| 1273 | int shift_402x = 0; |
| 1274 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1275 | /* Get changed maxima */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1276 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1277 | |
| 1278 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1279 | post.timA_max_high - post.timA_min_high) |
| 1280 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1281 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1282 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1283 | post.timA_max_high - post.timA_min_high) |
| 1284 | shift_402x = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1285 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1286 | else |
| 1287 | shift_402x = 0; |
| 1288 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1289 | ctrl->timings[channel][slotrank].io_latency += shift_402x; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1290 | ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1291 | printram("4024 += %d;\n", shift_402x); |
| 1292 | printram("4028 += %d;\n", shift_402x); |
| 1293 | } |
| 1294 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1295 | /* |
| 1296 | * Compensate the skew between DQS and DQs. |
| 1297 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1298 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1299 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1300 | * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1301 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1302 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1303 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1304 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1305 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1306 | * DQ in phase the data being read is expected to alternate on every byte: |
| 1307 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1308 | * 0xFF 0x00 0xFF ... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1309 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1310 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1311 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1312 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1313 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1314 | { |
| 1315 | int channel, slotrank, lane; |
| 1316 | int err; |
| 1317 | |
| 1318 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1319 | int all_high, some_high; |
| 1320 | int upperA[NUM_LANES]; |
| 1321 | struct timA_minmax mnmx; |
| 1322 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1323 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1324 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1325 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1326 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1327 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1328 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1329 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1330 | 0, 0, 0, 0, 0, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1331 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1332 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1333 | iosav_run_once(channel, 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1334 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1335 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1336 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1337 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1338 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1339 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1340 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1341 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1342 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1343 | all_high = 1; |
| 1344 | some_high = 0; |
| 1345 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1346 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1347 | some_high = 1; |
| 1348 | else |
| 1349 | all_high = 0; |
| 1350 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1351 | |
| 1352 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1353 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1354 | printram("4028--;\n"); |
| 1355 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1356 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1357 | upperA[lane] -= 0x40; |
| 1358 | |
| 1359 | } |
| 1360 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1361 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1362 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1363 | printram("4024++;\n"); |
| 1364 | printram("4028++;\n"); |
| 1365 | } |
| 1366 | |
| 1367 | program_timings(ctrl, channel); |
| 1368 | |
| 1369 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1370 | |
| 1371 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1372 | if (err) |
| 1373 | return err; |
| 1374 | |
| 1375 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1376 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1377 | |
| 1378 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1379 | |
| 1380 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1381 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1382 | |
| 1383 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1384 | ctrl->timings[channel][slotrank].lanes[lane].timA -= |
| 1385 | mnmx.timA_min_high * 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1386 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1387 | ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1388 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1389 | |
| 1390 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1391 | |
| 1392 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1393 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1394 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1395 | |
| 1396 | printram("final results:\n"); |
| 1397 | FOR_ALL_LANES |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1398 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1399 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1400 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1401 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1402 | |
| 1403 | toggle_io_reset(); |
| 1404 | } |
| 1405 | |
| 1406 | FOR_ALL_POPULATED_CHANNELS { |
| 1407 | program_timings(ctrl, channel); |
| 1408 | } |
| 1409 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1410 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1411 | } |
| 1412 | return 0; |
| 1413 | } |
| 1414 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1415 | static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1416 | { |
| 1417 | int lane; |
| 1418 | |
| 1419 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1420 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1421 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1422 | } |
| 1423 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1424 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1425 | |
| 1426 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1427 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1428 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1429 | 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, |
| 1430 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1431 | 0, 0, 1, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1432 | |
| 1433 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1434 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1435 | IOSAV_NOP, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1436 | 1, 4, 4, SSQ_WR, |
| 1437 | 8, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1438 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1439 | |
| 1440 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1441 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1442 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1443 | 500, 4, 4, SSQ_WR, |
| 1444 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1445 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1446 | |
| 1447 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1448 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1449 | IOSAV_NOP, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1450 | 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, |
| 1451 | 8, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1452 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1453 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1454 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1455 | iosav_run_once(channel, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1456 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1457 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1458 | |
| 1459 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1460 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1461 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1462 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1463 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1464 | 0, 0, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1465 | |
| 1466 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1467 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1468 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1469 | 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->CAS, SSQ_NA, |
| 1470 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1471 | 0, 0, 1, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1472 | |
| 1473 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1474 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1475 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1476 | 500, 4, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 1477 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1478 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1479 | |
| 1480 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1481 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1482 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1483 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1484 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1485 | 0, 0, 0, 0, 18, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1486 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1487 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1488 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1489 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1490 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1491 | } |
| 1492 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1493 | static void timC_threshold_process(int *data, const int count) |
| 1494 | { |
| 1495 | int min = data[0]; |
| 1496 | int max = min; |
| 1497 | int i; |
| 1498 | for (i = 1; i < count; i++) { |
| 1499 | if (min > data[i]) |
| 1500 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1501 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1502 | if (max < data[i]) |
| 1503 | max = data[i]; |
| 1504 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1505 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1506 | for (i = 0; i < count; i++) |
| 1507 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1508 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1509 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1510 | } |
| 1511 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1512 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1513 | { |
| 1514 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1515 | int stats[NUM_LANES][MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1516 | int lane; |
| 1517 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1518 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1519 | |
| 1520 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1521 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1522 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1523 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1524 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1525 | 0, 0, 0, 0, 18, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1526 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1527 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1528 | iosav_run_once(channel, 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1529 | |
| 1530 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1531 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1532 | program_timings(ctrl, channel); |
| 1533 | |
| 1534 | test_timC(ctrl, channel, slotrank); |
| 1535 | |
| 1536 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1537 | stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1538 | } |
| 1539 | } |
| 1540 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1541 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1542 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1543 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1544 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1545 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1546 | /* |
| 1547 | * With command training not being done yet, the lane can be erroneous. |
| 1548 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1549 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1550 | timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1551 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1552 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1553 | if (rn.all || rn.length < 8) { |
| 1554 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1555 | return MAKE_ERR; |
| 1556 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1557 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1558 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1559 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1560 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1561 | } |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1565 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1566 | { |
| 1567 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1568 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1569 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1570 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1571 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1572 | return ret; |
| 1573 | } |
| 1574 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1575 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1576 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1577 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1578 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1579 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1580 | for (j = 0; j < 16; j++) |
| 1581 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1582 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1583 | sfence(); |
| 1584 | } |
| 1585 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1586 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1587 | { |
| 1588 | int ret = 0; |
| 1589 | int channel; |
| 1590 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1591 | return ret; |
| 1592 | } |
| 1593 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1594 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1595 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1596 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1597 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1598 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1599 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1600 | for (j = 0; j < 16; j++) |
| 1601 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1602 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1603 | for (j = 0; j < 16; j++) |
| 1604 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1605 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1606 | sfence(); |
| 1607 | } |
| 1608 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1609 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1610 | { |
| 1611 | int channel, slotrank, lane; |
| 1612 | |
| 1613 | FOR_ALL_POPULATED_CHANNELS { |
| 1614 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1615 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1616 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1617 | } |
| 1618 | |
| 1619 | program_timings(ctrl, channel); |
| 1620 | |
| 1621 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1622 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1623 | |
| 1624 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1625 | write MR3 MPR enable |
| 1626 | in this mode only RD and RDA are allowed |
| 1627 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1628 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1629 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1630 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1631 | 4, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1632 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1633 | |
| 1634 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1635 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1636 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1637 | 3, 4, 4, SSQ_RD, |
| 1638 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1639 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1640 | |
| 1641 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1642 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1643 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1644 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 1645 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1646 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1647 | |
| 1648 | /* DRAM command MRS |
| 1649 | * write MR3 MPR disable */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1650 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1651 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1652 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1653 | 0, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1654 | 0, 0, 0, 0, 0, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1655 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1656 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1657 | iosav_run_once(channel, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1658 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1659 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1660 | } |
| 1661 | |
| 1662 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1663 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 1664 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1665 | } |
| 1666 | |
| 1667 | program_timings(ctrl, channel); |
| 1668 | |
| 1669 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1670 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1671 | /* DRAM command MRS |
| 1672 | * write MR3 MPR enable |
| 1673 | * in this mode only RD and RDA are allowed |
| 1674 | * all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1675 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1676 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1677 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1678 | 4, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1679 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1680 | |
| 1681 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1682 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1683 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1684 | 3, 4, 4, SSQ_RD, |
| 1685 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1686 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1687 | |
| 1688 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1689 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1690 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1691 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 1692 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1693 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1694 | |
| 1695 | /* DRAM command MRS |
| 1696 | * write MR3 MPR disable */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1697 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1698 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1699 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1700 | 0, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1701 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1702 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1703 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1704 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1705 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1706 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1707 | } |
| 1708 | } |
| 1709 | } |
| 1710 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1711 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1712 | { |
| 1713 | /* enable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1714 | write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1715 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1716 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1717 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1718 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1719 | IOSAV_NOP, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1720 | 1, 3, ctrl->CWL + ctrl->tWLO, SSQ_WR, |
| 1721 | 8, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1722 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1723 | |
| 1724 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1725 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1726 | IOSAV_NOP_ALT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1727 | 1, 3, ctrl->CAS + 38, SSQ_RD, |
| 1728 | 4, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1729 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1730 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1731 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1732 | iosav_run_once(channel, 2); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1733 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1734 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1735 | |
| 1736 | /* disable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1737 | write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1738 | } |
| 1739 | |
| 1740 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1741 | { |
| 1742 | int timB; |
| 1743 | int statistics[NUM_LANES][128]; |
| 1744 | int lane; |
| 1745 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1746 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1747 | |
| 1748 | for (timB = 0; timB < 128; timB++) { |
| 1749 | FOR_ALL_LANES { |
| 1750 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1751 | } |
| 1752 | program_timings(ctrl, channel); |
| 1753 | |
| 1754 | test_timB(ctrl, channel, slotrank); |
| 1755 | |
| 1756 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1757 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 1758 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 1759 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1760 | } |
| 1761 | } |
| 1762 | FOR_ALL_LANES { |
| 1763 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1764 | /* |
| 1765 | * timC is a direct function of timB's 6 LSBs. Some tests increments the value |
| 1766 | * of timB by a small value, which might cause the 6-bit value to overflow if |
| 1767 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 1768 | * to overflow, to make sure it won't overflow while running tests and bricks |
| 1769 | * the system due to a non matching timC. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1770 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1771 | * TODO: find out why some tests (edge write discovery) increment timB. |
| 1772 | */ |
| 1773 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1774 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1775 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1776 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1777 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1778 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1779 | if (rn.all) { |
| 1780 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1781 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1782 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1783 | return MAKE_ERR; |
| 1784 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1785 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1786 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1787 | } |
| 1788 | return 0; |
| 1789 | } |
| 1790 | |
| 1791 | static int get_timB_high_adjust(u64 val) |
| 1792 | { |
| 1793 | int i; |
| 1794 | |
| 1795 | /* good */ |
| 1796 | if (val == 0xffffffffffffffffLL) |
| 1797 | return 0; |
| 1798 | |
| 1799 | if (val >= 0xf000000000000000LL) { |
| 1800 | /* needs negative adjustment */ |
| 1801 | for (i = 0; i < 8; i++) |
| 1802 | if (val << (8 * (7 - i) + 4)) |
| 1803 | return -i; |
| 1804 | } else { |
| 1805 | /* needs positive adjustment */ |
| 1806 | for (i = 0; i < 8; i++) |
| 1807 | if (val >> (8 * (7 - i) + 4)) |
| 1808 | return i; |
| 1809 | } |
| 1810 | return 8; |
| 1811 | } |
| 1812 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1813 | static void adjust_high_timB(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1814 | { |
| 1815 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1816 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1817 | FOR_ALL_POPULATED_CHANNELS { |
| 1818 | fill_pattern1(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1819 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1820 | } |
| 1821 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1822 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1823 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1824 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1825 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1826 | |
| 1827 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1828 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1829 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1830 | 1, 3, ctrl->tRCD, SSQ_NA, |
| 1831 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1832 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1833 | |
| 1834 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1835 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1836 | IOSAV_NOP, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1837 | 1, 3, 4, SSQ_WR, |
| 1838 | 8, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1839 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1840 | |
| 1841 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1842 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1843 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1844 | 3, 4, 4, SSQ_WR, |
| 1845 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1846 | 0, 1, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1847 | |
| 1848 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1849 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1850 | IOSAV_NOP, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1851 | 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, |
| 1852 | 8, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1853 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1854 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1855 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1856 | iosav_run_once(channel, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1857 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1858 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1859 | |
| 1860 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1861 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1862 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1863 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1864 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1865 | 0, 0, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1866 | |
| 1867 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1868 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1869 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1870 | 1, 3, ctrl->tRCD, SSQ_NA, |
| 1871 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1872 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1873 | |
| 1874 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1875 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1876 | IOSAV_RD, 3, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1877 | 1, 3, ctrl->tRP + |
| 1878 | ctrl->timings[channel][slotrank].roundtrip_latency + |
| 1879 | ctrl->timings[channel][slotrank].io_latency, SSQ_RD, |
| 1880 | 8, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1881 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1882 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1883 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1884 | iosav_run_once(channel, 3); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1885 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1886 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1887 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1888 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 1889 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1890 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1891 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 1892 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 1893 | get_timB_high_adjust(res) * 64; |
| 1894 | |
| 1895 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1896 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 1897 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1898 | } |
| 1899 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1900 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1901 | } |
| 1902 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1903 | static void write_op(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1904 | { |
| 1905 | int slotrank; |
| 1906 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1907 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1908 | |
| 1909 | /* choose an existing rank. */ |
| 1910 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 1911 | |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 1912 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1913 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1914 | IOSAV_ZQCS, 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1915 | 1, 4, 4, SSQ_NA, |
| 1916 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1917 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1918 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1919 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1920 | iosav_run_once(channel, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1921 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1922 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1923 | } |
| 1924 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1925 | /* |
| 1926 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1927 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1928 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 1929 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 1930 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 1931 | * CLK/ADDR/CMD signals have the same routing delay. |
| 1932 | * |
| 1933 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 1934 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 1935 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1936 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1937 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1938 | { |
| 1939 | int channel, slotrank, lane; |
| 1940 | int err; |
| 1941 | |
| 1942 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1943 | MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1944 | |
| 1945 | FOR_ALL_POPULATED_CHANNELS { |
| 1946 | write_op(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1947 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1948 | } |
| 1949 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1950 | /* Refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1951 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1952 | FOR_ALL_POPULATED_CHANNELS { |
| 1953 | write_op(ctrl, channel); |
| 1954 | } |
| 1955 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1956 | /* Enable write leveling on all ranks |
| 1957 | Disable all DQ outputs |
| 1958 | Only NOP is allowed in this mode */ |
| 1959 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 1960 | write_mrreg(ctrl, channel, slotrank, 1, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1961 | make_mr1(ctrl, slotrank, channel) | 0x1080); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1962 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1963 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1964 | |
| 1965 | toggle_io_reset(); |
| 1966 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1967 | /* Set any valid value for timB, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1968 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1969 | err = discover_timB(ctrl, channel, slotrank); |
| 1970 | if (err) |
| 1971 | return err; |
| 1972 | } |
| 1973 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1974 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1975 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1976 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1977 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1978 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1979 | |
| 1980 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1981 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1982 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1983 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1984 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1985 | |
| 1986 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1987 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); |
| 1988 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 1989 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1990 | |
| 1991 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1992 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1993 | IOSAV_ZQCS, 0, |
Angel Pons | 2be5900 | 2020-05-02 22:15:03 +0200 | [diff] [blame] | 1994 | 1, 4, 101, SSQ_NA, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1995 | 0, 6, 0, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 1996 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1997 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1998 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 1999 | iosav_run_once(channel, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2000 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2001 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2002 | } |
| 2003 | |
| 2004 | toggle_io_reset(); |
| 2005 | |
| 2006 | printram("CPE\n"); |
| 2007 | precharge(ctrl); |
| 2008 | printram("CPF\n"); |
| 2009 | |
| 2010 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2011 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2012 | } |
| 2013 | |
| 2014 | FOR_ALL_POPULATED_CHANNELS { |
| 2015 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2016 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2017 | } |
| 2018 | |
| 2019 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2020 | err = discover_timC(ctrl, channel, slotrank); |
| 2021 | if (err) |
| 2022 | return err; |
| 2023 | } |
| 2024 | |
| 2025 | FOR_ALL_POPULATED_CHANNELS |
| 2026 | program_timings(ctrl, channel); |
| 2027 | |
| 2028 | /* measure and adjust timB timings */ |
| 2029 | adjust_high_timB(ctrl); |
| 2030 | |
| 2031 | FOR_ALL_POPULATED_CHANNELS |
| 2032 | program_timings(ctrl, channel); |
| 2033 | |
| 2034 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2035 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2036 | } |
| 2037 | return 0; |
| 2038 | } |
| 2039 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2040 | static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2041 | { |
| 2042 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2043 | int timC_delta; |
| 2044 | int lanes_ok = 0; |
| 2045 | int ctr = 0; |
| 2046 | int lane; |
| 2047 | |
| 2048 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2049 | FOR_ALL_LANES { |
| 2050 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2051 | saved_rt.lanes[lane].timC + timC_delta; |
| 2052 | } |
| 2053 | program_timings(ctrl, channel); |
| 2054 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2055 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2056 | } |
| 2057 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2058 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2059 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2060 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2061 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2062 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2063 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2064 | 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, |
| 2065 | ctr, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2066 | 0, 0, 1, 0, 18, 0, 0, 0); |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 2067 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2068 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2069 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2070 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2071 | 32, 4, ctrl->CWL + ctrl->tWTR + 8, SSQ_WR, |
| 2072 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2073 | 0, 1, 0, 0, 18, 3, 0, 2); |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2074 | |
Angel Pons | c36cd07 | 2020-05-02 16:51:39 +0200 | [diff] [blame] | 2075 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2076 | |
| 2077 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2078 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2079 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2080 | 32, 4, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 2081 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2082 | 0, 1, 0, 0, 18, 3, 0, 2); |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2083 | |
Angel Pons | c36cd07 | 2020-05-02 16:51:39 +0200 | [diff] [blame] | 2084 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2085 | |
| 2086 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2087 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2088 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2089 | 1, 4, 15, SSQ_NA, |
| 2090 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2091 | 0, 0, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2092 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2093 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2094 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2095 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2096 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2097 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2098 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2099 | |
| 2100 | if (r32 == 0) |
| 2101 | lanes_ok |= 1 << lane; |
| 2102 | } |
| 2103 | ctr++; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2104 | if (lanes_ok == ((1 << ctrl->lanes) - 1)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2105 | break; |
| 2106 | } |
| 2107 | |
| 2108 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2109 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2110 | return lanes_ok != ((1 << ctrl->lanes) - 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2111 | } |
| 2112 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2113 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2114 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2115 | unsigned int i, j; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2116 | unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; |
| 2117 | unsigned int step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2118 | |
| 2119 | if (patno) { |
| 2120 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2121 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2122 | for (i = 0; i < 32; i++) { |
| 2123 | for (j = 0; j < 16; j++) { |
| 2124 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2125 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2126 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2127 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2128 | |
| 2129 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2130 | } |
| 2131 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2132 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2133 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 2134 | for (j = 0; j < 16; j++) { |
| 2135 | const u32 val = pattern[i][j]; |
| 2136 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 2137 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2138 | } |
| 2139 | sfence(); |
| 2140 | } |
| 2141 | } |
| 2142 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2143 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2144 | { |
| 2145 | int channel, slotrank; |
| 2146 | |
| 2147 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2148 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2149 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2150 | /* Choose an existing rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2151 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2152 | |
| 2153 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2154 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2155 | IOSAV_ZQCS, 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2156 | 1, 4, 4, SSQ_NA, |
| 2157 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2158 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2159 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2160 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2161 | iosav_run_once(channel, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2162 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2163 | wait_for_iosav(channel); |
| 2164 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2165 | } |
| 2166 | |
| 2167 | /* refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2168 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2169 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2170 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2171 | |
| 2172 | /* choose an existing rank. */ |
| 2173 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2174 | |
| 2175 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2176 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2177 | IOSAV_ZQCS, 0, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2178 | 1, 4, 4, SSQ_NA, |
| 2179 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2180 | 0, 0, 0, 0, 31, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2181 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2182 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2183 | iosav_run_once(channel, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2184 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2185 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2186 | } |
| 2187 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2188 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2189 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2190 | |
| 2191 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2192 | dram_mrscommands(ctrl); |
| 2193 | |
| 2194 | toggle_io_reset(); |
| 2195 | } |
| 2196 | |
| 2197 | #define MIN_C320C_LEN 13 |
| 2198 | |
| 2199 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2200 | { |
| 2201 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2202 | int slotrank; |
| 2203 | int c320c; |
| 2204 | int stat[NUM_SLOTRANKS][256]; |
| 2205 | int delta = 0; |
| 2206 | |
| 2207 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2208 | |
| 2209 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2210 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2211 | } |
| 2212 | |
| 2213 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2214 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2215 | MCHBAR32(TC_RAP_ch(channel)) = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2216 | (ctrl->tRRD << 0) |
| 2217 | | (ctrl->tRTP << 4) |
| 2218 | | (ctrl->tCKE << 8) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2219 | | (ctrl->tWTR << 12) |
| 2220 | | (ctrl->tFAW << 16) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2221 | | (ctrl->tWR << 24) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2222 | | (ctrl->cmd_stretch[channel] << 30); |
| 2223 | |
| 2224 | if (ctrl->cmd_stretch[channel] == 2) |
| 2225 | delta = 2; |
| 2226 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2227 | delta = 4; |
| 2228 | |
| 2229 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2230 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2231 | } |
| 2232 | |
| 2233 | for (c320c = -127; c320c <= 127; c320c++) { |
| 2234 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2235 | ctrl->timings[channel][slotrank].pi_coding = c320c; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2236 | } |
| 2237 | program_timings(ctrl, channel); |
| 2238 | reprogram_320c(ctrl); |
| 2239 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2240 | stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2241 | } |
| 2242 | } |
| 2243 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2244 | struct run rn = get_longest_zero_run(stat[slotrank], 255); |
| 2245 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2246 | ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2247 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2248 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2249 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2250 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2251 | FOR_ALL_POPULATED_RANKS { |
| 2252 | ctrl->timings[channel][slotrank] = |
| 2253 | saved_timings[channel][slotrank]; |
| 2254 | } |
| 2255 | return MAKE_ERR; |
| 2256 | } |
| 2257 | } |
| 2258 | |
| 2259 | return 0; |
| 2260 | } |
| 2261 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2262 | /* |
| 2263 | * Adjust CMD phase shift and try multiple command rates. |
| 2264 | * A command rate of 2T doubles the time needed for address and command decode. |
| 2265 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2266 | int command_training(ramctr_timing *ctrl) |
| 2267 | { |
| 2268 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2269 | |
| 2270 | FOR_ALL_POPULATED_CHANNELS { |
| 2271 | fill_pattern5(ctrl, channel, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2272 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2273 | } |
| 2274 | |
| 2275 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2276 | int cmdrate, err; |
| 2277 | |
| 2278 | /* |
| 2279 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2280 | * Issue: |
| 2281 | * While c320c discovery seems to succeed raminit will fail in write training. |
| 2282 | * |
| 2283 | * Workaround: |
| 2284 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 2285 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2286 | * |
| 2287 | * Single DIMM per channel: |
| 2288 | * Try command rate 1T and 2T |
| 2289 | */ |
| 2290 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2291 | if (ctrl->tCMD) |
| 2292 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2293 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2294 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2295 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2296 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2297 | |
| 2298 | if (!err) |
| 2299 | break; |
| 2300 | } |
| 2301 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2302 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2303 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2304 | return err; |
| 2305 | } |
| 2306 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2307 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2308 | } |
| 2309 | |
| 2310 | FOR_ALL_POPULATED_CHANNELS |
| 2311 | program_timings(ctrl, channel); |
| 2312 | |
| 2313 | reprogram_320c(ctrl); |
| 2314 | return 0; |
| 2315 | } |
| 2316 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2317 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2318 | { |
| 2319 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2320 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2321 | int lane; |
| 2322 | |
| 2323 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2324 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2325 | ctrl->timings[channel][slotrank].lanes[lane].rising = edge; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2326 | ctrl->timings[channel][slotrank].lanes[lane].falling = edge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2327 | } |
| 2328 | program_timings(ctrl, channel); |
| 2329 | |
| 2330 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2331 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2332 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2333 | } |
| 2334 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2335 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2336 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2337 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2338 | write MR3 MPR enable |
| 2339 | in this mode only RD and RDA are allowed |
| 2340 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2341 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2342 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2343 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2344 | 4, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2345 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2346 | |
| 2347 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2348 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2349 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2350 | 500, 4, 4, SSQ_RD, |
| 2351 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2352 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2353 | |
| 2354 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2355 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2356 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2357 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 2358 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2359 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2360 | |
| 2361 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2362 | MR3 disable MPR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2363 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2364 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2365 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2366 | 0, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2367 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2368 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2369 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2370 | iosav_run_once(channel, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2371 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2372 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2373 | |
| 2374 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2375 | stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2376 | } |
| 2377 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2378 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2379 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2380 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2381 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2382 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2383 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2384 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, |
| 2385 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2386 | return MAKE_ERR; |
| 2387 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2388 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2389 | } |
| 2390 | return 0; |
| 2391 | } |
| 2392 | |
| 2393 | int discover_edges(ramctr_timing *ctrl) |
| 2394 | { |
| 2395 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2396 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2397 | int channel, slotrank, lane; |
| 2398 | int err; |
| 2399 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2400 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2401 | |
| 2402 | toggle_io_reset(); |
| 2403 | |
| 2404 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2405 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2406 | } |
| 2407 | |
| 2408 | FOR_ALL_POPULATED_CHANNELS { |
| 2409 | fill_pattern0(ctrl, channel, 0, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2410 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2411 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2412 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2413 | } |
| 2414 | |
| 2415 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2416 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 2417 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2418 | } |
| 2419 | |
| 2420 | program_timings(ctrl, channel); |
| 2421 | |
| 2422 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2423 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2424 | |
| 2425 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2426 | MR3 enable MPR |
| 2427 | write MR3 MPR enable |
| 2428 | in this mode only RD and RDA are allowed |
| 2429 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2430 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2431 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2432 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2433 | 4, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2434 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2435 | |
| 2436 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2437 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2438 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2439 | 3, 4, 4, SSQ_RD, |
| 2440 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2441 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2442 | |
| 2443 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2444 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2445 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2446 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 2447 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2448 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2449 | |
| 2450 | /* DRAM command MRS |
| 2451 | * MR3 disable MPR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2452 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2453 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2454 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2455 | 0, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2456 | 0, 0, 0, 0, 0, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2457 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2458 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2459 | iosav_run_once(channel, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2460 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2461 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2462 | } |
| 2463 | |
| 2464 | /* XXX: check any measured value ? */ |
| 2465 | |
| 2466 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2467 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2468 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2469 | } |
| 2470 | |
| 2471 | program_timings(ctrl, channel); |
| 2472 | |
| 2473 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2474 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2475 | |
| 2476 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2477 | MR3 enable MPR |
| 2478 | write MR3 MPR enable |
| 2479 | in this mode only RD and RDA are allowed |
| 2480 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2481 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2482 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2483 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2484 | 4, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2485 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2486 | |
| 2487 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2488 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2489 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2490 | 3, 4, 4, SSQ_RD, |
| 2491 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2492 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2493 | |
| 2494 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2495 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2496 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2497 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 2498 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2499 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2500 | |
| 2501 | /* DRAM command MRS |
| 2502 | * MR3 disable MPR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2503 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2504 | IOSAV_MRS, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2505 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2506 | 0, 6, 3, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2507 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2508 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2509 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2510 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2511 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2512 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2513 | } |
| 2514 | |
| 2515 | /* XXX: check any measured value ? */ |
| 2516 | |
| 2517 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2518 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2519 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2520 | } |
| 2521 | |
| 2522 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2523 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2524 | } |
| 2525 | |
Angel Pons | 0c3936e | 2020-03-22 12:49:27 +0100 | [diff] [blame] | 2526 | /* |
| 2527 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2528 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2529 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2530 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2531 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2532 | |
| 2533 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2534 | err = discover_edges_real(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2535 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2536 | if (err) |
| 2537 | return err; |
| 2538 | } |
| 2539 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2540 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2541 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2542 | |
| 2543 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2544 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2545 | rising_edges[channel][slotrank]); |
| 2546 | if (err) |
| 2547 | return err; |
| 2548 | } |
| 2549 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2550 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2551 | |
| 2552 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2553 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2554 | falling_edges[channel][slotrank][lane]; |
| 2555 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2556 | rising_edges[channel][slotrank][lane]; |
| 2557 | } |
| 2558 | |
| 2559 | FOR_ALL_POPULATED_CHANNELS { |
| 2560 | program_timings(ctrl, channel); |
| 2561 | } |
| 2562 | |
| 2563 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2564 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2565 | } |
| 2566 | return 0; |
| 2567 | } |
| 2568 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2569 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2570 | { |
| 2571 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2572 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
| 2573 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2574 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2575 | int lane, i; |
| 2576 | int lower[NUM_LANES]; |
| 2577 | int upper[NUM_LANES]; |
| 2578 | int pat; |
| 2579 | |
| 2580 | FOR_ALL_LANES { |
| 2581 | lower[lane] = 0; |
| 2582 | upper[lane] = MAX_EDGE_TIMING; |
| 2583 | } |
| 2584 | |
| 2585 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2586 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2587 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
| 2588 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2589 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2590 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2591 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2592 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2593 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2594 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2595 | FOR_ALL_LANES { |
| 2596 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2597 | rising = edge; |
| 2598 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2599 | falling = edge; |
| 2600 | } |
| 2601 | program_timings(ctrl, channel); |
| 2602 | |
| 2603 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2604 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2605 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2606 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2607 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2608 | |
| 2609 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2610 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2611 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2612 | 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, |
| 2613 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2614 | 0, 0, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2615 | |
| 2616 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2617 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2618 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2619 | 32, 20, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, |
| 2620 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2621 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2622 | |
| 2623 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2624 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2625 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2626 | 32, 20, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 2627 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2628 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2629 | |
| 2630 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2631 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2632 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2633 | 1, 3, ctrl->tRP, SSQ_NA, |
| 2634 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2635 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2636 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2637 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2638 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2639 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2640 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2641 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2642 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2643 | } |
| 2644 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2645 | /* FIXME: This register only exists on Ivy Bridge */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2646 | raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2647 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2648 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2649 | FOR_ALL_LANES { |
| 2650 | struct run rn; |
| 2651 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2652 | stats[edge] = !!(raw_stats[edge] & (1 << lane)); |
| 2653 | |
| 2654 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 2655 | |
| 2656 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " |
| 2657 | "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, |
| 2658 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2659 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2660 | |
| 2661 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2662 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2663 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2664 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2665 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2666 | printk(BIOS_EMERG, "edge write discovery failed: " |
| 2667 | "%d, %d, %d\n", channel, slotrank, lane); |
| 2668 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2669 | return MAKE_ERR; |
| 2670 | } |
| 2671 | } |
| 2672 | } |
| 2673 | } |
| 2674 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2675 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2676 | printram("CPA\n"); |
| 2677 | return 0; |
| 2678 | } |
| 2679 | |
| 2680 | int discover_edges_write(ramctr_timing *ctrl) |
| 2681 | { |
| 2682 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2683 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2684 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2685 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2686 | /* |
| 2687 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2688 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2689 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2690 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2691 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2692 | |
| 2693 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2694 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2695 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2696 | if (err) |
| 2697 | return err; |
| 2698 | } |
| 2699 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2700 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2701 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2702 | |
| 2703 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2704 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2705 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2706 | if (err) |
| 2707 | return err; |
| 2708 | } |
| 2709 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2710 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2711 | |
| 2712 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2713 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2714 | falling_edges[channel][slotrank][lane]; |
| 2715 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2716 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2717 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2718 | } |
| 2719 | |
| 2720 | FOR_ALL_POPULATED_CHANNELS |
| 2721 | program_timings(ctrl, channel); |
| 2722 | |
| 2723 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2724 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2725 | } |
| 2726 | return 0; |
| 2727 | } |
| 2728 | |
| 2729 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2730 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2731 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2732 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2733 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2734 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2735 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2736 | 4, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, |
| 2737 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2738 | 0, 0, 1, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2739 | |
| 2740 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2741 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2742 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2743 | 480, 4, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, |
| 2744 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2745 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2746 | |
| 2747 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2748 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2749 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2750 | 480, 4, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 2751 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2752 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2753 | |
| 2754 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2755 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2756 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2757 | 1, 4, ctrl->tRP, SSQ_NA, |
| 2758 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2759 | 0, 0, 0, 0, 0, 0, 0, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2760 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2761 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2762 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2763 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2764 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2765 | } |
| 2766 | |
| 2767 | int discover_timC_write(ramctr_timing *ctrl) |
| 2768 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2769 | const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2770 | int i, pat; |
| 2771 | |
| 2772 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2773 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2774 | int channel, slotrank, lane; |
| 2775 | |
| 2776 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2777 | lower[channel][slotrank][lane] = 0; |
| 2778 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2779 | } |
| 2780 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2781 | /* |
| 2782 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2783 | * FIXME: This must only be done on Ivy Bridge. |
| 2784 | */ |
| 2785 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2786 | printram("discover timC write:\n"); |
| 2787 | |
| 2788 | for (i = 0; i < 3; i++) |
| 2789 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2790 | |
| 2791 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
| 2792 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), |
| 2793 | ~0x3f000000, rege3c_b24[i] << 24); |
| 2794 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2795 | udelay(2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2796 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2797 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2798 | FOR_ALL_POPULATED_RANKS { |
| 2799 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2800 | u32 raw_stats[MAX_TIMC + 1]; |
| 2801 | int stats[MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2802 | |
| 2803 | /* Make sure rn.start < rn.end */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2804 | stats[MAX_TIMC] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2805 | |
| 2806 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2807 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
| 2808 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2809 | for (timC = 0; timC < MAX_TIMC; timC++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2810 | FOR_ALL_LANES { |
| 2811 | ctrl->timings[channel][slotrank] |
| 2812 | .lanes[lane].timC = timC; |
| 2813 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2814 | program_timings(ctrl, channel); |
| 2815 | |
| 2816 | test_timC_write (ctrl, channel, slotrank); |
| 2817 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2818 | /* FIXME: Another IVB-only register! */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2819 | raw_stats[timC] = MCHBAR32( |
| 2820 | IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2821 | } |
| 2822 | FOR_ALL_LANES { |
| 2823 | struct run rn; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2824 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2825 | stats[timC] = !!(raw_stats[timC] |
| 2826 | & (1 << lane)); |
| 2827 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2828 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2829 | rn = get_longest_zero_run(stats, MAX_TIMC + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2830 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2831 | printk(BIOS_EMERG, |
| 2832 | "timC write discovery failed: " |
| 2833 | "%d, %d, %d\n", channel, |
| 2834 | slotrank, lane); |
| 2835 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2836 | return MAKE_ERR; |
| 2837 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2838 | printram("timC: %d, %d, %d: " |
| 2839 | "0x%02x-0x%02x-0x%02x, " |
| 2840 | "0x%02x-0x%02x\n", channel, slotrank, |
| 2841 | i, rn.start, rn.middle, rn.end, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2842 | rn.start + ctrl->timC_offset[i], |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2843 | rn.end - ctrl->timC_offset[i]); |
| 2844 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2845 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2846 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2847 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2848 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2849 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2850 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2851 | upper[channel][slotrank][lane]); |
| 2852 | |
| 2853 | } |
| 2854 | } |
| 2855 | } |
| 2856 | } |
| 2857 | |
| 2858 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2859 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2860 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2861 | udelay(2); |
| 2862 | } |
| 2863 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2864 | /* |
| 2865 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2866 | * FIXME: This must only be done on Ivy Bridge. |
| 2867 | */ |
| 2868 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2869 | |
| 2870 | printram("CPB\n"); |
| 2871 | |
| 2872 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2873 | printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2874 | (lower[channel][slotrank][lane] + |
| 2875 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2876 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2877 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2878 | (lower[channel][slotrank][lane] + |
| 2879 | upper[channel][slotrank][lane]) / 2; |
| 2880 | } |
| 2881 | FOR_ALL_POPULATED_CHANNELS { |
| 2882 | program_timings(ctrl, channel); |
| 2883 | } |
| 2884 | return 0; |
| 2885 | } |
| 2886 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2887 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2888 | { |
| 2889 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2890 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2891 | |
| 2892 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2893 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2894 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2895 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2896 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2897 | printram("normalize %d, %d, %d: mat %d\n", |
| 2898 | channel, slotrank, lane, mat); |
| 2899 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2900 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2901 | printram("normalize %d, %d, %d: delta %d\n", |
| 2902 | channel, slotrank, lane, delta); |
| 2903 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2904 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2905 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2906 | } |
| 2907 | |
| 2908 | FOR_ALL_POPULATED_CHANNELS { |
| 2909 | program_timings(ctrl, channel); |
| 2910 | } |
| 2911 | } |
| 2912 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2913 | void write_controller_mr(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2914 | { |
| 2915 | int channel, slotrank; |
| 2916 | |
| 2917 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2918 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2919 | make_mr0(ctrl, slotrank); |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2920 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2921 | make_mr1(ctrl, slotrank, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2922 | } |
| 2923 | } |
| 2924 | |
| 2925 | int channel_test(ramctr_timing *ctrl) |
| 2926 | { |
| 2927 | int channel, slotrank, lane; |
| 2928 | |
| 2929 | slotrank = 0; |
| 2930 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2931 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2932 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2933 | return MAKE_ERR; |
| 2934 | } |
| 2935 | FOR_ALL_POPULATED_CHANNELS { |
| 2936 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
| 2937 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2938 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2939 | } |
| 2940 | |
| 2941 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 2942 | FOR_ALL_CHANNELS |
| 2943 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 2944 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2945 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 2946 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2947 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2948 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2949 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2950 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2951 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2952 | IOSAV_ACT, 1, |
Angel Pons | 2be5900 | 2020-05-02 22:15:03 +0200 | [diff] [blame] | 2953 | 4, 8, 40, SSQ_NA, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2954 | 0, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2955 | 0, 0, 1, 0, 18, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2956 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2957 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2958 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2959 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2960 | 100, 4, 40, SSQ_WR, |
| 2961 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2962 | 0, 1, 0, 0, 18, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2963 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2964 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2965 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2966 | IOSAV_RD, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2967 | 100, 4, 40, SSQ_RD, |
| 2968 | 0, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2969 | 0, 1, 0, 0, 18, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2970 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2971 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2972 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2973 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2974 | 1, 3, 40, SSQ_NA, |
| 2975 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 2976 | 0, 0, 0, 0, 18, 0, 0, 0); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2977 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2978 | /* Execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 2979 | iosav_run_once(channel, 4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2980 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2981 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2982 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2983 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2984 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 2985 | channel, slotrank, lane); |
| 2986 | return MAKE_ERR; |
| 2987 | } |
| 2988 | } |
| 2989 | return 0; |
| 2990 | } |
| 2991 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2992 | void channel_scrub(ramctr_timing *ctrl) |
| 2993 | { |
| 2994 | int channel, slotrank, row, rowsize; |
| 2995 | |
| 2996 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2997 | rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; |
| 2998 | for (row = 0; row < rowsize; row += 16) { |
| 2999 | |
| 3000 | wait_for_iosav(channel); |
| 3001 | |
| 3002 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 3003 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 3004 | IOSAV_ACT, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 3005 | 1, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, |
| 3006 | row, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 3007 | 1, 0, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 3008 | |
| 3009 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 3010 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 3011 | IOSAV_WR, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 3012 | 129, 4, 40, SSQ_WR, |
| 3013 | row, 0, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 3014 | 0, 1, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 3015 | |
| 3016 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 3017 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 3018 | IOSAV_PRE, 1, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 3019 | 1, 3, 40, SSQ_NA, |
| 3020 | 1024, 6, 0, slotrank, |
Angel Pons | b631d07 | 2020-05-02 20:00:32 +0200 | [diff] [blame] | 3021 | 0, 0, 0, 0, 18, 0, 0, 0); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 3022 | |
| 3023 | /* execute command queue */ |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 3024 | iosav_run_once(channel, 3); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 3025 | |
| 3026 | wait_for_iosav(channel); |
| 3027 | } |
| 3028 | } |
| 3029 | } |
| 3030 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3031 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3032 | { |
| 3033 | int channel; |
| 3034 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3035 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3036 | static u32 seeds[NUM_CHANNELS][3] = { |
| 3037 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 3038 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 3039 | }; |
| 3040 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3041 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3042 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 3043 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 3044 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3045 | } |
| 3046 | } |
| 3047 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 3048 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3049 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3050 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3051 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3052 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3053 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3054 | } |
| 3055 | } |
| 3056 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3057 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3058 | { |
| 3059 | int channel; |
| 3060 | |
| 3061 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3062 | /* Always drive command bus */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3063 | MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3064 | } |
| 3065 | |
| 3066 | udelay(1); |
| 3067 | |
| 3068 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3069 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3070 | } |
| 3071 | } |
| 3072 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3073 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3074 | { |
| 3075 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3076 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3077 | FOR_ALL_POPULATED_CHANNELS { |
| 3078 | u32 b20, b4_8_12; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3079 | int min_pi = 10000; |
| 3080 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3081 | |
| 3082 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3083 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 3084 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3085 | } |
| 3086 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3087 | b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3088 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3089 | b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3090 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3091 | dram_odt_stretch(ctrl, channel); |
| 3092 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3093 | MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 3094 | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3095 | } |
| 3096 | } |
| 3097 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3098 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3099 | { |
| 3100 | int channel; |
| 3101 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3102 | MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; |
| 3103 | MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3104 | } |
| 3105 | } |
| 3106 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3107 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 3108 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3109 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3110 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3111 | } |
| 3112 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3113 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3114 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3115 | { |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3116 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
| 3117 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3118 | int channel; |
| 3119 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 3120 | int t3_ns; |
| 3121 | u32 r32; |
| 3122 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3123 | /* FIXME: This register only exists on Ivy Bridge */ |
| 3124 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3125 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3126 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3127 | MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3128 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3129 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3130 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3131 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3132 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3133 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3134 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3135 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3136 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3137 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3138 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3139 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 3140 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3141 | |
| 3142 | FOR_ALL_CHANNELS { |
| 3143 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3144 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3145 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3146 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3147 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3148 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3149 | case 1: |
| 3150 | case 4: |
| 3151 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3152 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3153 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3154 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3155 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3156 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3157 | break; |
| 3158 | } |
| 3159 | } |
| 3160 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3161 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3162 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3163 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3164 | |
| 3165 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3166 | MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3167 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3168 | MCHBAR32_OR(MC_INIT_STATE_G, 1); |
| 3169 | MCHBAR32_OR(MC_INIT_STATE_G, 0x80); |
| 3170 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3171 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3172 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3173 | FOR_ALL_POPULATED_CHANNELS |
| 3174 | break; |
| 3175 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3176 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 3177 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3178 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3179 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3180 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3181 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3182 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3183 | t1_ns += 500; |
| 3184 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3185 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3186 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3187 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3188 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3189 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3190 | t3_ns = 500; |
| 3191 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3192 | |
| 3193 | /* The graphics driver will use these watermark values */ |
| 3194 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
| 3195 | MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, |
| 3196 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 3197 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3198 | } |
| 3199 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3200 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3201 | { |
| 3202 | int channel, slotrank, lane; |
| 3203 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3204 | FOR_ALL_POPULATED_CHANNELS { |
| 3205 | MCHBAR32(TC_RAP_ch(channel)) = |
| 3206 | (ctrl->tRRD << 0) |
| 3207 | | (ctrl->tRTP << 4) |
| 3208 | | (ctrl->tCKE << 8) |
| 3209 | | (ctrl->tWTR << 12) |
| 3210 | | (ctrl->tFAW << 16) |
| 3211 | | (ctrl->tWR << 24) |
| 3212 | | (ctrl->cmd_stretch[channel] << 30); |
| 3213 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3214 | |
| 3215 | udelay(1); |
| 3216 | |
| 3217 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3218 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3219 | } |
| 3220 | |
| 3221 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3222 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3223 | } |
| 3224 | |
| 3225 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3226 | MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3227 | |
| 3228 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3229 | udelay(1); |
| 3230 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3231 | } |
| 3232 | |
| 3233 | printram("CPE\n"); |
| 3234 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3235 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 3236 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3237 | |
| 3238 | printram("CP5b\n"); |
| 3239 | |
| 3240 | FOR_ALL_POPULATED_CHANNELS { |
| 3241 | program_timings(ctrl, channel); |
| 3242 | } |
| 3243 | |
| 3244 | u32 reg, addr; |
| 3245 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3246 | /* Poll for RCOMP */ |
| 3247 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 3248 | ; |
| 3249 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3250 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3251 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3252 | } while ((reg & 0x14) == 0); |
| 3253 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3254 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3255 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3256 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3257 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3258 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3259 | udelay(500); |
| 3260 | |
| 3261 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3262 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3263 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3264 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3265 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3266 | MCHBAR32(addr) = reg; |
| 3267 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3268 | /* Wait 10ns for ranks to settle */ |
| 3269 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3270 | |
| 3271 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3272 | MCHBAR32(addr) = reg; |
| 3273 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3274 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3275 | write_reset(ctrl); |
| 3276 | } |
| 3277 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3278 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3279 | dram_mrscommands(ctrl); |
| 3280 | |
| 3281 | printram("CP5c\n"); |
| 3282 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3283 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3284 | |
| 3285 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3286 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3287 | udelay(2); |
| 3288 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3289 | } |