Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 5 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 15 | */ |
| 16 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 17 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 18 | #include <AGESA.h> |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 19 | #include <northbridge/amd/agesa/state_machine.h> |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 20 | #include <PlatformMemoryConfiguration.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 21 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 22 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
| 23 | /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ |
| 24 | { |
| 25 | 0, |
| 26 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 27 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 28 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 29 | 4, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 30 | HotplugDisabled, |
| 31 | PcieGen2, |
| 32 | PcieGen2, |
| 33 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 34 | 46) |
| 35 | }, |
| 36 | /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ |
| 37 | { |
| 38 | 0, |
| 39 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 40 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 41 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 42 | 5, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 43 | HotplugDisabled, |
| 44 | PcieGen2, |
| 45 | PcieGen2, |
| 46 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 47 | 46) |
| 48 | }, |
| 49 | /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ |
| 50 | { |
| 51 | 0, |
| 52 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 53 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 54 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 55 | 6, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 56 | HotplugDisabled, |
| 57 | PcieGen2, |
| 58 | PcieGen2, |
| 59 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 60 | 46) |
| 61 | }, |
| 62 | /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ |
| 63 | { |
| 64 | 0, |
| 65 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 66 | PCIE_PORT_DATA_INITIALIZER(PortDisabled, |
| 67 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 68 | 7, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 69 | HotplugDisabled, |
| 70 | PcieGen2, |
| 71 | PcieGen2, |
| 72 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 73 | 0) |
| 74 | }, |
| 75 | /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ |
| 76 | { |
| 77 | DESCRIPTOR_TERMINATE_LIST, |
| 78 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 79 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 80 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 81 | 8, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame^] | 82 | HotplugDisabled, |
| 83 | PcieGen2, |
| 84 | PcieGen2, |
| 85 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 86 | 0) |
| 87 | } |
| 88 | }; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 89 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 90 | static const PCIe_DDI_DESCRIPTOR DdiList[] = { |
| 91 | /* (DDI interface Lanes 8:11, DdA, ...) */ |
| 92 | { |
| 93 | 0, |
| 94 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), |
| 95 | /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */ |
| 96 | {ConnectorTypeLvds, Aux1, Hdp1} |
| 97 | }, |
| 98 | /* (DDI interface Lanes 12:15, DdB, ...) */ |
| 99 | { |
| 100 | DESCRIPTOR_TERMINATE_LIST, |
| 101 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), |
| 102 | /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */ |
| 103 | {ConnectorTypeDP, Aux2, Hdp2} |
| 104 | } |
| 105 | }; |
| 106 | |
| 107 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 108 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 109 | .SocketId = 0, |
| 110 | .PciePortList = PortList, |
| 111 | .DdiLinkList = DdiList, |
| 112 | }; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 113 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 114 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 115 | { |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 116 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
| 117 | InitEarly->GnbConfig.PsppPolicy = 0; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 118 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 119 | |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 120 | /** |
| 121 | * @brief Customer Overides Memory Table |
| 122 | * |
| 123 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform |
| 124 | * information to AGESA |
| 125 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). |
| 126 | * If PlatformSpecificTable is populated, AGESA will base its settings on the |
| 127 | * data from the table. Otherwise, it will use its default conservative settings. |
| 128 | */ |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 129 | static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 130 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), |
| 131 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 132 | PSO_END |
| 133 | }; |
| 134 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 135 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 136 | { |
| 137 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 138 | } |