Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 5 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 21 | #include "PlatformGnbPcieComplex.h" |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 22 | |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 23 | #include <string.h> |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 24 | #include <northbridge/amd/agesa/agesawrapper.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 25 | #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> |
| 26 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 27 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 28 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 29 | /** |
| 30 | * OemCustomizeInitEarly |
| 31 | * |
| 32 | * Description: |
| 33 | * This stub function will call the host environment through the binary block |
| 34 | * interface (call-out port) to provide a user hook opportunity |
| 35 | * |
| 36 | * Parameters: |
| 37 | * @param[in] **PeiServices |
| 38 | * @param[in] *InitEarly |
| 39 | * |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 40 | **/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame^] | 41 | |
| 42 | static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 43 | { |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 44 | AGESA_STATUS Status; |
| 45 | void *BrazosPcieComplexListPtr; |
| 46 | void *BrazosPciePortPtr; |
| 47 | void *BrazosPcieDdiPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 48 | |
| 49 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 50 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 51 | /** |
| 52 | * @brief Initialize Port descriptors |
| 53 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 54 | PCIe_PORT_DESCRIPTOR PortList [] = { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 55 | /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 56 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 57 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 58 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 59 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, |
| 60 | GNB_GPP_PORT4_CHANNEL_TYPE, |
| 61 | 4, |
| 62 | GNB_GPP_PORT4_HOTPLUG_SUPPORT, |
| 63 | GNB_GPP_PORT4_SPEED_MODE, |
| 64 | GNB_GPP_PORT4_SPEED_MODE, |
| 65 | GNB_GPP_PORT4_LINK_ASPM, |
| 66 | 46) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 67 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 68 | /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 69 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 70 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 71 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 72 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, |
| 73 | GNB_GPP_PORT5_CHANNEL_TYPE, |
| 74 | 5, |
| 75 | GNB_GPP_PORT5_HOTPLUG_SUPPORT, |
| 76 | GNB_GPP_PORT5_SPEED_MODE, |
| 77 | GNB_GPP_PORT5_SPEED_MODE, |
| 78 | GNB_GPP_PORT5_LINK_ASPM, |
| 79 | 46) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 80 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 81 | /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 82 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 83 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 84 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 85 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, |
| 86 | GNB_GPP_PORT6_CHANNEL_TYPE, |
| 87 | 6, |
| 88 | GNB_GPP_PORT6_HOTPLUG_SUPPORT, |
| 89 | GNB_GPP_PORT6_SPEED_MODE, |
| 90 | GNB_GPP_PORT6_SPEED_MODE, |
| 91 | GNB_GPP_PORT6_LINK_ASPM, |
| 92 | 46) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 93 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 94 | /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 95 | { |
| 96 | 0, |
| 97 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 98 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, |
| 99 | GNB_GPP_PORT7_CHANNEL_TYPE, |
| 100 | 7, |
| 101 | GNB_GPP_PORT7_HOTPLUG_SUPPORT, |
| 102 | GNB_GPP_PORT7_SPEED_MODE, |
| 103 | GNB_GPP_PORT7_SPEED_MODE, |
| 104 | GNB_GPP_PORT7_LINK_ASPM, |
| 105 | 0) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 106 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 107 | /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 108 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 109 | /* Descriptor flags. IMPORTANT! Terminate last element of array */ |
| 110 | DESCRIPTOR_TERMINATE_LIST, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 111 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 112 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, |
| 113 | GNB_GPP_PORT8_CHANNEL_TYPE, |
| 114 | 8, |
| 115 | GNB_GPP_PORT8_HOTPLUG_SUPPORT, |
| 116 | GNB_GPP_PORT8_SPEED_MODE, |
| 117 | GNB_GPP_PORT8_SPEED_MODE, |
| 118 | GNB_GPP_PORT8_LINK_ASPM, |
| 119 | 0) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 120 | } |
| 121 | }; |
| 122 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 123 | /** |
| 124 | * @brief Initialize Ddi descriptors |
| 125 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 126 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 127 | /* (DDI interface Lanes 8:11, DdA, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 128 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 129 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 130 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 131 | /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 132 | {ConnectorTypeLvds, Aux1, Hdp1} |
| 133 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 134 | /* (DDI interface Lanes 12:15, DdB, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 135 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 136 | /* Descriptor flags. IMPORTANT! Terminate last element of array */ |
| 137 | DESCRIPTOR_TERMINATE_LIST, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 138 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 139 | /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 140 | {ConnectorTypeDP, Aux2, Hdp2} |
| 141 | } |
| 142 | }; |
| 143 | |
| 144 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 145 | DESCRIPTOR_TERMINATE_LIST, |
| 146 | 0, |
| 147 | &PortList[0], |
| 148 | &DdiList[0] |
| 149 | }; |
| 150 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 151 | /** |
| 152 | * @brief GNB PCIe topology Porting |
| 153 | * |
| 154 | * Allocate buffer for |
| 155 | * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 156 | */ |
| 157 | AllocHeapParams.RequestedBufferSize = |
| 158 | sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 159 | |
| 160 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 161 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 162 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 163 | ASSERT(Status == AGESA_SUCCESS); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 164 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 165 | BrazosPcieComplexListPtr = |
| 166 | (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 167 | |
| 168 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 169 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 170 | |
| 171 | AllocHeapParams.BufferPtr += sizeof(PortList); |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 172 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 173 | |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 174 | memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); |
| 175 | memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); |
| 176 | memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 177 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 178 | ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = |
| 179 | (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; |
| 180 | ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = |
| 181 | (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 182 | |
| 183 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 184 | InitEarly->GnbConfig.PsppPolicy = 0; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame^] | 185 | return AGESA_SUCCESS; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 186 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame^] | 187 | |
| 188 | const struct OEM_HOOK OemCustomize = { |
| 189 | .InitEarly = OemInitEarly, |
| 190 | }; |