AGESA f14: Drop PlatformGnbPcieComplex.h
These were OEM configurations hidden inside a header file, notation
was already dropped for f15tb and f16kb.
Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
index d2d9202..73f5c2c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include "PlatformGnbPcieComplex.h"
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -25,65 +24,65 @@
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
- GNB_GPP_PORT4_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
4,
- GNB_GPP_PORT4_HOTPLUG_SUPPORT,
- GNB_GPP_PORT4_SPEED_MODE,
- GNB_GPP_PORT4_SPEED_MODE,
- GNB_GPP_PORT4_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
46)
},
/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
- GNB_GPP_PORT5_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
5,
- GNB_GPP_PORT5_HOTPLUG_SUPPORT,
- GNB_GPP_PORT5_SPEED_MODE,
- GNB_GPP_PORT5_SPEED_MODE,
- GNB_GPP_PORT5_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
46)
},
/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
- GNB_GPP_PORT6_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
6,
- GNB_GPP_PORT6_HOTPLUG_SUPPORT,
- GNB_GPP_PORT6_SPEED_MODE,
- GNB_GPP_PORT6_SPEED_MODE,
- GNB_GPP_PORT6_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
46)
},
/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
- GNB_GPP_PORT7_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled,
+ ChannelTypeExt6db,
7,
- GNB_GPP_PORT7_HOTPLUG_SUPPORT,
- GNB_GPP_PORT7_SPEED_MODE,
- GNB_GPP_PORT7_SPEED_MODE,
- GNB_GPP_PORT7_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
0)
},
/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
- GNB_GPP_PORT8_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
8,
- GNB_GPP_PORT8_HOTPLUG_SUPPORT,
- GNB_GPP_PORT8_SPEED_MODE,
- GNB_GPP_PORT8_SPEED_MODE,
- GNB_GPP_PORT8_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
0)
}
};