Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 20 | #include "PlatformGnbPcieComplex.h" |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 21 | #include "BiosCallOuts.h" |
| 22 | |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame^] | 23 | #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> |
| 24 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 25 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 26 | |
| 27 | /*---------------------------------------------------------------------------------------*/ |
| 28 | /** |
| 29 | * OemCustomizeInitEarly |
| 30 | * |
| 31 | * Description: |
| 32 | * This stub function will call the host environment through the binary block |
| 33 | * interface (call-out port) to provide a user hook opportunity |
| 34 | * |
| 35 | * Parameters: |
| 36 | * @param[in] **PeiServices |
| 37 | * @param[in] *InitEarly |
| 38 | * |
| 39 | * @retval VOID |
| 40 | * |
| 41 | **/ |
| 42 | /*---------------------------------------------------------------------------------------*/ |
| 43 | VOID |
| 44 | OemCustomizeInitEarly ( |
| 45 | IN OUT AMD_EARLY_PARAMS *InitEarly |
| 46 | ) |
| 47 | { |
| 48 | AGESA_STATUS Status; |
| 49 | VOID *BrazosPcieComplexListPtr; |
| 50 | VOID *BrazosPciePortPtr; |
| 51 | VOID *BrazosPcieDdiPtr; |
| 52 | |
| 53 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 54 | |
| 55 | PCIe_PORT_DESCRIPTOR PortList [] = { |
| 56 | // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) |
| 57 | { |
| 58 | 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 59 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
| 60 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) |
| 61 | }, |
| 62 | // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) |
| 63 | { |
| 64 | 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 65 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), |
| 66 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) |
| 67 | }, |
| 68 | // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) |
| 69 | { |
| 70 | 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 71 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
| 72 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) |
| 73 | }, |
| 74 | // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) |
| 75 | { |
| 76 | 0, |
| 77 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
| 78 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) |
| 79 | }, |
| 80 | // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) |
| 81 | { |
| 82 | DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 83 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
| 84 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) |
| 85 | } |
| 86 | }; |
| 87 | |
| 88 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
| 89 | // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) |
| 90 | { |
| 91 | 0, //Descriptor flags |
| 92 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
| 93 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) |
| 94 | {ConnectorTypeLvds, Aux1, Hdp1} |
| 95 | }, |
| 96 | // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) |
| 97 | { |
| 98 | DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 99 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
| 100 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) |
| 101 | {ConnectorTypeDP, Aux2, Hdp2} |
| 102 | } |
| 103 | }; |
| 104 | |
| 105 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 106 | DESCRIPTOR_TERMINATE_LIST, |
| 107 | 0, |
| 108 | &PortList[0], |
| 109 | &DdiList[0] |
| 110 | }; |
| 111 | |
| 112 | // GNB PCIe topology Porting |
| 113 | |
| 114 | // |
| 115 | // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 116 | // |
| 117 | AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
| 118 | |
| 119 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 120 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 121 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
| 122 | if ( Status!= AGESA_SUCCESS) { |
| 123 | // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 124 | ASSERT(FALSE); |
| 125 | return; |
| 126 | } |
| 127 | |
| 128 | BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 129 | |
| 130 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
| 131 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; |
| 132 | |
| 133 | AllocHeapParams.BufferPtr += sizeof(PortList); |
| 134 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 135 | |
| 136 | LibAmdMemFill (BrazosPcieComplexListPtr, |
| 137 | 0, |
| 138 | sizeof(Brazos), |
| 139 | &InitEarly->StdHeader); |
| 140 | |
| 141 | LibAmdMemFill (BrazosPciePortPtr, |
| 142 | 0, |
| 143 | sizeof(PortList), |
| 144 | &InitEarly->StdHeader); |
| 145 | |
| 146 | LibAmdMemFill (BrazosPcieDdiPtr, |
| 147 | 0, |
| 148 | sizeof(DdiList), |
| 149 | &InitEarly->StdHeader); |
| 150 | |
| 151 | LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); |
| 152 | LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); |
| 153 | LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); |
| 154 | |
| 155 | |
| 156 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; |
| 157 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; |
| 158 | |
| 159 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
| 160 | InitEarly->GnbConfig.PsppPolicy = 0; |
| 161 | } |