Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 5 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 15 | */ |
| 16 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 17 | #include "PlatformGnbPcieComplex.h" |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 18 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame^] | 19 | #include <AGESA.h> |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 20 | #include <northbridge/amd/agesa/state_machine.h> |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 21 | #include <PlatformMemoryConfiguration.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 22 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame^] | 23 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
| 24 | /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ |
| 25 | { |
| 26 | 0, |
| 27 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), |
| 28 | PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, |
| 29 | GNB_GPP_PORT4_CHANNEL_TYPE, |
| 30 | 4, |
| 31 | GNB_GPP_PORT4_HOTPLUG_SUPPORT, |
| 32 | GNB_GPP_PORT4_SPEED_MODE, |
| 33 | GNB_GPP_PORT4_SPEED_MODE, |
| 34 | GNB_GPP_PORT4_LINK_ASPM, |
| 35 | 46) |
| 36 | }, |
| 37 | /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ |
| 38 | { |
| 39 | 0, |
| 40 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), |
| 41 | PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, |
| 42 | GNB_GPP_PORT5_CHANNEL_TYPE, |
| 43 | 5, |
| 44 | GNB_GPP_PORT5_HOTPLUG_SUPPORT, |
| 45 | GNB_GPP_PORT5_SPEED_MODE, |
| 46 | GNB_GPP_PORT5_SPEED_MODE, |
| 47 | GNB_GPP_PORT5_LINK_ASPM, |
| 48 | 46) |
| 49 | }, |
| 50 | /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ |
| 51 | { |
| 52 | 0, |
| 53 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), |
| 54 | PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, |
| 55 | GNB_GPP_PORT6_CHANNEL_TYPE, |
| 56 | 6, |
| 57 | GNB_GPP_PORT6_HOTPLUG_SUPPORT, |
| 58 | GNB_GPP_PORT6_SPEED_MODE, |
| 59 | GNB_GPP_PORT6_SPEED_MODE, |
| 60 | GNB_GPP_PORT6_LINK_ASPM, |
| 61 | 46) |
| 62 | }, |
| 63 | /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ |
| 64 | { |
| 65 | 0, |
| 66 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), |
| 67 | PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, |
| 68 | GNB_GPP_PORT7_CHANNEL_TYPE, |
| 69 | 7, |
| 70 | GNB_GPP_PORT7_HOTPLUG_SUPPORT, |
| 71 | GNB_GPP_PORT7_SPEED_MODE, |
| 72 | GNB_GPP_PORT7_SPEED_MODE, |
| 73 | GNB_GPP_PORT7_LINK_ASPM, |
| 74 | 0) |
| 75 | }, |
| 76 | /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ |
| 77 | { |
| 78 | DESCRIPTOR_TERMINATE_LIST, |
| 79 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), |
| 80 | PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, |
| 81 | GNB_GPP_PORT8_CHANNEL_TYPE, |
| 82 | 8, |
| 83 | GNB_GPP_PORT8_HOTPLUG_SUPPORT, |
| 84 | GNB_GPP_PORT8_SPEED_MODE, |
| 85 | GNB_GPP_PORT8_SPEED_MODE, |
| 86 | GNB_GPP_PORT8_LINK_ASPM, |
| 87 | 0) |
| 88 | } |
| 89 | }; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 90 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame^] | 91 | static const PCIe_DDI_DESCRIPTOR DdiList[] = { |
| 92 | /* (DDI interface Lanes 8:11, DdA, ...) */ |
| 93 | { |
| 94 | 0, |
| 95 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), |
| 96 | /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */ |
| 97 | {ConnectorTypeLvds, Aux1, Hdp1} |
| 98 | }, |
| 99 | /* (DDI interface Lanes 12:15, DdB, ...) */ |
| 100 | { |
| 101 | DESCRIPTOR_TERMINATE_LIST, |
| 102 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), |
| 103 | /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */ |
| 104 | {ConnectorTypeDP, Aux2, Hdp2} |
| 105 | } |
| 106 | }; |
| 107 | |
| 108 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 109 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 110 | .SocketId = 0, |
| 111 | .PciePortList = PortList, |
| 112 | .DdiLinkList = DdiList, |
| 113 | }; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 114 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 115 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 116 | { |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame^] | 117 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
| 118 | InitEarly->GnbConfig.PsppPolicy = 0; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 119 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 120 | |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 121 | /** |
| 122 | * @brief Customer Overides Memory Table |
| 123 | * |
| 124 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform |
| 125 | * information to AGESA |
| 126 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). |
| 127 | * If PlatformSpecificTable is populated, AGESA will base its settings on the |
| 128 | * data from the table. Otherwise, it will use its default conservative settings. |
| 129 | */ |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 130 | static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 131 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), |
| 132 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 133 | PSO_END |
| 134 | }; |
| 135 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 136 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 137 | { |
| 138 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 139 | } |