commit e52738b42889a8bf6b96fe86b87fbdd73947b367
author Kyösti Mälkki <kyosti.malkki@gmail.com> Thu Sep 21 12:32:43 2017 +0300
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Tue Sep 26 08:36:05 2017 +0000
tree ab3ddcc914b9ab69fdb793ba42e30480d9a8824f
parent e1dced4561ed3b7bff98984c1d51b8e84f004b47

AGESA binaryPI boards: Fix some whitespace

Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c

diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
index 6b039f7..c0fd960 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
@@ -46,12 +46,12 @@
 /**
  * @brief Initialize Port descriptors
  */
-PCIe_PORT_DESCRIPTOR PortList [] = {
+PCIe_PORT_DESCRIPTOR PortList[] = {
 		/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
 		{
 			0,
-			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT,
+			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
 							GNB_GPP_PORT4_CHANNEL_TYPE,
 							4,
 							GNB_GPP_PORT4_HOTPLUG_SUPPORT,
@@ -63,8 +63,8 @@
 		/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
 		{
 			0,
-			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT,
+			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
 							GNB_GPP_PORT5_CHANNEL_TYPE,
 							5,
 							GNB_GPP_PORT5_HOTPLUG_SUPPORT,
@@ -76,8 +76,8 @@
 		/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
 		{
 			0,
-			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT,
+			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
 							GNB_GPP_PORT6_CHANNEL_TYPE,
 							6,
 							GNB_GPP_PORT6_HOTPLUG_SUPPORT,
@@ -89,8 +89,8 @@
 		/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
 		{
 			0,
-			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT,
+			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
 							GNB_GPP_PORT7_CHANNEL_TYPE,
 							7,
 							GNB_GPP_PORT7_HOTPLUG_SUPPORT,
@@ -102,8 +102,8 @@
 		/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
 		{
 			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT,
+			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
 							GNB_GPP_PORT8_CHANNEL_TYPE,
 							8,
 							GNB_GPP_PORT8_HOTPLUG_SUPPORT,
@@ -117,19 +117,19 @@
 /**
  * @brief Initialize Ddi descriptors
  */
-PCIe_DDI_DESCRIPTOR DdiList [] = {
+PCIe_DDI_DESCRIPTOR DdiList[] = {
 		/* (DDI interface Lanes 8:11, DdA, ...) */
 		{
 			0,
-			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-			/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */
+			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+			/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
 			{ConnectorTypeLvds, Aux1, Hdp1}
 		},
 		/* (DDI interface Lanes 12:15, DdB, ...) */
 		{
 			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-			/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */
+			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+			/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
 			{ConnectorTypeDP, Aux2, Hdp2}
 		}
 };
@@ -187,8 +187,8 @@
  * data from the table. Otherwise, it will use its default conservative settings.
  */
 static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
 	PSO_END
 };