Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 5 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 15 | */ |
| 16 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 17 | #include "PlatformGnbPcieComplex.h" |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 18 | |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 19 | #include <string.h> |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame^] | 20 | #include <northbridge/amd/agesa/state_machine.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 21 | #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 22 | #include <PlatformMemoryConfiguration.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 23 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 24 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 25 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 26 | /** |
| 27 | * OemCustomizeInitEarly |
| 28 | * |
| 29 | * Description: |
| 30 | * This stub function will call the host environment through the binary block |
| 31 | * interface (call-out port) to provide a user hook opportunity |
| 32 | * |
| 33 | * Parameters: |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 34 | * @param[in] *InitEarly |
| 35 | * |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 36 | **/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 37 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame^] | 38 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 39 | { |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 40 | AGESA_STATUS Status; |
| 41 | void *BrazosPcieComplexListPtr; |
| 42 | void *BrazosPciePortPtr; |
| 43 | void *BrazosPcieDdiPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 44 | |
| 45 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 46 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 47 | /** |
| 48 | * @brief Initialize Port descriptors |
| 49 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 50 | PCIe_PORT_DESCRIPTOR PortList [] = { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 51 | /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 52 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 53 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 54 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 55 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, |
| 56 | GNB_GPP_PORT4_CHANNEL_TYPE, |
| 57 | 4, |
| 58 | GNB_GPP_PORT4_HOTPLUG_SUPPORT, |
| 59 | GNB_GPP_PORT4_SPEED_MODE, |
| 60 | GNB_GPP_PORT4_SPEED_MODE, |
| 61 | GNB_GPP_PORT4_LINK_ASPM, |
| 62 | 46) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 63 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 64 | /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 65 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 66 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 67 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 68 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, |
| 69 | GNB_GPP_PORT5_CHANNEL_TYPE, |
| 70 | 5, |
| 71 | GNB_GPP_PORT5_HOTPLUG_SUPPORT, |
| 72 | GNB_GPP_PORT5_SPEED_MODE, |
| 73 | GNB_GPP_PORT5_SPEED_MODE, |
| 74 | GNB_GPP_PORT5_LINK_ASPM, |
| 75 | 46) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 76 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 77 | /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 78 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 79 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 80 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 81 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, |
| 82 | GNB_GPP_PORT6_CHANNEL_TYPE, |
| 83 | 6, |
| 84 | GNB_GPP_PORT6_HOTPLUG_SUPPORT, |
| 85 | GNB_GPP_PORT6_SPEED_MODE, |
| 86 | GNB_GPP_PORT6_SPEED_MODE, |
| 87 | GNB_GPP_PORT6_LINK_ASPM, |
| 88 | 46) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 89 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 90 | /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 91 | { |
| 92 | 0, |
| 93 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 94 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, |
| 95 | GNB_GPP_PORT7_CHANNEL_TYPE, |
| 96 | 7, |
| 97 | GNB_GPP_PORT7_HOTPLUG_SUPPORT, |
| 98 | GNB_GPP_PORT7_SPEED_MODE, |
| 99 | GNB_GPP_PORT7_SPEED_MODE, |
| 100 | GNB_GPP_PORT7_LINK_ASPM, |
| 101 | 0) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 102 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 103 | /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 104 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 105 | DESCRIPTOR_TERMINATE_LIST, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 106 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 107 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, |
| 108 | GNB_GPP_PORT8_CHANNEL_TYPE, |
| 109 | 8, |
| 110 | GNB_GPP_PORT8_HOTPLUG_SUPPORT, |
| 111 | GNB_GPP_PORT8_SPEED_MODE, |
| 112 | GNB_GPP_PORT8_SPEED_MODE, |
| 113 | GNB_GPP_PORT8_LINK_ASPM, |
| 114 | 0) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 115 | } |
| 116 | }; |
| 117 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 118 | /** |
| 119 | * @brief Initialize Ddi descriptors |
| 120 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 121 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 122 | /* (DDI interface Lanes 8:11, DdA, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 123 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 124 | 0, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 125 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 126 | /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 127 | {ConnectorTypeLvds, Aux1, Hdp1} |
| 128 | }, |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 129 | /* (DDI interface Lanes 12:15, DdB, ...) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 130 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 131 | DESCRIPTOR_TERMINATE_LIST, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 132 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 133 | /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 134 | {ConnectorTypeDP, Aux2, Hdp2} |
| 135 | } |
| 136 | }; |
| 137 | |
| 138 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 139 | DESCRIPTOR_TERMINATE_LIST, |
| 140 | 0, |
| 141 | &PortList[0], |
| 142 | &DdiList[0] |
| 143 | }; |
| 144 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 145 | /** |
| 146 | * @brief GNB PCIe topology Porting |
| 147 | * |
| 148 | * Allocate buffer for |
| 149 | * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 150 | */ |
| 151 | AllocHeapParams.RequestedBufferSize = |
| 152 | sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 153 | |
| 154 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 155 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 156 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 157 | ASSERT(Status == AGESA_SUCCESS); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 158 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 159 | BrazosPcieComplexListPtr = |
| 160 | (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 161 | |
| 162 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 163 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 164 | |
| 165 | AllocHeapParams.BufferPtr += sizeof(PortList); |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 166 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 167 | |
Edward O'Callaghan | e2f3bfc | 2014-04-11 12:56:13 +1000 | [diff] [blame] | 168 | memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); |
| 169 | memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); |
| 170 | memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 171 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 172 | ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = |
| 173 | (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; |
| 174 | ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = |
| 175 | (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 176 | |
| 177 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 178 | InitEarly->GnbConfig.PsppPolicy = 0; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 179 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 180 | |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 181 | /** |
| 182 | * @brief Customer Overides Memory Table |
| 183 | * |
| 184 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform |
| 185 | * information to AGESA |
| 186 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). |
| 187 | * If PlatformSpecificTable is populated, AGESA will base its settings on the |
| 188 | * data from the table. Otherwise, it will use its default conservative settings. |
| 189 | */ |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame^] | 190 | static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 191 | NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), |
| 192 | NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), |
| 193 | PSO_END |
| 194 | }; |
| 195 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame^] | 196 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 197 | { |
| 198 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 199 | } |