Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 3 | #include <arch/romstage.h> |
Arthur Heymans | 8a1b94c | 2019-05-25 09:47:01 +0200 | [diff] [blame] | 4 | #include <arch/symbols.h> |
Julius Werner | 5358467 | 2021-01-11 16:44:06 -0800 | [diff] [blame] | 5 | #include <cbfs.h> |
Kyösti Mälkki | 8f23b5d | 2019-06-30 21:00:07 +0300 | [diff] [blame] | 6 | #include <cbmem.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 7 | #include <console/console.h> |
Elyes HAOUAS | 2195f7a | 2019-06-21 07:20:12 +0200 | [diff] [blame] | 8 | #include <commonlib/helpers.h> |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 9 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 10 | #include <fsp/car.h> |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 11 | #include <fsp/util.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 12 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 13 | void fill_postcar_frame(struct postcar_frame *pcf) |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 14 | { |
Kyösti Mälkki | 8f23b5d | 2019-06-30 21:00:07 +0300 | [diff] [blame] | 15 | uintptr_t top_of_ram; |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 16 | |
Kyösti Mälkki | 8f23b5d | 2019-06-30 21:00:07 +0300 | [diff] [blame] | 17 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 18 | * above top of the ram. This satisfies MTRR alignment requirement |
| 19 | * with different TSEG size configurations. */ |
| 20 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 21 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 22 | } |
| 23 | |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 24 | /* This is the romstage entry called from cpu/intel/car/romstage.c */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 25 | void mainboard_romstage_entry(void) |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 26 | { |
| 27 | /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram |
| 28 | * is still enabled. We can directly access work buffer here. */ |
Julius Werner | 5358467 | 2021-01-11 16:44:06 -0800 | [diff] [blame] | 29 | void *fsp = cbfs_map("fsp.bin", NULL); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 30 | |
Julius Werner | 5358467 | 2021-01-11 16:44:06 -0800 | [diff] [blame] | 31 | if (!fsp) |
Jacob Garber | f7f90f7 | 2019-05-28 15:37:37 -0600 | [diff] [blame] | 32 | die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); |
| 33 | |
| 34 | /* This leaks a mapping which this code assumes is benign as |
| 35 | * the flash is memory mapped CPU's address space. */ |
Julius Werner | 5358467 | 2021-01-11 16:44:06 -0800 | [diff] [blame] | 36 | FSP_INFO_HEADER *fih = find_fsp((uintptr_t)fsp); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 37 | |
John Zhao | d3a7328 | 2019-05-31 09:58:49 -0700 | [diff] [blame] | 38 | if (!fih) |
| 39 | die("Invalid FSP header\n"); |
| 40 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 41 | cache_as_ram_stage_main(fih); |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 42 | } |